remove ssvoffs from SVSTATE

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 84a662db1caf598f6a33c961180b787fa9c69f85..3b0d3956ff8b8dc3fedb8387db8661b9c642a2ca 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -526,9 +526,7 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       state.sv().srcoffs  = std::min(srcoffs , state.sv().vl-1);
       state.sv().destoffs = std::min(destoffs, state.sv().vl-1);
       // decode (and limit) src/dest SUBVL offsets
-      reg_t subsrcoffs = get_field(val, SV_STATE_SSVOFFS);
       reg_t subdestoffs = get_field(val, SV_STATE_DSVOFFS);
-      state.sv().ssvoffs  = std::min(subsrcoffs , state.sv().subvl-1);
       state.sv().dsvoffs = std::min(subdestoffs, state.sv().subvl-1);
       //int state_bank = get_field(val, SV_STATE_BANK);
       //int state_size = get_field(val, SV_STATE_SIZE);
@@ -911,8 +909,7 @@ reg_t processor_t::get_csr(int which)
              (state.sv().srcoffs<<12)     |
              (state.sv().destoffs<<18) |
              ((std::max((int)state.sv().subvl, 1)-1)<<24)   |
-             (state.sv().ssvoffs<<26)     |
-             (state.sv().dsvoffs<<28);
+             (state.sv().dsvoffs<<26);
     case CSR_SV_MVL:
       return state.sv().mvl;
     case CSR_SV_SUBVL:

diff --git a/riscv/processor.h b/riscv/processor.h
index 4d4bf81fdaed569f1b558568911524bc01f94066..4a4d4fd4f758c8a5585592a8da9302bfbc1458cd 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -99,8 +99,7 @@ typedef struct
 
   // subvector loop
   uint64_t subvl;
-  int dsvoffs; // destination sub-loop element offset
-  int ssvoffs;  // source sub-loop element offset (used in twin-predication)
+  int dsvoffs; // sub-loop element offset
 
   int state_size;
   int state_bank;

diff --git a/riscv/sv.h b/riscv/sv.h
index 2a9cf4f254d58af6de311e0119c331c0294d4ee1..0521df3863e9e7a34d1fe474e6f6a651018d06bb 100644 (file)
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -113,8 +113,7 @@ typedef struct {
 #define SV_STATE_SRCOFFS (0x1f<<12)
 #define SV_STATE_DESTOFFS (0x1f<<18)
 #define SV_STATE_SUBVL (0x3<<24)
-#define SV_STATE_SSVOFFS (0x3<<26)
-#define SV_STATE_DSVOFFS (0x3<<28)
+#define SV_STATE_DSVOFFS (0x3<<26)
 
 #define SV_CFG_BANK (0x7)
 #define SV_CFG_SIZE (0x3<<3)