fhdl: replication support

diff --git a/migen/fhdl/convtools.py b/migen/fhdl/convtools.py
index f8051749d445799ee647d6855b7059ed0a7c05b1..f9798b5d44d2d450616f1f6a8ca68145912fa688 100644 (file)
--- a/migen/fhdl/convtools.py
+++ b/migen/fhdl/convtools.py
@@ -37,6 +37,8 @@ def ListSignals(node):
        elif isinstance(node, Cat):
                l = list(map(ListSignals, node.l))
                return set().union(*l)
+       elif isinstance(node, Replicate):
+               return ListSignals(node.v)
        elif isinstance(node, Assign):
                return ListSignals(node.l) | ListSignals(node.r)
        elif isinstance(node, StatementList):
@@ -60,6 +62,8 @@ def ListTargets(node):
        elif isinstance(node, Cat):
                l = list(map(ListTargets, node.l))
                return set().union(*l)
+       elif isinstance(node, Replicate):
+               return ListTargets(node.v)
        elif isinstance(node, Assign):
                return ListTargets(node.l)
        elif isinstance(node, StatementList):

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index f1ecb0e4c144d851cb5316c83ca624ab9fffc832..a1a49526ab46fb7101cd6a7eb71644e427930542 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -1,17 +1,20 @@
 import math
 
 def BitsFor(n):
-       if n == 0:
-               return 1
+       if isinstance(n, Constant):
+               return n.bv.width
        else:
-               return int(math.ceil(math.log(n+1, 2)))
+               if n == 0:
+                       return 1
+               else:
+                       return int(math.ceil(math.log(n+1, 2)))
 
 class BV:
        def __init__(self, width=1, signed=False):
                self.width = width
                self.signed = signed
        
-       def __str__(self):
+       def __repr__(self):
                r = str(self.width) + "'"
                if self.signed:
                        r += "s"
@@ -98,10 +101,18 @@ class Cat(Value):
        def __init__(self, *args):
                self.l = list(map(_cst, args))
 
+class Replicate(Value):
+       def __init__(self, v, n):
+               self.v = v
+               self.n = n
+
 class Constant(Value):
        def __init__(self, n, bv=None):
                self.bv = bv or BV(BitsFor(n))
                self.n = n
+       
+       def __repr__(self):
+               return str(self.bv) + str(self.n)
 
 def _cst(x):
        if isinstance(x, int):

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index c403e897924791c0633038fee59c464afaba8a33..7f386cb8bda73b1cdd629ce39c23d071adef1ecc 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -39,6 +39,8 @@ def _printexpr(ns, node):
                l = list(map(partial(_printexpr, ns), node.l))
                l.reverse()
                return "{" + ", ".join(l) + "}"
+       elif isinstance(node, Replicate):
+               return "{" + str(node.n) + "{" + _printexpr(ns, node.v) + "}}"
        else:
                raise TypeError