class AMDGPUTargetMachine;
// R600 Passes
+FunctionPass* createR600KernelParametersPass(const TargetData* TD);
FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS);
FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
-#===-- AMDGPUGenInstrEnums.pl - TODO: Add brief description -------===#
+#===-- AMDGPUGenInstrEnums.pl - Script for generating instruction enums ----===#
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
-#===----------------------------------------------------------------------===#
+#===-----------------------------------------------------------------------===#
#
-# TODO: Add full description
+# This perl script is used to generate the following files:
#
-#===----------------------------------------------------------------------===#
+# 1. perl AMDGPUGenInstrEnums.pl td > AMDGPUInstrEnums.td
+#
+# This file contains Tablegen constants used for matching hw instructions
+# from R600 and SI with functionally similar AMDIL instruction. It aslo
+# contains definitions of floating point constants like pi (in hex notation)
+# that are used in some of the shader patterns.
+#
+# 2. perl AMDGPUGenInstrEnums.pl h > AMDGPUInstrEnums.h
+#
+# This file contains cpp enums that match the constant values in
+# AMDGPUInstrEnums.td
+#
+# 3. perl AMDGPUGenInstrEnums.pl inc > AMDGPUInstrEnums.include
+#
+# This file contains a function called GetRealAMDILOpcode which maps the
+# constant values defined in AMDGPUInstrEnums.h to the corresponding AMDIL
+# instructions.
+#===-----------------------------------------------------------------------===#
use warnings;
use strict;
-//===-- AMDGPUInstructions.td - TODO: Add brief description -------===//
+//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// This file contains instruction defs that are common to all hw codegen
+// targets.
//
//===----------------------------------------------------------------------===//
-//===-- AMDGPUIntrinsics.td - TODO: Add brief description -------===//
+//===-- AMDGPUIntrinsics.td - Common intrinsics -*- tablegen -*-----------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// This file defines intrinsics that are used by all hw codegen targets.
//
//===----------------------------------------------------------------------===//
-//===-- AMDGPURegisterInfo.h - TODO: Add brief description -------===//
+//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// This file contains the TargetRegisterInfo interface that is implemented
+// by all hw codegen targets.
//
//===----------------------------------------------------------------------===//
-//===-- AMDGPURegisterInfo.td - TODO: Add brief description -------===//
+//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// Tablegen register definitions common to all hw codegen targets.
//
//===----------------------------------------------------------------------===//
#include "AMDILTargetMachine.h"
#include "R600ISelLowering.h"
#include "R600InstrInfo.h"
-#include "R600KernelParameters.h"
#include "SIISelLowering.h"
#include "SIInstrInfo.h"
#include "llvm/Analysis/Passes.h"
-//===-- AMDGPUTargetMachine.h - TODO: Add brief description -------===//
+//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// The AMDGPU TargetMachine interface definition for hw codgen targets.
//
//===----------------------------------------------------------------------===//
-//===-- AMDIL.td - TODO: Add brief description -------===//
+//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDIL7XXDevice.cpp - TODO: Add brief description -------===//
+//===-- AMDIL7XXDevice.cpp - Device Info for 7XX GPUs ---------------------===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/ADT/SCCIterator.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/Analysis/DominatorInternals.h"
+#include "llvm/Analysis/Dominators.h"
+#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#define FirstNonDebugInstr(A) A->begin()
using namespace llvm;
-// bixia TODO: move this out to analysis lib. Make this work for both target
-// AMDIL and CBackend.
// TODO: move-begin.
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#include "AMDILTargetMachine.h"
-#include "AMDILUtilityFunctions.h"
-#include "llvm/ADT/SCCIterator.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Analysis/DominatorInternals.h"
-#include "llvm/Analysis/Dominators.h"
-#include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionAnalysis.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-
namespace llvm {
/// PostDominatorTree Class - Concrete subclass of DominatorTree that is used
-// The LLVM Compiler Infrastructure
+//===-- AMDILCodeEmitter.h - AMDIL Code Emitter interface -----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
-//===-- AMDILCodeEmitter.h - TODO: Add brief description -------===//
-//===-- AMDILCodeEmitter.h - TODO: Add brief description -------===//
-//===-- AMDILCodeEmitter.h - TODO: Add brief description -------===//
+//===----------------------------------------------------------------------===//
//
-// The LLVM Compiler Infrastructure
+// CodeEmitter interface for R600 and SI codegen.
//
+//===----------------------------------------------------------------------===//
#ifndef AMDILCODEEMITTER_H
#define AMDILCODEEMITTER_H
namespace llvm {
- /* XXX: Temp HACK to work around tablegen name generation */
class AMDILCodeEmitter {
public:
uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
-//===-- AMDILConversions.td - TODO: Add brief description -------===//
+//==- AMDILConversions.td - Type conversion tablegen patterns -*-tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILDevice.cpp - TODO: Add brief description -------===//
+//===-- AMDILDevice.cpp - Base class for AMDIL Devices --------------------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILDeviceInfo.cpp - TODO: Add brief description -------===//
+//===-- AMDILDeviceInfo.cpp - AMDILDeviceInfo class -----------------------===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//==-----------------------------------------------------------------------===//
+//
+// Function that creates DeviceInfo from a device name and other information.
+//
+//==-----------------------------------------------------------------------===//
#include "AMDILDevices.h"
#include "AMDILSubtarget.h"
using namespace llvm;
namespace llvm {
+namespace AMDILDeviceInfo {
AMDILDevice*
getDeviceFromName(const std::string &deviceName, AMDILSubtarget *ptr, bool is64bit, bool is64on32bit)
{
return new AMDIL7XXDevice(ptr);
}
}
-}
+} // End namespace AMDILDeviceInfo
+} // End namespace llvm
-//===-- AMDILDeviceInfo.h - TODO: Add brief description -------===//
+//===-- AMDILDeviceInfo.h - Constants for describing devices --------------===//
//
// The LLVM Compiler Infrastructure
//
};
+ AMDILDevice*
+ getDeviceFromName(const std::string &name, AMDILSubtarget *ptr, bool is64bit = false, bool is64on32bit = false);
} // namespace AMDILDeviceInfo
- llvm::AMDILDevice*
- getDeviceFromName(const std::string &name, llvm::AMDILSubtarget *ptr, bool is64bit = false, bool is64on32bit = false);
} // namespace llvm
#endif // _AMDILDEVICEINFO_H_
-//===-- AMDILDevices.h - TODO: Add brief description -------===//
+//===-- AMDILDevices.h - Consolidate AMDIL Device headers -----------------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILEnumeratedTypes.td - TODO: Add brief description -------===//
+//===-- AMDILEnumeratedTypes.td - IL Type definitions --*- tablegen -*-----===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILEvergreenDevice.cpp - TODO: Add brief description -------===//
+//===-- AMDILEvergreenDevice.cpp - Device Info for Evergreen --------------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILInstructions.td - TODO: Add brief description -------===//
+//===-- AMDILInstructions.td - AMDIL Instruction definitions --------------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILMultiClass.td - TODO: Add brief description -------===//
+//===-- AMDILMultiClass.td - AMDIL Multiclass defs ---*- tablegen -*-------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILNIDevice.cpp - TODO: Add brief description -------===//
+//===-- AMDILNIDevice.cpp - Device Info for Northern Islands devices ------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILPeepholeOptimizer.cpp - TODO: Add brief description -------===//
+//===-- AMDILPeepholeOptimizer.cpp - AMDIL Peephole optimizations ---------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILSIDevice.cpp - TODO: Add brief description -------===//
+//===-- AMDILSIDevice.cpp - Device Info for Southern Islands GPUs ---------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
-//==-----------------------------------------------------------------------===//\r
-#include "AMDILSIDevice.h"\r
-#include "AMDILEvergreenDevice.h"\r
-#include "AMDILNIDevice.h"\r
-#include "AMDILSubtarget.h"\r
+//==-----------------------------------------------------------------------===//
+#include "AMDILSIDevice.h"
+#include "AMDILEvergreenDevice.h"
+#include "AMDILNIDevice.h"
+#include "AMDILSubtarget.h"
-using namespace llvm;\r
-\r
-AMDILSIDevice::AMDILSIDevice(AMDILSubtarget *ST)\r
- : AMDILEvergreenDevice(ST)\r
-{\r
-}\r
-AMDILSIDevice::~AMDILSIDevice()\r
-{\r
-}\r
-\r
-size_t\r
-AMDILSIDevice::getMaxLDSSize() const\r
-{\r
- if (usesHardware(AMDILDeviceInfo::LocalMem)) {\r
- return MAX_LDS_SIZE_900;\r
- } else {\r
- return 0;\r
- }\r
-}\r
-\r
-uint32_t\r
-AMDILSIDevice::getGeneration() const\r
-{\r
- return AMDILDeviceInfo::HD7XXX;\r
-}\r
-\r
-std::string\r
-AMDILSIDevice::getDataLayout() const\r
-{\r
- return std::string("e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16"\r
- "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"\r
- "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"\r
- "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"\r
- "-v512:512:512-v1024:1024:1024-v2048:2048:2048"\r
- "-n8:16:32:64");\r
-}\r
+using namespace llvm;
+
+AMDILSIDevice::AMDILSIDevice(AMDILSubtarget *ST)
+ : AMDILEvergreenDevice(ST)
+{
+}
+AMDILSIDevice::~AMDILSIDevice()
+{
+}
+
+size_t
+AMDILSIDevice::getMaxLDSSize() const
+{
+ if (usesHardware(AMDILDeviceInfo::LocalMem)) {
+ return MAX_LDS_SIZE_900;
+ } else {
+ return 0;
+ }
+}
+
+uint32_t
+AMDILSIDevice::getGeneration() const
+{
+ return AMDILDeviceInfo::HD7XXX;
+}
+
+std::string
+AMDILSIDevice::getDataLayout() const
+{
+ return std::string("e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16"
+ "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
+ "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
+ "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
+ "-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+ "-n8:16:32:64");
+}
-//===------- AMDILSIDevice.h - Define SI Device for AMDIL -*- C++ -*------===//\r
+//===------- AMDILSIDevice.h - Define SI Device for AMDIL -*- C++ -*------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
-//==-----------------------------------------------------------------------===//\r
-//\r
-// Interface for the subtarget data classes.\r
-//\r
-//===---------------------------------------------------------------------===//\r
-// This file will define the interface that each generation needs to\r
-// implement in order to correctly answer queries on the capabilities of the\r
+//==-----------------------------------------------------------------------===//
+//
+// Interface for the subtarget data classes.
+//
+//===---------------------------------------------------------------------===//
+// This file will define the interface that each generation needs to
+// implement in order to correctly answer queries on the capabilities of the
// specific hardware.\r
-//===---------------------------------------------------------------------===//\r
-#ifndef _AMDILSIDEVICE_H_\r
-#define _AMDILSIDEVICE_H_\r
-#include "AMDILEvergreenDevice.h"\r
-#include "AMDILSubtarget.h"\r
+//===---------------------------------------------------------------------===//
+#ifndef _AMDILSIDEVICE_H_
+#define _AMDILSIDEVICE_H_
+#include "AMDILEvergreenDevice.h"
+#include "AMDILSubtarget.h"
+
+namespace llvm {
+ class AMDILSubtarget;
+//===---------------------------------------------------------------------===//
+// SI generation of devices and their respective sub classes
+//===---------------------------------------------------------------------===//
+
+// The AMDILSIDevice is the base class for all Northern Island series of
+// cards. It is very similiar to the AMDILEvergreenDevice, with the major
+// exception being differences in wavefront size and hardware capabilities. The
+// SI devices are all 64 wide wavefronts and also add support for signed 24 bit
+// integer operations
+
+ class AMDILSIDevice : public AMDILEvergreenDevice {
+ public:
+ AMDILSIDevice(AMDILSubtarget*);
+ virtual ~AMDILSIDevice();
+ virtual size_t getMaxLDSSize() const;
+ virtual uint32_t getGeneration() const;
+ virtual std::string getDataLayout() const;
+ protected:
+ }; // AMDILSIDevice
-namespace llvm {\r
- class AMDILSubtarget;\r
-//===---------------------------------------------------------------------===//\r
-// SI generation of devices and their respective sub classes\r
-//===---------------------------------------------------------------------===//\r
-\r
-// The AMDILSIDevice is the base class for all Northern Island series of\r
-// cards. It is very similiar to the AMDILEvergreenDevice, with the major\r
-// exception being differences in wavefront size and hardware capabilities. The\r
-// SI devices are all 64 wide wavefronts and also add support for signed 24 bit\r
-// integer operations\r
-\r
- class AMDILSIDevice : public AMDILEvergreenDevice {\r
- public:\r
- AMDILSIDevice(AMDILSubtarget*);\r
- virtual ~AMDILSIDevice();\r
- virtual size_t getMaxLDSSize() const;\r
- virtual uint32_t getGeneration() const;\r
- virtual std::string getDataLayout() const;\r
- protected:\r
- }; // AMDILSIDevice\r
-\r
-} // namespace llvm\r
-#endif // _AMDILSIDEVICE_H_\r
+} // namespace llvm
+#endif // _AMDILSIDEVICE_H_
}
#endif
mDevName = GPU;
- mDevice = getDeviceFromName(mDevName, this, mIs64bit);
+ mDevice = AMDILDeviceInfo::getDeviceFromName(mDevName, this, mIs64bit);
}
AMDILSubtarget::~AMDILSubtarget()
{
-//===-- AMDILTokenDesc.td - TODO: Add brief description -------===//
+//===-- AMDILTokenDesc.td - AMDIL Token Definitions --*- tablegen -*-----===//
//
// The LLVM Compiler Infrastructure
//
-//===-- AMDILVersion.td - TODO: Add brief description -------===//
+//===-- AMDILVersion.td - Barrier Instruction/Intrinsic definitions------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- R600CodeEmitter.cpp - TODO: Add brief description -------===//
+//===-- R600CodeEmitter.cpp - Code Emitter for R600->Cayman GPU families --===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// This code emitters outputs bytecode that is understood by the r600g driver
+// in the Mesa [1] project. The bytecode is very similar to the hardware's ISA,
+// except that the size of the instruction fields are rounded up to the
+// nearest byte.
+//
+// [1] http://www.mesa3d.org/
//
//===----------------------------------------------------------------------===//
-#===-- R600GenRegisterInfo.pl - TODO: Add brief description -------===#
+#===-- R600GenRegisterInfo.pl - Script for generating register info files --===#
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
-#===----------------------------------------------------------------------===#
+#===------------------------------------------------------------------------===#
#
-# TODO: Add full description
+# This perl script prints to stdout .td code to be used as R600RegisterInfo.td
+# it also generates a file called R600HwRegInfo.include, which contains helper
+# functions for determining the hw encoding of registers.
#
-#===----------------------------------------------------------------------===#
+#===------------------------------------------------------------------------===#
use strict;
use warnings;
-//===-- R600ISelLowering.cpp - TODO: Add brief description -------===//
+//===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// Most of the DAG lowering is handled in AMDILISelLowering.cpp. This file
+// is mostly EmitInstrWithCustomInserter().
//
//===----------------------------------------------------------------------===//
switch (MI->getOpcode()) {
default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
- /* XXX: Use helper function from AMDGPULowerShaderInstructions here */
case AMDIL::TGID_X:
addLiveIn(MI, MF, MRI, TII, AMDIL::T1_X);
break;
-//===-- R600ISelLowering.h - TODO: Add brief description -------===//
+//===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// R600 DAG Lowering interface definition
//
//===----------------------------------------------------------------------===//
+++ /dev/null
-//===-- R600InstrFormats.td - TODO: Add brief description -------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-
-
-class ALUInst <bits<10> op, dag outs, dag ins, string asm, list<dag> pattern>
- : InstR600 <, outs, ins , asm, pattern>
-//===-- R600InstrInfo.cpp - TODO: Add brief description -------===//
+//===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// R600 Implementation of TargetInstrInfo.
//
//===----------------------------------------------------------------------===//
-//===-- R600InstrInfo.h - TODO: Add brief description -------===//
+//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// Interface definition for R600InstrInfo
//
//===----------------------------------------------------------------------===//
-//===-- R600Instructions.td - TODO: Add brief description -------===//
+//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// R600 Tablegen instruction definitions
//
//===----------------------------------------------------------------------===//
-//===-- R600Intrinsics.td - TODO: Add brief description -------===//
+//===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// R600 Intrinsic Definitions
//
//===----------------------------------------------------------------------===//
-//===-- R600KernelParameters.cpp - TODO: Add brief description -------===//
+//===-- R600KernelParameters.cpp - Lower kernel function arguments --------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// This pass lowers kernel function arguments to loads from the vertex buffer.
+//
+// Kernel arguemnts are stored in the vertex buffer at an offset of 9 dwords,
+// so arg0 needs to be loaded from VTX_BUFFER[9] and arg1 is loaded from
+// VTX_BUFFER[10], etc.
//
//===----------------------------------------------------------------------===//
-#include <llvm-c/Core.h>
-#include "R600KernelParameters.h"
-#include "R600OpenCLUtils.h"
+#include "AMDGPU.h"
+#include "AMDIL.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Constants.h"
+#include "llvm/Function.h"
#include "llvm/Intrinsics.h"
+#include "llvm/Metadata.h"
+#include "llvm/Module.h"
+#include "llvm/Target/TargetData.h"
#include "llvm/Support/IRBuilder.h"
#include "llvm/Support/TypeBuilder.h"
-// #include "llvm/CodeGen/Function.h"
-
-namespace AMDILAS {
-enum AddressSpaces {
- PRIVATE_ADDRESS = 0, // Address space for private memory.
- GLOBAL_ADDRESS = 1, // Address space for global memory (RAT0, VTX0).
- CONSTANT_ADDRESS = 2, // Address space for constant memory.
- LOCAL_ADDRESS = 3, // Address space for local memory.
- REGION_ADDRESS = 4, // Address space for region memory.
- ADDRESS_NONE = 5, // Address space for unknown memory.
- PARAM_D_ADDRESS = 6, // Address space for direct addressible parameter memory (CONST0)
- PARAM_I_ADDRESS = 7, // Address space for indirect addressible parameter memory (VTX1)
- LAST_ADDRESS = 8
-};
-}
-
#include <map>
#include <set>
using namespace llvm;
-using namespace std;
+
+namespace {
#define CONSTANT_CACHE_SIZE_DW 127
-class R600KernelParameters : public llvm::FunctionPass
+class R600KernelParameters : public FunctionPass
{
- const llvm::TargetData * TD;
+ const TargetData * TD;
LLVMContext* Context;
Module *mod;
-
+
struct param
{
- param() : val(NULL), ptr_val(NULL), offset_in_dw(0), size_in_dw(0), indirect(false), specialID(0) {}
-
- llvm::Value* val;
- llvm::Value* ptr_val;
+ param() : val(NULL), ptr_val(NULL), offset_in_dw(0), size_in_dw(0),
+ indirect(false), specialID(0) {}
+
+ Value* val;
+ Value* ptr_val;
int offset_in_dw;
int size_in_dw;
bool indirect;
-
- string specialType;
+
+ std::string specialType;
int specialID;
-
+
int end() { return offset_in_dw + size_in_dw; }
- /* The first 9 dwords are reserved for the grid sizes. */
+ // The first 9 dwords are reserved for the grid sizes.
int get_rat_offset() { return 9 + offset_in_dw; }
};
std::vector<param> params;
- int getLastSpecialID(const string& TypeName);
-
+ bool isOpenCLKernel(const Function* fun);
+ int getLastSpecialID(const std::string& TypeName);
+
int getListSize();
- void AddParam(llvm::Argument* arg);
- int calculateArgumentSize(llvm::Argument* arg);
- void RunAna(llvm::Function* fun);
- void Replace(llvm::Function* fun);
- bool isIndirect(Value* val, set<Value*>& visited);
- void Propagate(llvm::Function* fun);
- void Propagate(llvm::Value* v, const llvm::Twine& name, bool indirect = false);
+ void AddParam(Argument* arg);
+ int calculateArgumentSize(Argument* arg);
+ void RunAna(Function* fun);
+ void Replace(Function* fun);
+ bool isIndirect(Value* val, std::set<Value*>& visited);
+ void Propagate(Function* fun);
+ void Propagate(Value* v, const Twine& name, bool indirect = false);
Value* ConstantRead(Function* fun, param& p);
Value* handleSpecial(Function* fun, param& p);
bool isSpecialType(Type*);
- string getSpecialTypeName(Type*);
+ std::string getSpecialTypeName(Type*);
public:
static char ID;
R600KernelParameters() : FunctionPass(ID) {};
- R600KernelParameters(const llvm::TargetData* TD) : FunctionPass(ID), TD(TD) {}
-// bool runOnFunction (llvm::Function &F);
- bool runOnFunction (llvm::Function &F);
+ R600KernelParameters(const TargetData* TD) : FunctionPass(ID), TD(TD) {}
+ bool runOnFunction (Function &F);
void getAnalysisUsage(AnalysisUsage &AU) const;
const char *getPassName() const;
bool doInitialization(Module &M);
char R600KernelParameters::ID = 0;
-static RegisterPass<R600KernelParameters> X("kerparam", "OpenCL Kernel Parameter conversion", false, false);
+static RegisterPass<R600KernelParameters> X("kerparam",
+ "OpenCL Kernel Parameter conversion", false, false);
-int R600KernelParameters::getLastSpecialID(const string& TypeName)
+bool R600KernelParameters::isOpenCLKernel(const Function* fun)
+{
+ Module *mod = const_cast<Function*>(fun)->getParent();
+ NamedMDNode * md = mod->getOrInsertNamedMetadata("opencl.kernels");
+
+ if (!md or !md->getNumOperands())
+ {
+ return false;
+ }
+
+ for (int i = 0; i < int(md->getNumOperands()); i++)
+ {
+ if (!md->getOperand(i) or !md->getOperand(i)->getOperand(0))
+ {
+ continue;
+ }
+
+ assert(md->getOperand(i)->getNumOperands() == 1);
+
+ if (md->getOperand(i)->getOperand(0)->getName() == fun->getName())
+ {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+int R600KernelParameters::getLastSpecialID(const std::string& TypeName)
{
int lastID = -1;
-
- for (vector<param>::iterator i = params.begin(); i != params.end(); i++)
+
+ for (
std::vector<param>::iterator i = params.begin(); i != params.end(); i++)
{
if (i->specialType == TypeName)
{
return params.back().end();
}
-bool R600KernelParameters::isIndirect(Value* val, set<Value*>& visited)
+bool R600KernelParameters::isIndirect(Value* val, std::set<Value*>& visited)
{
if (isa<LoadInst>(val))
{
}
visited.insert(val);
-
+
if (isa<GetElementPtrInst>(val))
{
GetElementPtrInst* GEP = dyn_cast<GetElementPtrInst>(val);
}
}
}
-
+
for (Value::use_iterator i = val->use_begin(); i != val->use_end(); i++)
{
Value* v2 = dyn_cast<Value>(*i);
return false;
}
-void R600KernelParameters::AddParam(llvm::Argument* arg)
+void R600KernelParameters::AddParam(Argument* arg)
{
param p;
-
+
p.val = dyn_cast<Value>(arg);
p.offset_in_dw = getListSize();
p.size_in_dw = calculateArgumentSize(arg);
if (isa<PointerType>(arg->getType()) and arg->hasByValAttr())
{
- set<Value*> visited;
+ std::set<Value*> visited;
p.indirect = isIndirect(p.val, visited);
}
-
+
params.push_back(p);
}
-int R600KernelParameters::calculateArgumentSize(llvm::Argument* arg)
+int R600KernelParameters::calculateArgumentSize(Argument* arg)
{
Type* t = arg->getType();
{
t = dyn_cast<PointerType>(t)->getElementType();
}
-
+
int store_size_in_dw = (TD->getTypeStoreSize(t) + 3)/4;
assert(store_size_in_dw);
-
+
return store_size_in_dw;
}
-void R600KernelParameters::RunAna(llvm::Function* fun)
+void R600KernelParameters::RunAna(Function* fun)
{
assert(isOpenCLKernel(fun));
}
-void R600KernelParameters::Replace(llvm::Function* fun)
+void R600KernelParameters::Replace(Function* fun)
{
for (std::vector<param>::iterator i = params.begin(); i != params.end(); i++)
{
if (new_val)
{
i->val->replaceAllUsesWith(new_val);
- }
+ }
}
}
-void R600KernelParameters::Propagate(llvm::Function* fun)
+void R600KernelParameters::Propagate(Function* fun)
{
for (std::vector<param>::iterator i = params.begin(); i != params.end(); i++)
{
{
LoadInst* load = dyn_cast<LoadInst>(v);
GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(v);
-
- unsigned addrspace;
+
+ unsigned addrspace;
if (indirect)
{
if (dyn_cast<PointerType>(op->getType())->getAddressSpace() != addrspace)
{
- op = new BitCastInst(op, PointerType::get(dyn_cast<PointerType>(op->getType())->getElementType(), addrspace), name, dyn_cast<Instruction>(v));
+ op = new BitCastInst(op, PointerType::get(dyn_cast<PointerType>(
+ op->getType())->getElementType(), addrspace),
+ name, dyn_cast<Instruction>(v));
}
- vector<Value*> params(GEP->idx_begin(), GEP->idx_end());
-
- GetElementPtrInst* GEP2 = GetElementPtrInst::Create(op, params, name, dyn_cast<Instruction>(v));
+ std::vector<Value*> params(GEP->idx_begin(), GEP->idx_end());
+
+ GetElementPtrInst* GEP2 = GetElementPtrInst::Create(op, params, name,
+ dyn_cast<Instruction>(v));
GEP2->setIsInBounds(GEP->isInBounds());
v = dyn_cast<Value>(GEP2);
GEP->replaceAllUsesWith(GEP2);
GEP->eraseFromParent();
load = NULL;
}
-
+
if (load)
{
- if (load->getPointerAddressSpace() != addrspace) ///normally at this point we have the right address space
+ ///normally at this point we have the right address space
+ if (load->getPointerAddressSpace() != addrspace)
{
Value *orig_ptr = load->getPointerOperand();
PointerType *orig_ptr_type = dyn_cast<PointerType>(orig_ptr->getType());
-
- Type* new_ptr_type = PointerType::get(orig_ptr_type->getElementType(), addrspace);
+
+ Type* new_ptr_type = PointerType::get(orig_ptr_type->getElementType(),
+ addrspace);
Value* new_ptr = orig_ptr;
-
+
if (orig_ptr->getType() != new_ptr_type)
{
new_ptr = new BitCastInst(orig_ptr, new_ptr_type, "prop_cast", load);
}
-
+
Value* new_load = new LoadInst(new_ptr, name, load);
load->replaceAllUsesWith(new_load);
load->eraseFromParent();
}
-
+
return;
}
- vector<User*> users(v->use_begin(), v->use_end());
-
+ std::vector<User*> users(v->use_begin(), v->use_end());
+
for (int i = 0; i < int(users.size()); i++)
{
Value* v2 = dyn_cast<Value>(users[i]);
-
+
if (v2)
{
Propagate(v2, name, indirect);
Value* R600KernelParameters::ConstantRead(Function* fun, param& p)
{
assert(fun->front().begin() != fun->front().end());
-
+
Instruction *first_inst = fun->front().begin();
IRBuilder <> builder (first_inst);
/* First 3 dwords are reserved for the dimmension info */
{
addrspace = AMDILAS::PARAM_D_ADDRESS;
}
-
+
Argument *arg = dyn_cast<Argument>(p.val);
Type * argType = p.val->getType();
PointerType * argPtrType = dyn_cast<PointerType>(p.val->getType());
-
+
if (argPtrType and arg->hasByValAttr())
{
- Value* param_addr_space_ptr = ConstantPointerNull::get(PointerType::get(Type::getInt32Ty(*Context), addrspace));
- Value* param_ptr = GetElementPtrInst::Create(param_addr_space_ptr, ConstantInt::get(Type::getInt32Ty(*Context), p.get_rat_offset()), arg->getName(), first_inst);
- param_ptr = new BitCastInst(param_ptr, PointerType::get(argPtrType->getElementType(), addrspace), arg->getName(), first_inst);
+ Value* param_addr_space_ptr = ConstantPointerNull::get(
+ PointerType::get(Type::getInt32Ty(*Context),
+ addrspace));
+ Value* param_ptr = GetElementPtrInst::Create(param_addr_space_ptr,
+ ConstantInt::get(Type::getInt32Ty(*Context),
+ p.get_rat_offset()), arg->getName(),
+ first_inst);
+ param_ptr = new BitCastInst(param_ptr,
+ PointerType::get(argPtrType->getElementType(),
+ addrspace),
+ arg->getName(), first_inst);
p.ptr_val = param_ptr;
return param_ptr;
}
else
{
- Value* param_addr_space_ptr = ConstantPointerNull::get(PointerType::get(argType, addrspace));
-
+ Value* param_addr_space_ptr = ConstantPointerNull::get(PointerType::get(
+ argType, addrspace));
+
Value* param_ptr = builder.CreateGEP(param_addr_space_ptr,
- ConstantInt::get(Type::getInt32Ty(*Context), p.get_rat_offset()), arg->getName());
-
+ ConstantInt::get(Type::getInt32Ty(*Context), p.get_rat_offset()),
+ arg->getName());
+
Value* param_value = builder.CreateLoad(param_ptr, arg->getName());
-
+
return param_value;
}
}
Value* R600KernelParameters::handleSpecial(Function* fun, param& p)
{
- string name = getSpecialTypeName(p.val->getType());
+ std::string name = getSpecialTypeName(p.val->getType());
int ID;
assert(!name.empty());
-
+
if (name == "image2d_t" or name == "image3d_t")
{
- int lastID = max(getLastSpecialID("image2d_t"), getLastSpecialID("image3d_t"));
-
+ int lastID = std::max(getLastSpecialID("image2d_t"),
+ getLastSpecialID("image3d_t"));
+
if (lastID == -1)
{
ID = 2; ///ID0 and ID1 are used internally by the driver
else
{
ID = lastID + 1;
- }
+ }
}
else
{
///TODO: give some error message
return NULL;
}
-
+
p.specialType = name;
p.specialID = ID;
Instruction *first_inst = fun->front().begin();
- return new IntToPtrInst(ConstantInt::get(Type::getInt32Ty(*Context), p.specialID), p.val->getType(), "resourceID", first_inst);
+ return new IntToPtrInst(ConstantInt::get(Type::getInt32Ty(*Context),
+ p.specialID), p.val->getType(),
+ "resourceID", first_inst);
}
return !getSpecialTypeName(t).empty();
}
-string R600KernelParameters::getSpecialTypeName(Type* t)
+std::string R600KernelParameters::getSpecialTypeName(Type* t)
{
PointerType *pt = dyn_cast<PointerType>(t);
StructType *st = NULL;
if (st)
{
- string prefix = "struct.opencl_builtin_type_";
-
- string name = st->getName().str();
+ std::string prefix = "struct.opencl_builtin_type_";
+
+ std::string name = st->getName().str();
if (name.substr(0, prefix.length()) == prefix)
{
return false;
}
-// F.dump();
-
RunAna(&F);
Replace(&F);
Propagate(&F);
-
- mod->dump();
+
return false;
}
void R600KernelParameters::getAnalysisUsage(AnalysisUsage &AU) const
{
-// AU.addRequired<FunctionAnalysis>();
FunctionPass::getAnalysisUsage(AU);
AU.setPreservesAll();
}
{
Context = &M.getContext();
mod = &M;
-
+
return false;
}
return false;
}
-llvm::FunctionPass* createR600KernelParametersPass(const llvm::TargetData* TD)
+} // End anonymous namespace
+
+FunctionPass* llvm::createR600KernelParametersPass(const TargetData* TD)
{
FunctionPass *p = new R600KernelParameters(TD);
-
+
return p;
}
+++ /dev/null
-//===-- R600KernelParameters.h - TODO: Add brief description -------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef KERNELPARAMETERS_H
-#define KERNELPARAMETERS_H
-
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/Function.h"
-#include "llvm/Pass.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Value.h"
-
-#include <vector>
-
-llvm::FunctionPass* createR600KernelParametersPass(const llvm::TargetData* TD);
-
-
-#endif
-//===-- R600LowerInstructions.cpp - TODO: Add brief description -------===//
+//===-- R600LowerInstructions.cpp - Lower unsupported AMDIL instructions --===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// This pass lowers AMDIL MachineInstrs that aren't supported by the R600
+// target to either supported AMDIL MachineInstrs or R600 MachineInstrs.
//
//===----------------------------------------------------------------------===//
-//===-- R600MachineFunctionInfo.cpp - TODO: Add brief description -------===//
+//===-- R600MachineFunctionInfo.cpp - R600 Machine Function Info-*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
#include "R600MachineFunctionInfo.h"
-//===-- R600MachineFunctionInfo.h - TODO: Add brief description ---*- C++ -*-=//
+//===-- R600MachineFunctionInfo.h - R600 Machine Function Info ----*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// R600MachineFunctionInfo is used for keeping track of which registers have
+// been reserved by the llvm.AMDGPU.reserve.reg intrinsic.
//
//===----------------------------------------------------------------------===//
+++ /dev/null
-//===-- OpenCLUtils.h - TODO: Add brief description -------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-#ifndef OPENCLUTILS_H
-#define OPENCLUTILS_H
-
-#include "llvm/Function.h"
-
-#include <llvm/Module.h>
-
-static bool isOpenCLKernel(const llvm::Function* fun)
-{
- llvm::Module *mod = const_cast<llvm::Function*>(fun)->getParent();
- llvm::NamedMDNode * md = mod->getOrInsertNamedMetadata("opencl.kernels");
-
- if (!md or !md->getNumOperands())
- {
- return false;
- }
-
- for (int i = 0; i < int(md->getNumOperands()); i++)
- {
- if (!md->getOperand(i) or !md->getOperand(i)->getOperand(0))
- {
- continue;
- }
-
- assert(md->getOperand(i)->getNumOperands() == 1);
-
- if (md->getOperand(i)->getOperand(0)->getName() == fun->getName())
- {
- return true;
- }
- }
-
- return false;
-}
-
-
-#endif
-//===-- R600RegisterInfo.cpp - TODO: Add brief description -------===//
+//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// The file contains the R600 implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
-//===-- R600RegisterInfo.h - TODO: Add brief description -------===//
+//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// Interface definition for R600RegisterInfo
//
//===----------------------------------------------------------------------===//
-//===-- R600Schedule.td - TODO: Add brief description -------===//
+//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
+// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
+// slot has been removed.
//
//===----------------------------------------------------------------------===//
-//===-- SIAssignInterpRegs.cpp - TODO: Add brief description -------===//
+//===-- SIAssignInterpRegs.cpp - Assign interpolation registers -----------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// This pass maps the pseudo interpolation registers to the correct physical
+// registers. Prior to executing a fragment shader, the GPU loads interpolation
+// parameters into physical registers. The specific physical register that each
+// interpolation parameter ends up in depends on the type of the interpolation
+// parameter as well as how many interpolation parameters are used by the
+// shader.
//
//===----------------------------------------------------------------------===//
-//===-- SICodeEmitter.cpp - TODO: Add brief description -------===//
+//===-- SICodeEmitter.cpp - SI Code Emitter -------------------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// The SI code emitter produces machine code that can be executed directly on
+// the GPU device.
//
//===----------------------------------------------------------------------===//
-#===-- SIGenRegisterInfo.pl - TODO: Add brief description -------===#
+#===-- SIGenRegisterInfo.pl - Script for generating register info files ----===#
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
-#===----------------------------------------------------------------------===#
+#===------------------------------------------------------------------------===#
#
-# TODO: Add full description
+# This perl script prints to stdout .td code to be used as SIRegisterInfo.td
+# it also generates a file called SIHwRegInfo.include, which contains helper
+# functions for determining the hw encoding of registers.
#
-#===----------------------------------------------------------------------===#
-
+#===------------------------------------------------------------------------===#
use strict;
use warnings;
-//===-- SIISelLowering.cpp - TODO: Add brief description -------===//
+//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// Most of the DAG lowering is handled in AMDILISelLowering.cpp. This file is
+// mostly EmitInstrWithCustomInserter().
//
//===----------------------------------------------------------------------===//
-//===-- SIISelLowering.h - TODO: Add brief description -------===//
+//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// SI DAG Lowering interface definition
//
//===----------------------------------------------------------------------===//
-//===-- SIInstrFormats.td - TODO: Add brief description -------===//
+//===-- SIInstrFormats.td - SI Instruction Formats ------------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// SI Instruction format definitions.
+//
+// Instructions with _32 take 32-bit operands.
+// Instructions with _64 take 64-bit operands.
+//
+// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
+// encoding is the standard encoding, but instruction that make use of
+// any of the instruction modifiers must use the 64-bit encoding.
+//
+// Instructions with _e32 use the 32-bit encoding.
+// Instructions with _e64 use the 64-bit encoding.
//
//===----------------------------------------------------------------------===//
-//===-- SIInstrInfo.cpp - TODO: Add brief description -------===//
+//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// SI Implementation of TargetInstrInfo.
//
//===----------------------------------------------------------------------===//
-//===-- SIInstrInfo.h - TODO: Add brief description -------===//
+//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// Interface definition for SIInstrInfo.
//
//===----------------------------------------------------------------------===//
-//===-- SIInstrInfo.td - TODO: Add brief description -------===//
+//===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-//===-- SIInstructions.td - TODO: Add brief description -------===//
+//===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
def isSI : Predicate<"Subtarget.device()"
-//===-- SIIntrinsics.td - TODO: Add brief description -------===//
+//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// SI Intrinsic Definitions
//
//===----------------------------------------------------------------------===//
-//===-- SILowerShaderInstructions.cpp - TODO: Add brief description -------===//
+//===-- SILowerShaderInstructions.cpp - Pass for lowering shader instructions -------===//
//
// The LLVM Compiler Infrastructure
//
-//===-- SIMachineFunctionInfo.cpp - TODO: Add brief description -------===//
+//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
#include "SIMachineFunctionInfo.h"
-//===-- SIMachineFunctionInfo.h - TODO: Add brief description -------===//
+//===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// SIMachineFunctionInfo is used to keep track of the spi_sp_input_addr config
+// register, which is to tell the hardware which interpolation parameters to
+// load.
//
//===----------------------------------------------------------------------===//
-//===-- SIPropagateImmReads.cpp - TODO: Add brief description -------===//
+//===-- SIPropagateImmReads.cpp - Lower Immediate Reads Pass --------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// We can't do this in the ConvertToISA pass, because later passes might
+// create LOADCONST_* instructions that we would miss. This is why we need
+// a separate pass for this.
//
//===----------------------------------------------------------------------===//
-//===-- SIRegisterInfo.cpp - TODO: Add brief description -------===//
+//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// This file contains the SI implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
-//===-- SIRegisterInfo.h - TODO: Add brief description -------===//
+//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// Interface definition for SIRegisterInfo
//
//===----------------------------------------------------------------------===//
-//===-- SISchedule.td - TODO: Add brief description -------===//
+//===-- SISchedule.td - SI Scheduling definitons -------------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// TODO: This is just a place holder for now.
//
//===----------------------------------------------------------------------===//
projects / mesa.git / commitdiff