Add test for abc9+mince issue

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys
new file mode 100644 (file)
index 0000000..408e16f
--- /dev/null
+++ b/tests/various/ice40_mince_abc9.ys
@@ -0,0 +1,17 @@
+read_verilog <<EOT
+
+module top(input clk, ce, input [2:0] a, b, output reg [2:0] q);
+
+       reg [2:0] aa, bb;
+
+       always @(posedge clk) begin
+               if (ce) begin
+                       aa <= a;
+               end
+               bb <= b;
+               q <= aa + bb;
+       end
+endmodule
+EOT
+
+synth_ice40 -abc9 -dffe_min_ce_use 4