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radeonsi: set PA_SU_HARDWARE_SCREEN_OFFSET to 0
authorMarek Olšák <marek.olsak@amd.com>
Fri, 20 Feb 2015 11:14:37 +0000 (12:14 +0100)
committerMarek Olšák <marek.olsak@amd.com>
Tue, 24 Feb 2015 20:21:04 +0000 (21:21 +0100)
It was probably 0 already, but it doesn't hurt to set it.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
src/gallium/drivers/radeonsi/si_state.c patch | blob | history

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 3eea0b6c18a4c39b7ef49770826229376a92961d..db8af210c6aa986d73f73ed62f42f8defc9a5ebc 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3122,6 +3122,8 @@ void si_init_config(struct si_context *sctx)
 
        si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
        si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
+       /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
+       si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
        si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
        si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
        si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);