soc/integration/soc_zynq: fix HP0 connections

diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py
index c6b0a56610370c4acd659f5a14e67884cfcc7372..86d2d7b1a6aaeccf8ff4ea67ecfac176892d0818 100644 (file)
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@@ -136,60 +136,60 @@ class SoCZynq(SoCCore):
         self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
         self.ps7_params.update(
             # axi hp0 aw
-            i_M_AXI_HP0_AWVALID=axi_hp0.aw.valid,
-            o_M_AXI_HP0_AWREADY=axi_hp0.aw.ready,
-            i_M_AXI_HP0_AWADDR=axi_hp0.aw.addr,
-            i_M_AXI_HP0_AWBURST=axi_hp0.aw.burst,
-            i_M_AXI_HP0_AWLEN=axi_hp0.aw.len,
-            i_M_AXI_HP0_AWSIZE=axi_hp0.aw.size,
-            i_M_AXI_HP0_AWID=axi_hp0.aw.id,
-            i_M_AXI_HP0_AWLOCK=axi_hp0.aw.lock,
-            i_M_AXI_HP0_AWPROT=axi_hp0.aw.prot,
-            i_M_AXI_HP0_AWCACHE=axi_hp0.aw.cache,
-            i_M_AXI_HP0_AWQOS=axi_hp0.aw.qos,
+            i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,
+            o_S_AXI_HP0_AWREADY=axi_hp0.aw.ready,
+            i_S_AXI_HP0_AWADDR=axi_hp0.aw.addr,
+            i_S_AXI_HP0_AWBURST=axi_hp0.aw.burst,
+            i_S_AXI_HP0_AWLEN=axi_hp0.aw.len,
+            i_S_AXI_HP0_AWSIZE=axi_hp0.aw.size,
+            i_S_AXI_HP0_AWID=axi_hp0.aw.id,
+            i_S_AXI_HP0_AWLOCK=axi_hp0.aw.lock,
+            i_S_AXI_HP0_AWPROT=axi_hp0.aw.prot,
+            i_S_AXI_HP0_AWCACHE=axi_hp0.aw.cache,
+            i_S_AXI_HP0_AWQOS=axi_hp0.aw.qos,
 
             # axi hp0 w
-            i_M_AXI_HP0_WVALID=axi_hp0.w.valid,
-            i_M_AXI_HP0_WLAST=axi_hp0.w.last,
-            o_M_AXI_HP0_WREADY=axi_hp0.w.ready,
-            i_M_AXI_HP0_WID=axi_hp0.w.id,
-            i_M_AXI_HP0_WDATA=axi_hp0.w.data,
-            i_M_AXI_HP0_WSTRB=axi_hp0.w.strb,
+            i_S_AXI_HP0_WVALID=axi_hp0.w.valid,
+            i_S_AXI_HP0_WLAST=axi_hp0.w.last,
+            o_S_AXI_HP0_WREADY=axi_hp0.w.ready,
+            i_S_AXI_HP0_WID=axi_hp0.w.id,
+            i_S_AXI_HP0_WDATA=axi_hp0.w.data,
+            i_S_AXI_HP0_WSTRB=axi_hp0.w.strb,
 
             # axi hp0 b
-            o_M_AXI_HP0_BVALID=axi_hp0.b.valid,
-            i_M_AXI_HP0_BREADY=axi_hp0.b.ready,
-            o_M_AXI_HP0_BID=axi_hp0.b.id,
-            o_M_AXI_HP0_BRESP=axi_hp0.b.resp,
+            o_S_AXI_HP0_BVALID=axi_hp0.b.valid,
+            i_S_AXI_HP0_BREADY=axi_hp0.b.ready,
+            o_S_AXI_HP0_BID=axi_hp0.b.id,
+            o_S_AXI_HP0_BRESP=axi_hp0.b.resp,
 
             # axi hp0 ar
-            i_M_AXI_HP0_ARVALID=axi_hp0.ar.valid,
-            o_M_AXI_HP0_ARREADY=axi_hp0.ar.ready,
-            i_M_AXI_HP0_ARADDR=axi_hp0.ar.addr,
-            i_M_AXI_HP0_ARBURST=axi_hp0.ar.burst,
-            i_M_AXI_HP0_ARLEN=axi_hp0.ar.len,
-            i_M_AXI_HP0_ARID=axi_hp0.ar.id,
-            i_M_AXI_HP0_ARLOCK=axi_hp0.ar.lock,
-            i_M_AXI_HP0_ARSIZE=axi_hp0.ar.size,
-            i_M_AXI_HP0_ARPROT=axi_hp0.ar.prot,
-            i_M_AXI_HP0_ARCACHE=axi_hp0.ar.cache,
-            i_M_AXI_HP0_ARQOS=axi_hp0.ar.qos,
+            i_S_AXI_HP0_ARVALID=axi_hp0.ar.valid,
+            o_S_AXI_HP0_ARREADY=axi_hp0.ar.ready,
+            i_S_AXI_HP0_ARADDR=axi_hp0.ar.addr,
+            i_S_AXI_HP0_ARBURST=axi_hp0.ar.burst,
+            i_S_AXI_HP0_ARLEN=axi_hp0.ar.len,
+            i_S_AXI_HP0_ARID=axi_hp0.ar.id,
+            i_S_AXI_HP0_ARLOCK=axi_hp0.ar.lock,
+            i_S_AXI_HP0_ARSIZE=axi_hp0.ar.size,
+            i_S_AXI_HP0_ARPROT=axi_hp0.ar.prot,
+            i_S_AXI_HP0_ARCACHE=axi_hp0.ar.cache,
+            i_S_AXI_HP0_ARQOS=axi_hp0.ar.qos,
 
             # axi hp0 r
-            o_M_AXI_HP0_RVALID=axi_hp0.r.valid,
-            i_M_AXI_HP0_RREADY=axi_hp0.r.ready,
-            o_M_AXI_HP0_RLAST=axi_hp0.r.last,
-            o_M_AXI_HP0_RID=axi_hp0.r.id,
-            o_M_AXI_HP0_RRESP=axi_hp0.r.resp,
-            o_M_AXI_HP0_RDATA=axi_hp0.r.data,
+            o_S_AXI_HP0_RVALID=axi_hp0.r.valid,
+            i_S_AXI_HP0_RREADY=axi_hp0.r.ready,
+            o_S_AXI_HP0_RLAST=axi_hp0.r.last,
+            o_S_AXI_HP0_RID=axi_hp0.r.id,
+            o_S_AXI_HP0_RRESP=axi_hp0.r.resp,
+            o_S_AXI_HP0_RDATA=axi_hp0.r.data,
 
             # axi hp0 fifo ctrl
-            i_S_AXI_HP0_FIFO_CTRL_0_RACOUNT=axi_hp0_fifo_ctrl.racount,
-            i_S_AXI_HP0_FIFO_CTRL_0_RCOUNT=axi_hp0_fifo_ctrl.rcount,
-            o_S_AXI_HP0_FIFO_CTRL_0_RDISSUECAPEN=axi_hp0_fifo_ctrl.rdissuecapen,
-            i_S_AXI_HP0_FIFO_CTRL_0_WACOUNT=axi_hp0_fifo_ctrl.wacount,
-            i_S_AXI_HP0_FIFO_CTRL_0_WCOUNT=axi_hp0_fifo_ctrl.wcount,
-            o_S_AXI_HP0_FIFO_CTRL_0_WRISSUECAPEN=axi_hp0_fifo_ctrl.wrissuecapen
+            o_S_AXI_HP0_RACOUNT=axi_hp0_fifo_ctrl.racount,
+            o_S_AXI_HP0_RCOUNT=axi_hp0_fifo_ctrl.rcount,
+            i_S_AXI_HP0_RDISSUECAP1_EN=axi_hp0_fifo_ctrl.rdissuecapen,
+            o_S_AXI_HP0_WACOUNT=axi_hp0_fifo_ctrl.wacount,
+            o_S_AXI_HP0_WCOUNT=axi_hp0_fifo_ctrl.wcount,
+            i_S_AXI_HP0_WRISSUECAP1_EN=axi_hp0_fifo_ctrl.wrissuecapen
         )
 
     def add_axi_to_wishbone(self, axi_port, base_address=0x43c00000):