bus: add DFI

diff --git a/doc/migen.txt b/doc/migen.txt
index f8f97180c08de9c0074af32659996b06a792209a..b50bf9e6fee6605ed6f111c00b0346ea5fdba642 100644 (file)
--- a/doc/migen.txt
+++ b/doc/migen.txt
@@ -367,6 +367,8 @@ slave interfaces of the following buses:
     software.
   - ASMIbus, a split-transaction bus optimized for use with a
     high-performance, out-of-order SDRAM controller.
+  - DFI [12] (partial), a standard interface protocol between memory
+    controller logic and PHY interfaces.
 
 It also provides interconnect components for these buses, such as
 arbiters and address decoders. The strength of the Migen procedurally
@@ -476,3 +478,4 @@ References:
 [ 9] http://orc-apps.sourceforge.net/
 [10] http://opendf.sourceforge.net/
 [11] http://networkx.lanl.gov/
+[12] http://www.ddr-phy.org/

diff --git a/migen/bus/dfi.py b/migen/bus/dfi.py
new file mode 100644 (file)
index 0000000..3364f12
--- /dev/null
+++ b/migen/bus/dfi.py
@@ -0,0 +1,54 @@
+from migen.fhdl.structure import *
+from migen.bus.simple import *
+
+def phase_description(a, ba, d):
+       return Description(
+               (M_TO_S,        "address",      a),
+               (M_TO_S,        "bank",         ba),
+               (M_TO_S,        "cas_n",        1),
+               (M_TO_S,        "cke",          1),
+               (M_TO_S,        "cs_n",         1),
+               (M_TO_S,        "ras_n",        1),
+               (M_TO_S,        "we_n",         1),
+               
+               (M_TO_S,        "wrdata",       d),
+               (M_TO_S,        "wrdata_en",    1),
+               (M_TO_S,        "wrdata_mask",  d//8),
+               
+               (M_TO_S,        "rddata_en",    1),
+               (S_TO_M,        "rddata",       d),
+               (S_TO_M,        "rddata_valid", 1)
+       )
+
+class Interface:
+       def __init__(self, a, ba, d, nphases=1):
+               self.pdesc = phase_description(a, ba, d)
+               self.phases = [SimpleInterface(self.pdesc) for i in range(nphases)]
+       
+       # Returns pairs (DFI-mandated signal name, Migen signal object)
+       def get_standard_names(self):
+               r = []
+               add_suffix = len(self.phases) > 1
+               for n, phase in enumerate(self.phases):
+                       for signal in self.pdesc.desc:
+                               if add_suffix:
+                                       if signal[0] == M_TO_S:
+                                               suffix = "_p" + int(n)
+                                       else:
+                                               suffix = "_w" + int(n)
+                               else:
+                                       suffix = ""
+                       r.append(("dfi_" + signal[1] + suffix, getattr(self, signal[1])))
+               return r
+
+class Interconnect:
+       def __init__(self, master, slave):
+               self.master = master
+               self.slave = slave
+       
+       def get_fragment(self):
+               f = Fragment()
+               for pm, ps in zip(self.master.phases, self.slave.phases):
+                       ic = SimpleInterconnect(pm, [ps])
+                       f += ic.get_fragment()
+               return f