Added $_DFFE_??_ cell types

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 3d9e4cf93ce0e89039741363f38f7b4e7cd983b0..f58ae14c400cb165389fe269ce46dc0d6e05355c 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -156,6 +156,10 @@ struct CellTypes
                for (auto c1 : list_np)
                        setup_type(stringf("$_DFF_%c_", c1), {"\\C", "\\D"}, {"\\Q"});
 
+               for (auto c1 : list_np)
+               for (auto c2 : list_np)
+                       setup_type(stringf("$_DFFE_%c%c_", c1, c2), {"\\C", "\\D", "\\E"}, {"\\Q"});
+
                for (auto c1 : list_np)
                for (auto c2 : list_np)
                for (auto c3 : list_01)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 803d783af919d009eaa408d6a3c4bfcaa5ab968f..321c39e10215f3a34b4173cd973e79784c472135 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -892,6 +892,11 @@ namespace {
                        if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
                        if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
 
+                       if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
+                       if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
+                       if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
+                       if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
+
                        if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
                        if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
                        if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 88566411ada3f0a039f953b6d92104cd1965140f..eb62d7830786bc441bab4d5d75945c88b8778cb1 100644 (file)
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -163,6 +163,38 @@ always @(posedge C) begin
 end
 endmodule
 
+module  \$_DFFE_NN_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(negedge C) begin
+       if (!E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_NP_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(negedge C) begin
+       if (E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_PN_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(posedge C) begin
+       if (!E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_PP_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(posedge C) begin
+       if (E) Q <= D;
+end
+endmodule
+
 module  \$_DFF_NN0_ (D, Q, C, R);
 input D, C, R;
 output reg Q;