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Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 24 Apr 2018 08:00:45 +0000
(09:00 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 24 Apr 2018 08:00:45 +0000
(09:00 +0100)
simple_v_extension.mdwn
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diff --git
a/simple_v_extension.mdwn
b/simple_v_extension.mdwn
index 92ac117ede55c558cfffcc11fa68ca21dc6be069..d70038747ccb382fd3f4351a84a9c96b8ef0eb04 100644
(file)
--- a/
simple_v_extension.mdwn
+++ b/
simple_v_extension.mdwn
@@
-138,7
+138,7
@@
burdensome to implementations, given that instruction decode already has
to direct the operation to a correctly-sized width ALU engine, anyway.
Not least: in places where an ISA was previously constrained (due for
-whatever reason, including limitations of the available operand sp
c
ace),
+whatever reason, including limitations of the available operand space),
implicit bit-width allows the meaning of certain operations to be
type-overloaded *without* pollution or alteration of frozen and immutable
instructions, in a fully backwards-compatible fashion.