Update testcase comment.

   addb.cgs addd.cgs addi.cgs andb.cgs andd.cgs andw.cgs
   ashub.cgs ashub_i.cgs ashud.cgs ashud_i.cgs ashuw.cgs
   ashuw_i.cgs cmpi.cgs cmpw.cgs jlt.cgs jump.cgs loadd.cgs
   loadw.cgs lshb.cgs lshb_i.cgs lshd.cgs lshd_i.cgs lshw.cgs
   lshw_i.cgs movb.cgs movd.cgs movw.cgs movxb.cgs movxw.cgs
   movzb.cgs movzw.cgs mulb.cgs muluw.cgs mulw.cgs orb.cgs
   ord.cgs orw.cgs pop1.cgs pop2.cgs pop3.cgs popret1.cgs
   popret2.cgs popret3.cgs push1.cgs push2.cgs push3.cgs

Added BIT operation testcases:
  cbitb.cgs cbitw.cgs sbitb.cgs sbitw.cgs tbitb.cgs tbit.cgs and tbitw.cgs

diff --git a/sim/testsuite/sim/cr16/addb.cgs b/sim/testsuite/sim/cr16/addb.cgs
index 020f0fc52fbcb150bcc364004251888ad5732204..272804ae407382ac342fdc7c8209617b817fc758 100644 (file)
--- a/sim/testsuite/sim/cr16/addb.cgs
+++ b/sim/testsuite/sim/cr16/addb.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for addb $dr,$sr
+# cr16 testcase for addb $sr, reg
 # mach(): cr16 
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/addd.cgs b/sim/testsuite/sim/cr16/addd.cgs
index cf9a9755fe24315f306688f3697c61958a9826cb..c13164d14371c2c664b1d1cc24d9d039319abcc8 100644 (file)
--- a/sim/testsuite/sim/cr16/addd.cgs
+++ b/sim/testsuite/sim/cr16/addd.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for addd $sr,$dr
+# cr16 testcase for addd $sr, regp
 # mach(): cr16 
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/addi.cgs b/sim/testsuite/sim/cr16/addi.cgs
index 5d0fa1a14e8bbeb86c31701b4521f0f0eab6ec10..dae8941008fbfd5f27a3afd17f68f904879a2ea0 100644 (file)
--- a/sim/testsuite/sim/cr16/addi.cgs
+++ b/sim/testsuite/sim/cr16/addi.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for addi #$simm8, $dr
+# cr16 testcase for addi $imm8, $dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/andb.cgs b/sim/testsuite/sim/cr16/andb.cgs
index 56d10839ef2293e41705e6b8a2d0769799e4d497..bc201adef6093adc25db472a47499eba291a2fbe 100644 (file)
--- a/sim/testsuite/sim/cr16/andb.cgs
+++ b/sim/testsuite/sim/cr16/andb.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for and $dr,$sr
+# cr16 testcase for and $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/andd.cgs b/sim/testsuite/sim/cr16/andd.cgs
index 3951bf736fdd8f2ae20b584999ab19349370eb82..8e72baeb03917211d932a1b7bd04b83b80611110 100644 (file)
--- a/sim/testsuite/sim/cr16/andd.cgs
+++ b/sim/testsuite/sim/cr16/andd.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for and $dr,$sr
+# cr16 testcase for and $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/andw.cgs b/sim/testsuite/sim/cr16/andw.cgs
index 20bb37005762011d4d249500c52c864e93045f38..d2d634a7b548a569347060c01f429c12ffb6f88e 100644 (file)
--- a/sim/testsuite/sim/cr16/andw.cgs
+++ b/sim/testsuite/sim/cr16/andw.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for and $dr,$sr
+# cr16 testcase for and $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/ashub.cgs b/sim/testsuite/sim/cr16/ashub.cgs
index b3113e1535ba395d9c97ad4149e69645ad7182c1..ef3e94eff9a617a207648f14dc98344859458554 100644 (file)
--- a/sim/testsuite/sim/cr16/ashub.cgs
+++ b/sim/testsuite/sim/cr16/ashub.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for ashub $dr,$sr
+# cr16 testcase for ashub $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/ashub_i.cgs b/sim/testsuite/sim/cr16/ashub_i.cgs
index ce0af1d6f59390f1df6d0baf0755b0ec3b9a2739..b4765a4a53d88be372882b72a43500c9f1961de7 100644 (file)
--- a/sim/testsuite/sim/cr16/ashub_i.cgs
+++ b/sim/testsuite/sim/cr16/ashub_i.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for ashub $dr,$sr
+# cr16 testcase for ashub $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/ashud.cgs b/sim/testsuite/sim/cr16/ashud.cgs
index 91b6e754bb4be18d7533c0be84cd6683ef82b75f..c9511da49076da7abee95e52227d20b1ed3fc4ac 100644 (file)
--- a/sim/testsuite/sim/cr16/ashud.cgs
+++ b/sim/testsuite/sim/cr16/ashud.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for ashud $dr,$sr
+# cr16 testcase for ashud $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/ashud_i.cgs b/sim/testsuite/sim/cr16/ashud_i.cgs
index 3b457972d8bf0953cbab7795c1b321d1062d913d..3beb4e357203a07355e0ecfe2f7d430bf5245a96 100644 (file)
--- a/sim/testsuite/sim/cr16/ashud_i.cgs
+++ b/sim/testsuite/sim/cr16/ashud_i.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for ashud $dr,$sr
+# cr16 testcase for ashud $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/ashuw.cgs b/sim/testsuite/sim/cr16/ashuw.cgs
index 8ef3cf721fc88edd42557af07a736999babc27ed..8f52e35c08c79396c6e42d9a381e59a42ff0664a 100644 (file)
--- a/sim/testsuite/sim/cr16/ashuw.cgs
+++ b/sim/testsuite/sim/cr16/ashuw.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for ashuw $dr,$sr
+# cr16 testcase for ashuw $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/ashuw_i.cgs b/sim/testsuite/sim/cr16/ashuw_i.cgs
index 0a8322a23043804db00184ff423bad4a126563e8..99259143d08b090d11435a8ad0555a7b059f67a3 100644 (file)
--- a/sim/testsuite/sim/cr16/ashuw_i.cgs
+++ b/sim/testsuite/sim/cr16/ashuw_i.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for ashuw $dr,$sr
+# cr16 testcase for ashuw $sr,$dr
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/cbitb.cgs b/sim/testsuite/sim/cr16/cbitb.cgs
new file mode 100644 (file)
index 0000000..473fd71
--- /dev/null
+++ b/sim/testsuite/sim/cr16/cbitb.cgs
@@ -0,0 +1,35 @@
+# cr16 testcase for cbitb $bit_pos, ABS/REGP/REG
+# mach:         cr16
+
+       .include "testutils.inc"
+
+       start
+
+       .global cbitb
+cbitb:
+       cbitb   $0,_y
+       loadw   _y, r1
+       cmpb    $0xfe, r1
+       beq ok1
+not_ok:
+       fail
+
+ok1:
+       movd   $_y, (r1,r0)
+       cbitb   $1,0(r1,r0)
+       loadw   _y, r1
+       cmpb    $0xfc, r1
+       beq ok2
+       br not_ok
+ok2:
+
+       movw   $_y, r1
+       cbitb   $2,0(r1)
+       loadw   _y, r1
+       cmpb    $0xf8, r1
+       beq ok3
+       br not_ok
+ok3:
+       pass
+
+_y:    .word   0xff

diff --git a/sim/testsuite/sim/cr16/cbitw.cgs b/sim/testsuite/sim/cr16/cbitw.cgs
new file mode 100644 (file)
index 0000000..a97698c
--- /dev/null
+++ b/sim/testsuite/sim/cr16/cbitw.cgs
@@ -0,0 +1,35 @@
+# cr16 testcase for cbitw
+# mach:         cr16
+
+       .include "testutils.inc"
+
+       start
+
+       .global cbitw
+cbitw:
+       cbitw   $4,_y
+       loadw   _y, r1
+       cmpb    $0xef, r1
+       beq ok1
+not_ok:
+       fail
+
+ok1:
+       movd   $_y, (r1,r0)
+       cbitw   $5,0(r1,r0)
+       loadw   _y, r1
+       cmpb    $0xcf, r1
+       beq ok2
+       br not_ok
+ok2:
+
+       movw   $_y, r1
+       cbitw   $6,0(r1)
+       loadw   _y, r1
+       cmpb    $0x8f, r1
+       beq ok3
+       br not_ok
+ok3:
+       pass
+
+_y:    .word   0xff

diff --git a/sim/testsuite/sim/cr16/cmpi.cgs b/sim/testsuite/sim/cr16/cmpi.cgs
index e7302b874ddd6fffa5f5c0fd2ce4ce30d861f907..cff17e89a219c9968d17b42f0acb68bd6fa3fe3d 100644 (file)
--- a/sim/testsuite/sim/cr16/cmpi.cgs
+++ b/sim/testsuite/sim/cr16/cmpi.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for cmpi $src2,#$simm16
+# cr16 testcase for cmpi $imm16, reg
 # mach(): cr16 
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/cmpw.cgs b/sim/testsuite/sim/cr16/cmpw.cgs
index 5570a108bd3fd451f996161c8ed563d6fc3a9c96..9d333fb86b21ce78d2b0fa04a26f102d4ae28f3a 100644 (file)
--- a/sim/testsuite/sim/cr16/cmpw.cgs
+++ b/sim/testsuite/sim/cr16/cmpw.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for cmp $src1,$src2
+# cr16 testcase for cmp $imm, reg
 # mach(): cr16 
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/jlt.cgs b/sim/testsuite/sim/cr16/jlt.cgs
index 99c18626cbf3993e18a259cd67b5b839cab1e219..ca93cf119800e6add49c56fbc502ddec393d0da7 100644 (file)
--- a/sim/testsuite/sim/cr16/jlt.cgs
+++ b/sim/testsuite/sim/cr16/jlt.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for jlt (repl)
+# cr16 testcase for jlt (regp)
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/jump.cgs b/sim/testsuite/sim/cr16/jump.cgs
index b2b4774880fd57db89e00dee121866ba1c88bd48..df20c151d83a7c63487d7a7e193604fd4fdf241b 100644 (file)
--- a/sim/testsuite/sim/cr16/jump.cgs
+++ b/sim/testsuite/sim/cr16/jump.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for jmp $sr
+# cr16 testcase for jmp (regp)
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/loadd.cgs b/sim/testsuite/sim/cr16/loadd.cgs
index 03306876a7d7fea821c12383067a7befc1cf1c72..b6a851d1a36ece09ad5a30df835b1214a0c92909 100644 (file)
--- a/sim/testsuite/sim/cr16/loadd.cgs
+++ b/sim/testsuite/sim/cr16/loadd.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for ldb $dr,@$sr
+# cr16 testcase for loadd 0(regp),regp
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/loadw.cgs b/sim/testsuite/sim/cr16/loadw.cgs
index 47d92ad466392125edacaa8cf613c59039dad5d3..8faf61655a7f095072a57e8f403ef9476919e89d 100644 (file)
--- a/sim/testsuite/sim/cr16/loadw.cgs
+++ b/sim/testsuite/sim/cr16/loadw.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for ldb $dr,@$sr
+# cr16 testcase for loadw 0(regp), (regp)
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/lshb.cgs b/sim/testsuite/sim/cr16/lshb.cgs
index 877f33f51a690bc034c961e74bbbe8b141ede53e..59ddbba1a673314b31406847c686dc75b079b10f 100644 (file)
--- a/sim/testsuite/sim/cr16/lshb.cgs
+++ b/sim/testsuite/sim/cr16/lshb.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for sll $dr,$sr
+# cr16 testcase for lshb count, reg
 # mach(): cr16
 
        .include "testutils.inc"
 
        start
 
-       .global sll
-sll:
+       .global lshb
+lshb:
        movb $6, r4
        movb $1, r5
        lshb    r5, r4

diff --git a/sim/testsuite/sim/cr16/lshb_i.cgs b/sim/testsuite/sim/cr16/lshb_i.cgs
index 5302183f21ef8622c4fa107f508e582d7ab43279..10d308505100395b714e2ddee86f9c11a4516519 100644 (file)
--- a/sim/testsuite/sim/cr16/lshb_i.cgs
+++ b/sim/testsuite/sim/cr16/lshb_i.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for lshb_i $dr,#$uimm5
+# cr16 testcase for lshb_i $uimm5, reg
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/lshd.cgs b/sim/testsuite/sim/cr16/lshd.cgs
index d4554071f074122db42563d2acc3e010109130e3..e146ca11b6d7b9a4b1f9064b1b63437c761353d5 100644 (file)
--- a/sim/testsuite/sim/cr16/lshd.cgs
+++ b/sim/testsuite/sim/cr16/lshd.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for sll $dr,$sr
+# cr16 testcase for lshd  reg, regp
 # mach(): cr16
 
        .include "testutils.inc"
 
        start
 
-       .global sll
-sll:
+       .global lshd
+lshd:
        movd $0x12345678, (r4,r3)
        movw $0x10, r5
        lshd    r5, (r4,r3)

diff --git a/sim/testsuite/sim/cr16/lshd_i.cgs b/sim/testsuite/sim/cr16/lshd_i.cgs
index b517f38efab82a59b1e4f745965524e32474881e..aa65933648da2b9294b23a7e51305e70ec15a8c1 100644 (file)
--- a/sim/testsuite/sim/cr16/lshd_i.cgs
+++ b/sim/testsuite/sim/cr16/lshd_i.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for lshb_i $dr,#$uimm5
+# cr16 testcase for lshb_i $uimm5, regp
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/lshw.cgs b/sim/testsuite/sim/cr16/lshw.cgs
index 536fe2f3a21afcc8a57d59f8ba71783c85e391e5..a10edff0bc17edbc89f87aada8e7b936d1966632 100644 (file)
--- a/sim/testsuite/sim/cr16/lshw.cgs
+++ b/sim/testsuite/sim/cr16/lshw.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for sll $dr,$sr
+# cr16 testcase for lshw reg, reg
 # mach(): cr16
 
        .include "testutils.inc"
 
        start
 
-       .global sll
-sll:
+       .global lshw
+lshw:
        movw $0x1234, r4
        movw $8, r5
        lshw  r5, r4

diff --git a/sim/testsuite/sim/cr16/lshw_i.cgs b/sim/testsuite/sim/cr16/lshw_i.cgs
index c559f49fd57f5d73bb268d26bd92acb6b994c441..9e94a5ebf7f46d18457f8173e31d8e28f5a1f99e 100644 (file)
--- a/sim/testsuite/sim/cr16/lshw_i.cgs
+++ b/sim/testsuite/sim/cr16/lshw_i.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for lshb_i $dr,#$uimm5
+# cr16 testcase for lshb_i $uimm4, reg
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/movb.cgs b/sim/testsuite/sim/cr16/movb.cgs
index e235670d5ef8c04675f8576d0dc979e5464ea2b8..fc8fcba8bf20d7cb034175f8529c3ae8a4e4d678 100644 (file)
--- a/sim/testsuite/sim/cr16/movb.cgs
+++ b/sim/testsuite/sim/cr16/movb.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for movb $sr,$dr
+# cr16 testcase for movb $imm, reg
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/movd.cgs b/sim/testsuite/sim/cr16/movd.cgs
index 8e77b5ab5f0f9db78ad9a5b918e5bd7ac4bf3762..8b1b63840340a8c3c0c57ac32084b9394059ce9e 100644 (file)
--- a/sim/testsuite/sim/cr16/movd.cgs
+++ b/sim/testsuite/sim/cr16/movd.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for movd $sr,$dr
+# cr16 testcase for movd $imm32, regp
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/movw.cgs b/sim/testsuite/sim/cr16/movw.cgs
index cd92cba6d426870855cc184f5e6a96fff77b7145..e14afb0bbd536722ccf60cfa561dc7267f2fa048 100644 (file)
--- a/sim/testsuite/sim/cr16/movw.cgs
+++ b/sim/testsuite/sim/cr16/movw.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for movw $sr,$dr
+# cr16 testcase for movw $imm16, reg
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/movxb.cgs b/sim/testsuite/sim/cr16/movxb.cgs
index 301e9af48fea78136e5f54b181285de6e0eaecae..3c356c962ae5f6aa03d0e1592f8fdddef0184206 100644 (file)
--- a/sim/testsuite/sim/cr16/movxb.cgs
+++ b/sim/testsuite/sim/cr16/movxb.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for movb $sr,$dr
+# cr16 testcase for movb  $imm4, reg
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/movxw.cgs b/sim/testsuite/sim/cr16/movxw.cgs
index 44d954953405a17959089bef8c0ed0dee5cb1256..77dea808694bfcb34241229756bba831137e92cf 100644 (file)
--- a/sim/testsuite/sim/cr16/movxw.cgs
+++ b/sim/testsuite/sim/cr16/movxw.cgs
@@ -1,4 +1,4 @@
-# cr16 testcase for movw $sr,$dr
+# cr16 testcase for movw  reg, regp
 # mach(): cr16
 
        .include "testutils.inc"

diff --git a/sim/testsuite/sim/cr16/movzb.cgs b/sim/testsuite/sim/cr16/movzb.cgs
index e4de4b06e66ffe74f7c606b222be9c8823851725..acbe2b63457516cc56fa47d89914bc43c32d1048 100644 (file)
--- a/sim/testsuite/sim/cr16/movzb.cgs
+++ b/sim/testsuite/sim/cr16/movzb.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for movb $sr,$dr
+# cr16 testcase for movzb  reg, reg
 # mach(): cr16
 
        .include "testutils.inc"
 
        start
 
-       .global movb
-movb:
+       .global movzb
+movzb:
        movw $0x120f, r4
        movw $0x1200, r5
 

diff --git a/sim/testsuite/sim/cr16/movzw.cgs b/sim/testsuite/sim/cr16/movzw.cgs
index f3f58351653bb9a28a08603b2b860d36f1957daf..93855e464121ac58c6aff34b3f9740d03fa11aec 100644 (file)
--- a/sim/testsuite/sim/cr16/movzw.cgs
+++ b/sim/testsuite/sim/cr16/movzw.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for movw $sr,$dr
+# cr16 testcase for movzw  reg, regp
 # mach(): cr16
 
        .include "testutils.inc"
 
        start
 
-       .global movw
-movw:
+       .global movzw
+movzw:
        movb $0xff, r4
        movd $0x12345678,(r6, r5)
 

diff --git a/sim/testsuite/sim/cr16/mulb.cgs b/sim/testsuite/sim/cr16/mulb.cgs
index 6b77cb25ffb014c9a6d00286b5d0c5cad576685a..c4b859f22c53019d6f183cd806e4232ac9382e0e 100644 (file)
--- a/sim/testsuite/sim/cr16/mulb.cgs
+++ b/sim/testsuite/sim/cr16/mulb.cgs
@@ -7,11 +7,11 @@
 
        .global mulb
 mulb:
-       movw $0x2303,r4
-       movw $0x1207,r5
+       movw $0x1234,r4
+       movw $0x4567,r5
 
        mulb r4, r5
-       cmpb $21, r5
+       cmpb $0xec, r5
        beq ok1
 not_ok:
        fail

diff --git a/sim/testsuite/sim/cr16/muluw.cgs b/sim/testsuite/sim/cr16/muluw.cgs
index 3005a98594b68cbbdf50cb7c79abf5c293292bee..71f7ee08b4608a9cefa0172b820f7f8399d849f6 100644 (file)
--- a/sim/testsuite/sim/cr16/muluw.cgs
+++ b/sim/testsuite/sim/cr16/muluw.cgs
@@ -1,16 +1,16 @@
-# cr16 testcase for mul $dr,$sr
+# cr16 testcase for muluw reg, regp
 # mach(): cr16 
 
        .include "testutils.inc"
 
        start
 
-       .global mul
-mul:
+       .global muluw
+muluw:
        movw $0xfff,r4             # fix for 0xffff
        movd $0xffffffff,(r6,r5)
 
        muluw r4, (r6,r5)
-       test_h_grp "(r6,r5)", 0xfffff001
+       test_h_grp "(r6,r5)", 0xffef001
 
        pass

diff --git a/sim/testsuite/sim/cr16/mulw.cgs b/sim/testsuite/sim/cr16/mulw.cgs
index bee87faf80de8a503a65606b5f2a47de57ebcdef..cbd4552e338539ab9d75b5158e003532407811a4 100644 (file)
--- a/sim/testsuite/sim/cr16/mulw.cgs
+++ b/sim/testsuite/sim/cr16/mulw.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for mul $dr,$sr
+# cr16 testcase for mulw reg reg
 # mach(): cr16 
 
        .include "testutils.inc"
 
        start
 
-       .global mul
-mul:
+       .global mulw
+mulw:
        movw $0x1234,r4
        movw $0x1234,r5
 

diff --git a/sim/testsuite/sim/cr16/orb.cgs b/sim/testsuite/sim/cr16/orb.cgs
index 61f7f6e3e89414dc24456b535691283dd4b911e2..43ce26b305923fe6ab0721c2d851cd708d068d74 100644 (file)
--- a/sim/testsuite/sim/cr16/orb.cgs
+++ b/sim/testsuite/sim/cr16/orb.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for or $sr,$dr
+# cr16 testcase for orb $imm, reg
 # mach(): cr16
 
        .include "testutils.inc"
 
        start
 
-       .global or
-or:
+       .global orb
+orb:
        movb $3, r4
        movb $6, r5
 

diff --git a/sim/testsuite/sim/cr16/ord.cgs b/sim/testsuite/sim/cr16/ord.cgs
index b295f045fccac249930474b5e5367b4c9112ce4d..e682d3a74cdde2c23c902b34547331840032e10f 100644 (file)
--- a/sim/testsuite/sim/cr16/ord.cgs
+++ b/sim/testsuite/sim/cr16/ord.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for or $dr,$sr
+# cr16 testcase for ord $imm32, regp
 # mach(): cr16
 
        .include "testutils.inc"
 
        start
 
-       .global or
-or:
+       .global ord
+ord:
        movd $0x33333333, (r4,r3)
        movd $0x66666666, (r6,r5)
 

diff --git a/sim/testsuite/sim/cr16/orw.cgs b/sim/testsuite/sim/cr16/orw.cgs
index 138af881bdee4d08ab951bbc3912325af0d3b56a..4c1b529cba6e99c73e6b47852f7599251bbed564 100644 (file)
--- a/sim/testsuite/sim/cr16/orw.cgs
+++ b/sim/testsuite/sim/cr16/orw.cgs
@@ -1,12 +1,12 @@
-# cr16 testcase for or $dr,$sr
+# cr16 testcase for orw reg, reg
 # mach(): cr16
 
        .include "testutils.inc"
 
        start
 
-       .global or
-or:
+       .global orw
+orw:
        movw $3, r4
        movw $6, r5
 

diff --git a/sim/testsuite/sim/cr16/pop1.cgs b/sim/testsuite/sim/cr16/pop1.cgs
index 9ac46300e453361d45004d449890deecf24715de..cf2a02dbe99bdff9744604b707cf6b6542f0bc4b 100644 (file)
--- a/sim/testsuite/sim/cr16/pop1.cgs
+++ b/sim/testsuite/sim/cr16/pop1.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global pop1
 pop1:
        movd $0x1000, (sp)
        movw  $0x2f50, r3

diff --git a/sim/testsuite/sim/cr16/pop2.cgs b/sim/testsuite/sim/cr16/pop2.cgs
index 808f01e9a2e057c6e397b1a94e66c8502a857c39..aa3a9ec551ad8ed1eb8fce43a9c28d84ba21c37e 100644 (file)
--- a/sim/testsuite/sim/cr16/pop2.cgs
+++ b/sim/testsuite/sim/cr16/pop2.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global pop2
 pop2:
        movd $0x1000, (sp)
        movw  $0x2f50, r3

diff --git a/sim/testsuite/sim/cr16/pop3.cgs b/sim/testsuite/sim/cr16/pop3.cgs
index 35d893dae9561e029dad0a025f24cacee78ba669..13478f1f4e72e8de40e5017f718bce27670cbb41 100644 (file)
--- a/sim/testsuite/sim/cr16/pop3.cgs
+++ b/sim/testsuite/sim/cr16/pop3.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global pop3
 pop3:
        movd $0x1006, (sp)
        movd $0xabcd, (r3,r2)

diff --git a/sim/testsuite/sim/cr16/popret1.cgs b/sim/testsuite/sim/cr16/popret1.cgs
index aab42b30a23fb3ca5acc1bd1f48f79b03ce571ea..a34b0fbc706b7f6b378c1a7070c0dbed469f0884 100644 (file)
--- a/sim/testsuite/sim/cr16/popret1.cgs
+++ b/sim/testsuite/sim/cr16/popret1.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global popret1
 popret1:
        movd $0x1000, (sp)
        movw  $0x2f50, r3

diff --git a/sim/testsuite/sim/cr16/popret2.cgs b/sim/testsuite/sim/cr16/popret2.cgs
index 5ad65c548ffd1bd8a81e431f2e054f0582bca3d4..5a7f9056e8189cca4181b4a2f7fe1c7080a90808 100644 (file)
--- a/sim/testsuite/sim/cr16/popret2.cgs
+++ b/sim/testsuite/sim/cr16/popret2.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global popret2
 popret2:
        movd $0x1000, (sp)
        movw  $0x2f50, r3

diff --git a/sim/testsuite/sim/cr16/popret3.cgs b/sim/testsuite/sim/cr16/popret3.cgs
index c9c79df8c018ba48e3ce4a974959179baf6f1079..31aaa9b2aaf4a2c6dd91bb25b5aaabb1e8587dde 100644 (file)
--- a/sim/testsuite/sim/cr16/popret3.cgs
+++ b/sim/testsuite/sim/cr16/popret3.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global popret3
 popret3:
        movd $0x1006, (sp)
        movd $ok, (ra)

diff --git a/sim/testsuite/sim/cr16/push1.cgs b/sim/testsuite/sim/cr16/push1.cgs
index 025a69f2a84eb78a2aef5ab051fb99d603549188..12d50a614d61826821c55a0596f944c7087786db 100644 (file)
--- a/sim/testsuite/sim/cr16/push1.cgs
+++ b/sim/testsuite/sim/cr16/push1.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global push1
 push1:
        movd $0x100a, (sp)
        movd $0xabcd, (ra)

diff --git a/sim/testsuite/sim/cr16/push2.cgs b/sim/testsuite/sim/cr16/push2.cgs
index d6bd1b6607424c8c68ae634f36ea09363e7fac9d..76c1a374fc527e1d4d3193df73959ecafa0687af 100644 (file)
--- a/sim/testsuite/sim/cr16/push2.cgs
+++ b/sim/testsuite/sim/cr16/push2.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global push2
 push2:
        movd $0x1006, (sp)
        movw $0x2f50, r5

diff --git a/sim/testsuite/sim/cr16/push3.cgs b/sim/testsuite/sim/cr16/push3.cgs
index 6dbf04d9c3580120348e616c15096aea67f6428a..f9f5c2653c0d0ffb720128a67e42412adacb7276 100644 (file)
--- a/sim/testsuite/sim/cr16/push3.cgs
+++ b/sim/testsuite/sim/cr16/push3.cgs
@@ -4,6 +4,8 @@
        .include "testutils.inc"
 
        start
+
+       .global push1
 push1:
        movd $0x1006, (sp)
        movd $0xabcd, (ra)

diff --git a/sim/testsuite/sim/cr16/sbitb.cgs b/sim/testsuite/sim/cr16/sbitb.cgs
new file mode 100644 (file)
index 0000000..b98329c
--- /dev/null
+++ b/sim/testsuite/sim/cr16/sbitb.cgs
@@ -0,0 +1,35 @@
+# cr16 testcase for sbitb $count, reg/regp/mem
+# mach:         cr16
+
+       .include "testutils.inc"
+
+       start
+
+       .global sbitb
+sbitb:
+       sbitb   $0,_y
+       loadw   _y, r1
+       cmpb    $0xf1, r1
+       beq ok1
+not_ok:
+       fail
+
+ok1:
+       movd   $_y, (r1,r0)
+       sbitb   $1,0(r1,r0)
+       loadw   _y, r1
+       cmpb    $0xf3, r1
+       beq ok2
+       br not_ok
+ok2:
+
+       movw   $_y, r1
+       sbitb   $2,0(r1)
+       loadw   _y, r1
+       cmpb    $0xf7, r1
+       beq ok3
+       br not_ok
+ok3:
+       pass
+
+_y:    .word   0xf0

diff --git a/sim/testsuite/sim/cr16/sbitw.cgs b/sim/testsuite/sim/cr16/sbitw.cgs
new file mode 100644 (file)
index 0000000..2a9a828
--- /dev/null
+++ b/sim/testsuite/sim/cr16/sbitw.cgs
@@ -0,0 +1,35 @@
+# cr16 testcase for sbitw
+# mach:         cr16
+
+       .include "testutils.inc"
+
+       start
+
+       .global sbitw
+sbitw:
+       sbitw   $4,_y
+       loadw   _y, r1
+       cmpb    $0x1f, r1
+       beq ok1
+not_ok:
+       fail
+
+ok1:
+       movd   $_y, (r1,r0)
+       sbitw   $5,0(r1,r0)
+       loadw   _y, r1
+       cmpb    $0x3f, r1
+       beq ok2
+       br not_ok
+ok2:
+
+       movw   $_y, r1
+       sbitw   $6,0(r1)
+       loadw   _y, r1
+       cmpb    $0x7f, r1
+       beq ok3
+       br not_ok
+ok3:
+       pass
+
+_y:    .word   0x0f

diff --git a/sim/testsuite/sim/cr16/tbit.cgs b/sim/testsuite/sim/cr16/tbit.cgs
new file mode 100644 (file)
index 0000000..ac1b7e2
--- /dev/null
+++ b/sim/testsuite/sim/cr16/tbit.cgs
@@ -0,0 +1,31 @@
+# cr16 testcase for tbit
+# mach:         cr16
+
+       .include "testutils.inc"
+
+       start
+
+       .global tbit
+tbit:
+       movw $0, r1
+       lpr  r1, psr
+       movw $0x7, r1
+       tbit $0, r1
+       spr  psr, r1
+       cmpb $0x20, r1
+       beq ok1
+not_ok:
+       fail
+
+ok1:
+       movw $0, r1
+       lpr     r1, psr
+       movw $0xa, r1
+       movw $0x1, r2
+       tbit r2,r1
+       spr  psr, r1
+       cmpb $0x20, r1
+       beq ok2
+       br not_ok
+ok2:
+       pass

diff --git a/sim/testsuite/sim/cr16/tbitb.cgs b/sim/testsuite/sim/cr16/tbitb.cgs
new file mode 100644 (file)
index 0000000..57a8ab2
--- /dev/null
+++ b/sim/testsuite/sim/cr16/tbitb.cgs
@@ -0,0 +1,33 @@
+# cr16 testcase for tbitb
+# mach:         cr16
+
+       .include "testutils.inc"
+
+       start
+
+       .global tbitb
+tbitb:
+       movw $0, r1
+       lpr     r1, psr
+       movw $_y, r1
+       tbitb   $0, 0(r1)
+       spr  psr, r1
+       cmpb    $0x20, r1
+       beq ok1
+not_ok:
+       fail
+
+ok1:
+       movw $0, r1
+       lpr     r1, psr
+       movd   $_y, (r1,r0)
+       tbitb   $1,0(r1,r0)
+       spr  psr, r1
+       cmpb    $0x20, r1
+       beq ok2
+       br not_ok
+ok2:
+
+       pass
+
+_y:    .word   0xf7

diff --git a/sim/testsuite/sim/cr16/tbitw.cgs b/sim/testsuite/sim/cr16/tbitw.cgs
new file mode 100644 (file)
index 0000000..018c73e
--- /dev/null
+++ b/sim/testsuite/sim/cr16/tbitw.cgs
@@ -0,0 +1,33 @@
+# cr16 testcase for tbitw
+# mach:         cr16
+
+       .include "testutils.inc"
+
+       start
+
+       .global tbitw
+tbitw:
+       movw $0, r1
+       lpr     r1, psr
+       tbitw   $0,_y
+       spr  psr, r1
+       cmpb    $0x20, r1
+       beq ok1
+not_ok:
+       fail
+
+ok1:
+       movw $0, r1
+       lpr     r1, psr
+       movd   $_y, (r1,r0)
+       tbitw   $1,0(r1,r0)
+       loadw   _y, r1
+       spr  psr, r1
+       cmpb    $0x20, r1
+       beq ok2
+       br not_ok
+ok2:
+
+       pass
+
+_y:    .word   0xf7