(no commit message)

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 2583d794136f5b439604cc0fe0fd95e1b5a7a192..1d8fe9dc2efe85e338da7365ae4a81590788abb0 100644 (file)
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -384,7 +384,8 @@ simply does not exist in most Scalar 64-bit ISAs. Although Power ISA
 comes close with `divdeu`, by placing the dividend in the upper half
 of a 128-bit computation, the lower half is zero.  Again Power ISA
 has a Packed SIMD instruction `vdivuq` which is a 128/128
-(quad) divide, not a 128/64.  Some investigation into
+(quad) divide, not a 128/64, and its use would require considerable
+effort to move registers to and from GPRs.  Some investigation into
 soft-implementations of 128/128 or 128/64 divide show it to be typically
 implemented bit-wise, with all that implies.