radv/gfx10: disable CLEAR_STATE
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 25 Jun 2019 09:48:27 +0000 (11:48 +0200)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Sun, 7 Jul 2019 15:51:32 +0000 (17:51 +0200)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_device.c
src/amd/vulkan/si_cmd_buffer.c

index 2d5e5f511e02fe777acf2e4601fff79f822b3e8b..e429192ce898ddadb59dccb7ccec5caa8422304d 100644 (file)
@@ -354,7 +354,8 @@ radv_physical_device_init(struct radv_physical_device *device,
        /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
         * on GFX6.
         */
-       device->has_clear_state = device->rad_info.chip_class >= GFX7;
+       device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
+                                 device->rad_info.chip_class <= GFX9;
 
        device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
 
index 7a2099d7d1abf4700cf496d46f34861b788a677d..b3d12df45755f1b6b9c301fe04ba20840ff732b8 100644 (file)
@@ -161,10 +161,6 @@ si_emit_graphics(struct radv_physical_device *physical_device,
 {
        int i;
 
-       /* Only GFX6 can disable CLEAR_STATE for now. */
-       assert(physical_device->has_clear_state ||
-              physical_device->rad_info.chip_class == GFX6);
-
        radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
        radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
        radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));