intel/genxml: Make some 3DSTATE_PS fields more consistent
authorJason Ekstrand <jason.ekstrand@intel.com>
Sat, 12 Nov 2016 17:35:37 +0000 (09:35 -0800)
committerJason Ekstrand <jason.ekstrand@intel.com>
Wed, 16 Nov 2016 18:08:58 +0000 (10:08 -0800)
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
src/intel/blorp/blorp_genX_exec.h
src/intel/genxml/gen6.xml
src/intel/genxml/gen7.xml
src/intel/genxml/gen75.xml
src/intel/vulkan/gen7_pipeline.c

index 07c335aee52f3a483641c72786a1e67e03da3cef..4a98371e6f6e25796d177e65a838e58b5c3bee1c 100644 (file)
@@ -630,9 +630,9 @@ blorp_emit_ps_config(struct blorp_batch *batch,
 #endif
 
       if (prog_data) {
-         ps.DispatchGRFStartRegisterforConstantSetupData0 =
+         ps.DispatchGRFStartRegisterForConstantSetupData0 =
             prog_data->base.dispatch_grf_start_reg;
-         ps.DispatchGRFStartRegisterforConstantSetupData2 =
+         ps.DispatchGRFStartRegisterForConstantSetupData2 =
             prog_data->dispatch_grf_start_reg_2;
 
          ps.KernelStartPointer0 = params->wm_prog_kernel;
@@ -692,9 +692,9 @@ blorp_emit_ps_config(struct blorp_batch *batch,
       if (prog_data) {
          wm.ThreadDispatchEnable = true;
 
-         wm.DispatchGRFStartRegisterforConstantSetupData0 =
+         wm.DispatchGRFStartRegisterForConstantSetupData0 =
             prog_data->base.dispatch_grf_start_reg;
-         wm.DispatchGRFStartRegisterforConstantSetupData2 =
+         wm.DispatchGRFStartRegisterForConstantSetupData2 =
             prog_data->dispatch_grf_start_reg_2;
 
          wm.KernelStartPointer0 = params->wm_prog_kernel;
index ad130d95738c32fdb430430c8f9e45d67850a741..60e403a6d34394ed848c9a9146049c71bafc9911 100644 (file)
     <field name="Depth Buffer Clear" start="158" end="158" type="bool"/>
     <field name="Depth Buffer Resolve Enable" start="156" end="156" type="bool"/>
     <field name="Hierarchical Depth Buffer Resolve Enable" start="155" end="155" type="bool"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [0]" start="144" end="150" type="uint"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [1]" start="136" end="142" type="uint"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [2]" start="128" end="134" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [0]" start="144" end="150" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [1]" start="136" end="142" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [2]" start="128" end="134" type="uint"/>
     <field name="Maximum Number of Threads" start="185" end="191" type="uint"/>
     <field name="Legacy Diamond Line Rasterization" start="183" end="183" type="bool"/>
     <field name="Pixel Shader Kill Pixel" start="182" end="182" type="bool"/>
index 9bf3814344594e2b1b28145fc9cda822066657ec..7ac421fed60e49d07e1825cbdef9961fff7753f8 100644 (file)
     <field name="32 Pixel Dispatch Enable" start="130" end="130" type="bool"/>
     <field name="16 Pixel Dispatch Enable" start="129" end="129" type="bool"/>
     <field name="8 Pixel Dispatch Enable" start="128" end="128" type="bool"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [0]" start="176" end="182" type="uint"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [1]" start="168" end="174" type="uint"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [2]" start="160" end="166" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [0]" start="176" end="182" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [1]" start="168" end="174" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [2]" start="160" end="166" type="uint"/>
     <field name="Kernel Start Pointer[1]" start="198" end="223" type="offset"/>
     <field name="Kernel Start Pointer[2]" start="230" end="255" type="offset"/>
   </instruction>
index 280e7c4aba3d3fd47d7baf04d816022f964671da..2e61e7bea07ff97f2126cf77d984d5972562b184 100644 (file)
     <field name="32 Pixel Dispatch Enable" start="130" end="130" type="bool"/>
     <field name="16 Pixel Dispatch Enable" start="129" end="129" type="bool"/>
     <field name="8 Pixel Dispatch Enable" start="128" end="128" type="bool"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [0]" start="176" end="182" type="uint"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [1]" start="168" end="174" type="uint"/>
-    <field name="Dispatch GRF Start Register for Constant/Setup Data [2]" start="160" end="166" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [0]" start="176" end="182" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [1]" start="168" end="174" type="uint"/>
+    <field name="Dispatch GRF Start Register For Constant/Setup Data [2]" start="160" end="166" type="uint"/>
     <field name="Kernel Start Pointer[1]" start="198" end="223" type="offset"/>
     <field name="Kernel Start Pointer[2]" start="230" end="255" type="offset"/>
   </instruction>
index 3765d14b90934a343936f4c66cca9bbf3dbe668d..40e1d8130cb952c805cdd1a0ad8d18f4cc148bc8 100644 (file)
@@ -168,10 +168,10 @@ genX(graphics_pipeline_create)(
          ps._16PixelDispatchEnable        = wm_prog_data->dispatch_16;
          ps._8PixelDispatchEnable         = wm_prog_data->dispatch_8;
 
-         ps.DispatchGRFStartRegisterforConstantSetupData0 =
+         ps.DispatchGRFStartRegisterForConstantSetupData0 =
             wm_prog_data->base.dispatch_grf_start_reg,
-         ps.DispatchGRFStartRegisterforConstantSetupData1 = 0,
-         ps.DispatchGRFStartRegisterforConstantSetupData2 =
+         ps.DispatchGRFStartRegisterForConstantSetupData1 = 0,
+         ps.DispatchGRFStartRegisterForConstantSetupData2 =
             wm_prog_data->dispatch_grf_start_reg_2;
 
          /* Haswell requires the sample mask to be set in this packet as well as