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author
Eddie Hung
<eddie@fpgeh.com>
Sat, 13 Jul 2019 07:52:21 +0000
(
00:52
-0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Sat, 13 Jul 2019 07:52:21 +0000
(
00:52
-0700)
passes/techmap/abc9.cc
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diff --git
a/passes/techmap/abc9.cc
b/passes/techmap/abc9.cc
index 4a6ec3a47ee254550ec1a24a9ef4bbcab0c04574..658bb1225cef370d02bfbb08fb8ee6a2c76374b3 100644
(file)
--- a/
passes/techmap/abc9.cc
+++ b/
passes/techmap/abc9.cc
@@
-787,6
+787,11
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
sink_cell->setParam("\\LUT", mask);
}
+ // Since we have rewritten all sinks (which we know
+ // to be only LUTs) to be after the inverter, we can
+ // go ahead and clone the LUT with the expectation
+ // that the original driving LUT will become dangling
+ // and get cleaned away
clone_lut:
driver_mask = driver_lut->getParam("\\LUT");
for (auto &b : driver_mask.bits) {