aarch64: Fix SVE ACLE handling of SImode pointers

This long-overdue patch promotes SImode pointers to DImode addresses,
avoiding various ICEs in the existing tests.

2020-01-21  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve-builtins.h
	(function_expander::convert_to_pmode): Declare.
	* config/aarch64/aarch64-sve-builtins.cc
	(function_expander::convert_to_pmode): New function.
	(function_expander::get_contiguous_base): Use it.
	(function_expander::prepare_gather_address_operands): Likewise.
	* config/aarch64/aarch64-sve-builtins-sve2.cc
	(svwhilerw_svwhilewr_impl::expand): Likewise.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3b7df184ded353cc2e626f83f23e18f7b2e47e63..63ff0bf0d83b716daa708127b4258349a586929f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-01-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-sve-builtins.h
+       (function_expander::convert_to_pmode): Declare.
+       * config/aarch64/aarch64-sve-builtins.cc
+       (function_expander::convert_to_pmode): New function.
+       (function_expander::get_contiguous_base): Use it.
+       (function_expander::prepare_gather_address_operands): Likewise.
+       * config/aarch64/aarch64-sve-builtins-sve2.cc
+       (svwhilerw_svwhilewr_impl::expand): Likewise.
+
 2020-01-21  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
        PR target/92424

diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
index fa3b50680ba0588bd39438e968a14a33652c0a4b..53b16511623699eee4b30a0dd73af32c7ef80663 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
@@ -442,6 +442,8 @@ public:
   rtx
   expand (function_expander &e) const OVERRIDE
   {
+    for (unsigned int i = 0; i < 2; ++i)
+      e.args[i] = e.convert_to_pmode (e.args[i]);
     return e.use_exact_insn (code_for_while (m_unspec, Pmode, e.gp_mode (0)));
   }
 

diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc
index 587530a61bdb789ca32fc31446f67816227b6a4e..3d1b610cfd6ebaa1d4805c99d0179660c248501e 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve-builtins.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
@@ -2602,12 +2602,21 @@ function_expander::overlaps_input_p (rtx x)
   return false;
 }
 
+/* Convert ptr_mode value X to Pmode.  */
+rtx
+function_expander::convert_to_pmode (rtx x)
+{
+  if (ptr_mode == SImode)
+    x = simplify_gen_unary (ZERO_EXTEND, DImode, x, SImode);
+  return x;
+}
+
 /* Return the base address for a contiguous load or store function.
    MEM_MODE is the mode of the addressed memory.  */
 rtx
 function_expander::get_contiguous_base (machine_mode mem_mode)
 {
-  rtx base = args[1];
+  rtx base = convert_to_pmode (args[1]);
   if (mode_suffix_id == MODE_vnum)
     {
       /* Use the size of the memory mode for extending loads and truncating
@@ -2814,9 +2823,7 @@ function_expander::prepare_gather_address_operands (unsigned int argno,
     {
       /* Scalar base, vector displacement.  This is the order that the md
         pattern wants.  */
-      if (Pmode == SImode)
-       args[argno] = simplify_gen_unary (ZERO_EXTEND, DImode,
-                                         args[argno], SImode);
+      args[argno] = convert_to_pmode (args[argno]);
       vector_type = displacement_vector_type ();
       if (units == UNITS_elements && !scaled_p)
        shift_idx = argno + 1;

diff --git a/gcc/config/aarch64/aarch64-sve-builtins.h b/gcc/config/aarch64/aarch64-sve-builtins.h
index f307233f777632b69c3a7ff8515c7db61473aa75..9513b4973683eae86fd68b51b84d2d65fce04e0f 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve-builtins.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins.h
@@ -526,6 +526,7 @@ public:
 
   bool overlaps_input_p (rtx);
 
+  rtx convert_to_pmode (rtx);
   rtx get_contiguous_base (machine_mode);
   rtx get_fallback_value (machine_mode, unsigned int,
                          unsigned int, unsigned int &);