Fix native port we signal (fixes #44)

diff --git a/gram/frontend/wishbone.py b/gram/frontend/wishbone.py
index 19bfb8f5e616393826bac7f68efa4789a998c596..44856bd2745fac71d6fce29ba2ff1e85f408b1d2 100644 (file)
--- a/gram/frontend/wishbone.py
+++ b/gram/frontend/wishbone.py
@@ -40,7 +40,7 @@ class gramWishbone(Peripheral, Elaboratable):
         with m.Switch(self.bus.adr & ratio_bitmask):
             for i in range(self.ratio):
                 with m.Case(i):
-                    m.d.comb += self.native_port.wdata.we.eq(Repl(self.bus.sel, self.bus.data_width//self.bus.granularity) << (self.ratio*i))
+                    m.d.comb += self.native_port.wdata.we.eq(Repl(self.bus.sel, self.bus.granularity//8) << (self.ratio*i))
 
         with m.Switch(self.bus.adr & ratio_bitmask):
             for i in range(self.ratio):