sctx->b.create_compute_state = si_create_compute_state;
sctx->b.delete_compute_state = si_delete_compute_state;
sctx->b.bind_compute_state = si_bind_compute_state;
-/* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
sctx->b.set_compute_resources = si_set_compute_resources;
sctx->b.set_global_binding = si_set_global_binding;
sctx->b.launch_grid = si_launch_grid;
{
struct radeon_cmdbuf *cs = sctx->dma_cs;
- /* NOP waits for idle on Evergreen and later. */
+ /* NOP waits for idle. */
if (sctx->chip_class >= CIK)
radeon_emit(cs, 0x00000000); /* NOP */
else
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
{
- /* Offsets apply to EG+ */
static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
params->start_offset = offsets[index];
params->end_offset = 88 + offsets[index];
if (!is_flushed_depth &&
ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
- bpe = 4; /* stencil is allocated separately on evergreen */
+ bpe = 4; /* stencil is allocated separately */
} else {
bpe = util_format_get_blocksize(ptex->format);
assert(util_is_power_of_two_or_zero(bpe));