Added correct handling of $memwr priority

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 1b6fc1d8bccb139afa1b301a1bcf3f3dfab4e740..e44b2d361e1079853cacd1d8ffb18bd38e330369 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1271,6 +1271,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
                        cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
                        cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
+
+                       cell->parameters["\\PRIORITY"] = RTLIL::Const(RTLIL::autoidx-1);
                }
                break;
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 4916ca728984d864cb8ad9b063a9b11831fb3c21..1311f31cce733940a38053b9ff1a81876e767b0c 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -567,6 +567,7 @@ namespace {
                                param("\\MEMID");
                                param("\\CLK_ENABLE");
                                param("\\CLK_POLARITY");
+                               param("\\PRIORITY");
                                port("\\CLK", 1);
                                port("\\EN", 1);
                                port("\\ADDR", param("\\ABITS"));

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 61713e74dd7c1de5a004179ea42657d84c119ca4..b84e1b30e26c45f34624849029e074cf8d3ddb13 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -272,6 +272,9 @@ the \B{CLK} input is not used.
 \item \B{CLK\_POLARITY} \\
 Clock is active on positive edge if this parameter has the value {\tt 1'b1} and on the negative
 edge if this parameter is {\tt 1'b0}.
+
+\item \B{PRIORITY} \\
+The cell with the higher integer value in this parameter wins a write conflict.
 \end{itemize}
 
 The HDL frontend models a memory using RTLIL::Memory objects and asynchronous

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index ca1a3666f86d76f9bcd789d2f89cbd6120613010..ad4df228e9a6cc1d0e26880e247d6f6cdd22b4e2 100644 (file)
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -20,9 +20,19 @@
 #include "kernel/register.h"
 #include "kernel/log.h"
 #include <sstream>
+#include <algorithm>
 #include <stdlib.h>
 #include <assert.h>
 
+static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
+{
+       if (a->type == "$memrd" && b->type == "$memrd")
+               return a->name < b->name;
+       if (a->type == "$memrd" || b->type == "$memrd")
+               return (a->type == "$memrd") < (b->type == "$memrd");
+       return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
+}
+
 static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 {
        log("Collecting $memrd and $memwr for memory `%s' in module `%s':\n",
@@ -48,11 +58,18 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
        RTLIL::SigSpec sig_rd_data;
 
        std::vector<std::string> del_cell_ids;
+       std::vector<RTLIL::Cell*> memcells;
 
-       for (auto &cell_it : module->cells)
-       {
+       for (auto &cell_it : module->cells) {
                RTLIL::Cell *cell = cell_it.second;
+               if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name)
+                       memcells.push_back(cell);
+       }
+
+       std::sort(memcells.begin(), memcells.end(), memcells_cmp);
 
+       for (auto cell : memcells)
+       {
                if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
                {
                        wr_ports++;

diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index aea014a284213f30923bd87b0023ffd10ba65a09..eaeee01dd39cfc4bfd687cad507550f65e463e00 100644 (file)
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -1,4 +1,21 @@
 
+module test00(clk, setA, setB, y);
+
+input clk, setA, setB;
+output y;
+reg mem [1:0];
+
+always @(posedge clk) begin
+       if (setA) mem[0] <= 0;  // this is line 9
+       if (setB) mem[0] <= 1;  // this is line 10
+end
+
+assign y = mem[0];
+
+endmodule
+
+// ----------------------------------------------------------
+
 module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
 
 input clk, wr_en;