Use new memory port API

diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py
index 3a50b3d38cc1db3545c8558f3f352b2095189044..ce6bbaca1965e5e03efa3ad053612abcfd877bed 100644 (file)
--- a/milkymist/dvisampler/chansync.py
+++ b/milkymist/dvisampler/chansync.py
@@ -21,6 +21,7 @@ class _SyncBuffer(Module):
                self.specials += storage
 
                wrport = storage.get_port(write_capable=True)
+               self.specials += wrport
                self.comb += [
                        wrport.adr.eq(produce),
                        wrport.dat_w.eq(self.din),
@@ -29,6 +30,7 @@ class _SyncBuffer(Module):
                self.sync += _inc(produce, depth)
 
                rdport = storage.get_port(async_read=True)
+               self.specials += rdport
                self.comb += [
                        rdport.adr.eq(consume),
                        self.dout.eq(rdport.dat_r)

diff --git a/milkymist/dvisampler/edid.py b/milkymist/dvisampler/edid.py
index c2726a4717c7a72e8bb66ef8c1943ac3699a2e43..012a75308c0afc714abacf3b93430b269f04dde9 100644 (file)
--- a/milkymist/dvisampler/edid.py
+++ b/milkymist/dvisampler/edid.py
@@ -89,6 +89,7 @@ class EDID(Module, AutoCSR):
                        )
                ]
                rdport = self.mem.get_port()
+               self.specials += rdport
                self.comb += rdport.adr.eq(offset_counter)
                data_bit = Signal()
 

diff --git a/top.py b/top.py
index 1ab79e12d3684a4881bf17d3e932b8a2d377ed21..6dbb0f54186785117bfc5e53511738c10b9a2308 100644 (file)
--- a/top.py
+++ b/top.py
@@ -86,8 +86,8 @@ class SoC(Module):
                "uart":                 0,
                "timer0":               1,
                "minimac":              2,
-               "dvisampler0":  3,
-               "dvisampler1":  4,
+               "dvisampler0":  3,
+               "dvisampler1":  4,
        }
 
        def __init__(self, platform):