temporary hack disabling SV in anything other than user mode

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 7eaa7d2f045126d21770dbed962d73eedb26813c..9e27b801fd2e577d6e81fefed8e2a48d7e6f54f4 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -14,7 +14,10 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   // in a stack of other things that are needed.
   insn_bits_t bits = s_insn.bits();
 #ifndef USING_NOREGS
-  int vlen = p->get_state()->vl;
+  int vlen = 0;
+  if (p->get_state()->prv == 0) { // XXX HACK - disable in supervisor mode
+    vlen = p->get_state()->vl;
+  }
   // need to know if register is used as float or int.
   // REGS_PATTERN is generated by id_regs.py (per opcode)
   unsigned int floatintmap = REGS_PATTERN;
@@ -29,8 +32,9 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   sv_insn_t insn(p, bits, floatintmap, PRED_ARGS, OFFS_ARGS);
   if (vlen > 0)
   {
-    fprintf(stderr, "pre-ex reg %s %x rd %ld rs1 %ld rs2 %ld vlen %d\n",
-            xstr(INSN), INSNCODE, s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
+    fprintf(stderr, "pre-ex reg %s %x %ld rd %ld rs1 %ld rs2 %ld vlen %d\n",
+            xstr(INSN), INSNCODE, p->get_state()->prv,
+            s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
             vlen);
 #ifdef INSN_CATEGORY_TWINPREDICATION
 #ifdef INSN_TYPE_C_STACK_LD
@@ -69,7 +73,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
     if (*dest_offs >= vlen) {
         break;
     }
-#ifdef INSN_C_MV
+#ifdef INSN_C_LWSP
         fprintf(stderr, "pre twin reg %s src %d dest %d pred %lx %lx\n",
             xstr(INSN), *src_offs, *dest_offs, src_pred, dest_pred);
 #endif
@@ -100,13 +104,13 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
             xstr(INSN), *src_offs, *dest_offs, src_pred, dest_pred);
     }
 #endif
-#ifdef INSN_C_MV
-    fprintf(stderr, "pre loop reg %s %x vloop %d %d %d" \
-                      "vlen %d stop %d pred %lx rdv %lx rd %d rvc2 %d\n",
+#ifdef INSN_C_LWSP
+    fprintf(stderr, "pre %s %x vloop %d %d %d" \
+                      "vlen %d stop %d pred %lx rdv %lx rd %d rvc2 %d sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rd()),
-                insn._rd(), insn._rvc_rs2());
+                insn._rd(), insn.rvc_lwsp_imm(), READ_REG(X_SP));
 #endif
       #include INCLUDEFILE
 #ifdef DEST_PREDINT