+2018-12-22 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function.
+ (riscv_gdbarch_init): Register new function with gdbarch.
+ * riscv-tdep.h: New enum to define RISC-V DWARF register numbers.
+
2018-12-21 Simon Marchi <simon.marchi@ericsson.com>
* minsyms.c (mst_str): New.
}
}
+/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
+
+static int
+riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+{
+ if (reg < RISCV_DWARF_REGNUM_X31)
+ return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
+
+ else if (reg < RISCV_DWARF_REGNUM_F31)
+ return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
+
+ return -1;
+}
+
/* Initialize the current architecture based on INFO. If possible,
re-use an architecture from ARCHES, which is a list of
architectures already created during this debugging session.
/* Register architecture. */
riscv_add_reggroups (gdbarch);
+ /* Internal <-> external register number maps. */
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum);
+
/* We reserve all possible register numbers for the known registers.
This means the target description mechanism will add any target
specific registers after this number. This helps make debugging GDB
RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
};
+/* RiscV DWARF register numbers. */
+enum
+{
+ RISCV_DWARF_REGNUM_X0 = 0,
+ RISCV_DWARF_REGNUM_X31 = 31,
+ RISCV_DWARF_REGNUM_F0 = 32,
+ RISCV_DWARF_REGNUM_F31 = 63,
+};
+
/* RISC-V specific per-architecture information. */
struct gdbarch_tdep
{