platforms/kc705: generate clocks for SDRAM

diff --git a/targets/kc705.py b/targets/kc705.py
index bcafe9c2bdf04c6d6cc89b63d00800ad77ebe4a0..a4ce686b4995a1e7c586293bc4c83105a4c5f3e4 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -1,4 +1,5 @@
 from migen.fhdl.std import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.bus import wishbone
 
 from misoclib.gensoc import GenSoC, IntegratedBIOS
@@ -6,6 +7,8 @@ from misoclib.gensoc import GenSoC, IntegratedBIOS
 class _CRG(Module):
        def __init__(self, platform):
                self.clock_domains.cd_sys = ClockDomain()
+               self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+               self.clock_domains.cd_clk200 = ClockDomain()
 
                clk200 = platform.request("clk200")
                clk200_se = Signal()
@@ -13,29 +16,47 @@ class _CRG(Module):
 
                pll_locked = Signal()
                pll_fb = Signal()
-               pll_clk1x = Signal()
-               self.specials += Instance("PLLE2_BASE",
-                       p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
+               pll_sys = Signal()
+               pll_sys4x = Signal()
+               pll_clk200 = Signal()
+               self.specials += [
+                       Instance("PLLE2_BASE",
+                               p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
 
-                       # VCO @ 1GHz
-                       p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
-                       p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
-                       i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
+                               # VCO @ 1GHz
+                               p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
+                               p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
+                               i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
 
-                       # 125MHz
-                       p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk1x,
+                               # 125MHz
+                               p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
 
-                       p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=270.0, #o_CLKOUT1=,
+                               # 500MHz
+                               p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
 
-                       p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
+                               # 200MHz
+                               p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200,
 
-                       p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
+                               p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
 
-                       p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
-               )
-               self.specials += Instance("BUFG", i_I=pll_clk1x, o_O=self.cd_sys.clk)
-               self.specials += Instance("FD", p_INIT=1, i_D=~pll_locked,
-                       i_C=self.cd_sys.clk, o_Q=self.cd_sys.rst)
+                               p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
+                       ),
+                       Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
+                       Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
+                       Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
+                       AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
+                       AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),
+               ]
+
+               reset_counter = Signal(4, reset=15)
+               ic_reset = Signal(reset=1)
+               self.sync.clk200 += \
+                       If(reset_counter != 0,
+                               reset_counter.eq(reset_counter - 1)
+                       ).Else(
+                               ic_reset.eq(0)
+                       )
+               self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
 
 class BaseSoC(GenSoC, IntegratedBIOS):
        default_platform = "kc705"