arm: Invalidate cached TLB configuration in drainResume

Currently, we invalidate the cached miscregs in
TLB::unserialize(). The intended use of the drainResume() method is to
invalidate cached state and prepare the system to resume after a CPU
handover or (un)serialization. This patch moves the TLB miscregs
invalidation code to the drainResume() method to avoid surprising
behavior.

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index e7ac935e67aeefcade1e5384c81d09f41ab4f593..170d819d8a4e154f2f083c280930e10be2071fe3 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -252,6 +252,14 @@ TLB::flushMva(Addr mva)
     flushTlbMva++;
 }
 
+void
+TLB::drainResume()
+{
+    // We might have unserialized something or switched CPUs, so make
+    // sure to re-read the misc regs.
+    miscRegValid = false;
+}
+
 void
 TLB::serialize(ostream &os)
 {
@@ -278,7 +286,6 @@ TLB::unserialize(Checkpoint *cp, const string &section)
     for(int i = 0; i < min(size, num_entries); i++){
         table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
     }
-    miscRegValid = false;
 }
 
 void

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 968699764fbaf2c8b0f4f34a12c87849c1310bdb..f5c7320ed322a02d8979025907008a7749f42c9d 100644 (file)
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -208,6 +208,8 @@ class TLB : public BaseTLB
     Fault translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
 
+    void drainResume();
+
     // Checkpointing
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);