uart: remove litescope dependency for UARTWishboneBridge and remove frontend

diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
index 582e50bc7fa5351ea8ea530efe7a4cdeaea240d6..99b117c8645158a16477146c8d62966c0a35c980 100644 (file)
--- a/misoclib/com/liteeth/example_designs/targets/base.py
+++ b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -7,7 +7,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+from misoclib.com.uart.wishbone import UARTWishboneBridge
 
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII

diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
index f129135547c09d27a6b11c2d53e4456acb6e4288..c4c9e550714b565f3ebbcfc328450c550ac01cfc 100644 (file)
--- a/misoclib/com/litepcie/example_designs/targets/dma.py
+++ b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -7,7 +7,7 @@ from migen.genlib.misc import timeline
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
 
-from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+from misoclib.com.uart.wishbone import UARTWishboneBridge
 
 from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
 from misoclib.com.litepcie.core import Endpoint

diff --git a/misoclib/com/liteusb/frontend/wishbone.py b/misoclib/com/liteusb/frontend/wishbone.py
index c2c00d30cb00838d789ccb73a23266b90dba5fa9..394e2c4ce2330ee8e47c3f5f7a08dac9b2a5c3bb 100644 (file)
--- a/misoclib/com/liteusb/frontend/wishbone.py
+++ b/misoclib/com/liteusb/frontend/wishbone.py
@@ -1,9 +1,9 @@
 from migen.fhdl.std import *
 
 from misoclib.com.liteusb.common import *
-from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
+from misoclib.tools.wishbone import WishboneStreamingBridge
 
-class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
+class LiteUSBWishboneBridge(WishboneStreamingBridge):
     def __init__(self, port, clk_freq):
-        LiteScopeWishboneBridge.__init__(self, port, clk_freq)
+        WishboneStreamingBridge.__init__(self, port, clk_freq)
         self.comb += port.sink.dst.eq(port.tag)

diff --git a/misoclib/com/uart/frontend/__init__.py b/misoclib/com/uart/frontend/__init__.py
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/misoclib/com/uart/frontend/wishbone.py b/misoclib/com/uart/frontend/wishbone.py
deleted file mode 100644 (file)
index d149986..0000000
--- a/misoclib/com/uart/frontend/wishbone.py
+++ /dev/null
@@ -1,9 +0,0 @@
-from migen.fhdl.std import *
-
-from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
-from misoclib.com.uart.phy.serial import UARTPHYSerial
-
-class UARTWishboneBridge(LiteScopeWishboneBridge):
-    def __init__(self, pads, clk_freq, baudrate=115200):
-        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
-        LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq)

diff --git a/misoclib/com/uart/wishbone.py b/misoclib/com/uart/wishbone.py
new file mode 100644 (file)
index 0000000..fc0d292
--- /dev/null
+++ b/misoclib/com/uart/wishbone.py
@@ -0,0 +1,9 @@
+from migen.fhdl.std import *
+
+from misoclib.tools.wishbone import WishboneStreamingBridge
+from misoclib.com.uart.phy.serial import UARTPHYSerial
+
+class UARTWishboneBridge(WishboneStreamingBridge):
+    def __init__(self, pads, clk_freq, baudrate=115200):
+        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
+        WishboneStreamingBridge.__init__(self, self.phy, clk_freq)

diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py
index 8b28dfe36cf21c66c1b8968e3ad453686b47eb5b..ce7d53a102cb390d3fe19bdf6f9a4e330d13aa07 100644 (file)
--- a/misoclib/mem/litesata/example_designs/targets/bist.py
+++ b/misoclib/mem/litesata/example_designs/targets/bist.py
@@ -9,7 +9,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+from misoclib.com.uart.wishbone import UARTWishboneBridge
 
 from misoclib.mem.litesata.common import *
 from misoclib.mem.litesata.phy import LiteSATAPHY

diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index efbe3397aff467e4ddbfd02d36546bd69edcc468..26853f7e9b3f371e24524162e77af6ff4793fb2f 100644 (file)
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -7,7 +7,7 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm
 from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 
-from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+from misoclib.com.uart.wishbone import UARTWishboneBridge
 
 class LiteScopeSoC(SoC, AutoCSR):
     csr_map = {

diff --git a/misoclib/tools/litescope/frontend/wishbone.py b/misoclib/tools/litescope/frontend/wishbone.py
deleted file mode 100644 (file)
index e7e0066..0000000
--- a/misoclib/tools/litescope/frontend/wishbone.py
+++ /dev/null
@@ -1,149 +0,0 @@
-from misoclib.tools.litescope.common import *
-from migen.bus import wishbone
-from migen.genlib.misc import chooser
-from migen.genlib.record import Record
-from migen.flow.actor import Sink, Source
-
-from misoclib.com.uart.phy.serial import UARTPHYSerial
-
-class LiteScopeWishboneBridge(Module):
-    cmds = {
-        "write": 0x01,
-        "read": 0x02
-    }
-
-    def __init__(self, phy, clk_freq):
-        self.wishbone = wishbone.Interface()
-
-        # # #
-
-        byte_counter = Counter(3)
-        word_counter = Counter(8)
-        self.submodules += byte_counter, word_counter
-
-        cmd = Signal(8)
-        cmd_ce = Signal()
-
-        length = Signal(8)
-        length_ce = Signal()
-
-        address = Signal(32)
-        address_ce = Signal()
-
-        data = Signal(32)
-        rx_data_ce = Signal()
-        tx_data_ce = Signal()
-
-        self.sync += [
-            If(cmd_ce, cmd.eq(phy.source.data)),
-            If(length_ce, length.eq(phy.source.data)),
-            If(address_ce, address.eq(Cat(phy.source.data, address[0:24]))),
-            If(rx_data_ce,
-                data.eq(Cat(phy.source.data, data[0:24]))
-            ).Elif(tx_data_ce,
-                data.eq(self.wishbone.dat_r)
-            )
-        ]
-
-        fsm = InsertReset(FSM(reset_state="IDLE"))
-        timeout = Timeout(clk_freq//10)
-        self.submodules += fsm, timeout
-        self.comb += [
-            timeout.ce.eq(1),
-            fsm.reset.eq(timeout.reached),
-            phy.source.ack.eq(1)
-        ]
-        fsm.act("IDLE",
-            timeout.reset.eq(1),
-            If(phy.source.stb,
-                cmd_ce.eq(1),
-                If((phy.source.data == self.cmds["write"]) |
-                   (phy.source.data == self.cmds["read"]),
-                    NextState("RECEIVE_LENGTH")
-                ),
-                byte_counter.reset.eq(1),
-                word_counter.reset.eq(1)
-            )
-        )
-        fsm.act("RECEIVE_LENGTH",
-            If(phy.source.stb,
-                length_ce.eq(1),
-                NextState("RECEIVE_ADDRESS")
-            )
-        )
-        fsm.act("RECEIVE_ADDRESS",
-            If(phy.source.stb,
-                address_ce.eq(1),
-                byte_counter.ce.eq(1),
-                If(byte_counter.value == 3,
-                    If(cmd == self.cmds["write"],
-                        NextState("RECEIVE_DATA")
-                    ).Elif(cmd == self.cmds["read"],
-                        NextState("READ_DATA")
-                    ),
-                    byte_counter.reset.eq(1),
-                )
-            )
-        )
-        fsm.act("RECEIVE_DATA",
-            If(phy.source.stb,
-                rx_data_ce.eq(1),
-                byte_counter.ce.eq(1),
-                If(byte_counter.value == 3,
-                    NextState("WRITE_DATA"),
-                    byte_counter.reset.eq(1)
-                )
-            )
-        )
-        self.comb += [
-            self.wishbone.adr.eq(address + word_counter.value),
-            self.wishbone.dat_w.eq(data),
-            self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
-        ]
-        fsm.act("WRITE_DATA",
-            self.wishbone.stb.eq(1),
-            self.wishbone.we.eq(1),
-            self.wishbone.cyc.eq(1),
-            If(self.wishbone.ack,
-                word_counter.ce.eq(1),
-                If(word_counter.value == (length-1),
-                    NextState("IDLE")
-                ).Else(
-                    NextState("RECEIVE_DATA")
-                )
-            )
-        )
-        fsm.act("READ_DATA",
-            self.wishbone.stb.eq(1),
-            self.wishbone.we.eq(0),
-            self.wishbone.cyc.eq(1),
-            If(self.wishbone.ack,
-                tx_data_ce.eq(1),
-                NextState("SEND_DATA")
-            )
-        )
-        self.comb += \
-            chooser(data, byte_counter.value, phy.sink.data, n=4, reverse=True)
-        fsm.act("SEND_DATA",
-            phy.sink.stb.eq(1),
-            If(phy.sink.ack,
-                byte_counter.ce.eq(1),
-                If(byte_counter.value == 3,
-                    word_counter.ce.eq(1),
-                    If(word_counter.value == (length-1),
-                        NextState("IDLE")
-                    ).Else(
-                        NextState("READ_DATA"),
-                        byte_counter.reset.eq(1)
-                    )
-                )
-            )
-        )
-
-        if phy.sink.description.packetized:
-            self.comb += [
-                phy.sink.sop.eq((byte_counter.value == 0) & (word_counter.value == 0)),
-                phy.sink.eop.eq((byte_counter.value == 3) & (word_counter.value == (length-1)))
-            ]
-            if hasattr(phy.sink, "length"):
-                self.comb += phy.sink.length.eq(4*length)

diff --git a/misoclib/tools/wishbone.py b/misoclib/tools/wishbone.py
new file mode 100644 (file)
index 0000000..50ab287
--- /dev/null
+++ b/misoclib/tools/wishbone.py
@@ -0,0 +1,149 @@
+from migen.fhdl.std import *
+from migen.bus import wishbone
+from migen.genlib.misc import chooser, Counter, Timeout
+from migen.genlib.record import Record
+from migen.genlib.fsm import FSM, NextState
+from migen.flow.actor import Sink, Source
+
+
+class WishboneStreamingBridge(Module):
+    cmds = {
+        "write": 0x01,
+        "read": 0x02
+    }
+
+    def __init__(self, phy, clk_freq):
+        self.wishbone = wishbone.Interface()
+
+        # # #
+
+        byte_counter = Counter(3)
+        word_counter = Counter(8)
+        self.submodules += byte_counter, word_counter
+
+        cmd = Signal(8)
+        cmd_ce = Signal()
+
+        length = Signal(8)
+        length_ce = Signal()
+
+        address = Signal(32)
+        address_ce = Signal()
+
+        data = Signal(32)
+        rx_data_ce = Signal()
+        tx_data_ce = Signal()
+
+        self.sync += [
+            If(cmd_ce, cmd.eq(phy.source.data)),
+            If(length_ce, length.eq(phy.source.data)),
+            If(address_ce, address.eq(Cat(phy.source.data, address[0:24]))),
+            If(rx_data_ce,
+                data.eq(Cat(phy.source.data, data[0:24]))
+            ).Elif(tx_data_ce,
+                data.eq(self.wishbone.dat_r)
+            )
+        ]
+
+        fsm = InsertReset(FSM(reset_state="IDLE"))
+        timeout = Timeout(clk_freq//10)
+        self.submodules += fsm, timeout
+        self.comb += [
+            timeout.ce.eq(1),
+            fsm.reset.eq(timeout.reached),
+            phy.source.ack.eq(1)
+        ]
+        fsm.act("IDLE",
+            timeout.reset.eq(1),
+            If(phy.source.stb,
+                cmd_ce.eq(1),
+                If((phy.source.data == self.cmds["write"]) |
+                   (phy.source.data == self.cmds["read"]),
+                    NextState("RECEIVE_LENGTH")
+                ),
+                byte_counter.reset.eq(1),
+                word_counter.reset.eq(1)
+            )
+        )
+        fsm.act("RECEIVE_LENGTH",
+            If(phy.source.stb,
+                length_ce.eq(1),
+                NextState("RECEIVE_ADDRESS")
+            )
+        )
+        fsm.act("RECEIVE_ADDRESS",
+            If(phy.source.stb,
+                address_ce.eq(1),
+                byte_counter.ce.eq(1),
+                If(byte_counter.value == 3,
+                    If(cmd == self.cmds["write"],
+                        NextState("RECEIVE_DATA")
+                    ).Elif(cmd == self.cmds["read"],
+                        NextState("READ_DATA")
+                    ),
+                    byte_counter.reset.eq(1),
+                )
+            )
+        )
+        fsm.act("RECEIVE_DATA",
+            If(phy.source.stb,
+                rx_data_ce.eq(1),
+                byte_counter.ce.eq(1),
+                If(byte_counter.value == 3,
+                    NextState("WRITE_DATA"),
+                    byte_counter.reset.eq(1)
+                )
+            )
+        )
+        self.comb += [
+            self.wishbone.adr.eq(address + word_counter.value),
+            self.wishbone.dat_w.eq(data),
+            self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
+        ]
+        fsm.act("WRITE_DATA",
+            self.wishbone.stb.eq(1),
+            self.wishbone.we.eq(1),
+            self.wishbone.cyc.eq(1),
+            If(self.wishbone.ack,
+                word_counter.ce.eq(1),
+                If(word_counter.value == (length-1),
+                    NextState("IDLE")
+                ).Else(
+                    NextState("RECEIVE_DATA")
+                )
+            )
+        )
+        fsm.act("READ_DATA",
+            self.wishbone.stb.eq(1),
+            self.wishbone.we.eq(0),
+            self.wishbone.cyc.eq(1),
+            If(self.wishbone.ack,
+                tx_data_ce.eq(1),
+                NextState("SEND_DATA")
+            )
+        )
+        self.comb += \
+            chooser(data, byte_counter.value, phy.sink.data, n=4, reverse=True)
+        fsm.act("SEND_DATA",
+            phy.sink.stb.eq(1),
+            If(phy.sink.ack,
+                byte_counter.ce.eq(1),
+                If(byte_counter.value == 3,
+                    word_counter.ce.eq(1),
+                    If(word_counter.value == (length-1),
+                        NextState("IDLE")
+                    ).Else(
+                        NextState("READ_DATA"),
+                        byte_counter.reset.eq(1)
+                    )
+                )
+            )
+        )
+
+        if phy.sink.description.packetized:
+            self.comb += [
+                phy.sink.sop.eq((byte_counter.value == 0) & (word_counter.value == 0)),
+                phy.sink.eop.eq((byte_counter.value == 3) & (word_counter.value == (length-1)))
+            ]
+            if hasattr(phy.sink, "length"):
+                self.comb += phy.sink.length.eq(4*length)