2012-02-25 Walter Lee <walt@tilera.com>
+ * config.bfd (tilegx-*-*): rename little endian vector; add big
+ endian vector.
+ (tilegxbe-*-*): New case.
+ * configure.in (bfd_elf32_tilegx_vec): Rename...
+ (bfd_elf32_tilegx_le_vec): ... to this.
+ (bfd_elf32_tilegx_be_vec): New vector.
+ (bfd_elf64_tilegx_vec): Rename...
+ (bfd_elf64_tilegx_le_vec): ... to this.
+ (bfd_elf64_tilegx_be_vec): New vector.
+ * configure: Regenerate.
+ * elf32-tilegx.c (TARGET_LITTLE_SYM): Rename.
+ (TARGET_LITTLE_NAME): Ditto.
+ (TARGET_BIG_SYM): Define.
+ (TARGET_BIG_NAME): Define.
+ * elf64-tilegx.c (TARGET_LITTLE_SYM): Rename.
+ (TARGET_LITTLE_NAME): Ditto.
+ (TARGET_BIG_SYM): Define.
+ (TARGET_BIG_NAME): Define.
+ * targets.c (bfd_elf32_tilegx_vec): Rename...
+ (bfd_elf32_tilegx_le_vec): ... to this.
+ (bfd_elf32_tilegx_be_vec): Declare.
+ (bfd_elf64_tilegx_vec): Rename...
+ (bfd_elf64_tilegx_le_vec): ... to this.
+ (bfd_elf64_tilegx_be_vec): Declare.
+ (_bfd_target_vector): Add / rename above vectors.
* arctures.c (bfd_architecture): Define bfd_mach_tilegx32.
* bfd-in2.h: Regenerate.
* cpu-tilegx.c (bfd_tilegx32_arch): define.
- (bfd_tilegx_arch): link to bfd_tilegx32_arch.
+ (bfd_tilegx_arch): link to bfd_tilegx32_arch.
2012-02-24 Nick Clifton <nickc@redhat.com>
#ifdef BFD64
tilegx-*-*)
- targ_defvec=bfd_elf64_tilegx_vec
- targ_selvecs=bfd_elf32_tilegx_vec
+ targ_defvec=bfd_elf64_tilegx_le_vec
+ targ_selvecs="bfd_elf64_tilegx_be_vec bfd_elf32_tilegx_be_vec bfd_elf32_tilegx_le_vec"
+ ;;
+ tilegxbe-*-*)
+ targ_defvec=bfd_elf64_tilegx_be_vec
+ targ_selvecs="bfd_elf64_tilegx_le_vec bfd_elf32_tilegx_be_vec bfd_elf32_tilegx_le_vec"
;;
#endif
bfd_elf32_tic6x_linux_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tic6x_elf_be_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tic6x_elf_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
- bfd_elf32_tilegx_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
+ bfd_elf32_tilegx_be_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
+ bfd_elf32_tilegx_le_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
bfd_elf32_tilepro_vec) tb="$tb elf32-tilepro.lo elf32.lo $elf" ;;
bfd_elf32_tradbigmips_vec | bfd_elf32_tradbigmips_freebsd_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf64_sparc_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sparc_freebsd_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sparc_sol2_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
- bfd_elf64_tilegx_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
+ bfd_elf64_tilegx_be_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
+ bfd_elf64_tilegx_le_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
bfd_elf64_tradbigmips_vec | bfd_elf64_tradbigmips_freebsd_vec)
tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_tradlittlemips_vec | bfd_elf64_tradlittlemips_freebsd_vec)
bfd_elf32_tic6x_linux_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tic6x_elf_be_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tic6x_elf_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
- bfd_elf32_tilegx_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
+ bfd_elf32_tilegx_be_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
+ bfd_elf32_tilegx_le_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
bfd_elf32_tilepro_vec) tb="$tb elf32-tilepro.lo elf32.lo $elf" ;;
bfd_elf32_tradbigmips_vec | bfd_elf32_tradbigmips_freebsd_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf64_sparc_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sparc_freebsd_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sparc_sol2_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
- bfd_elf64_tilegx_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
+ bfd_elf64_tilegx_be_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
+ bfd_elf64_tilegx_le_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
bfd_elf64_tradbigmips_vec | bfd_elf64_tradbigmips_freebsd_vec)
tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_tradlittlemips_vec | bfd_elf64_tradlittlemips_freebsd_vec)
#define ELF_MAXPAGESIZE 0x10000
#define ELF_COMMONPAGESIZE 0x10000
-#define TARGET_LITTLE_SYM bfd_elf32_tilegx_vec
-#define TARGET_LITTLE_NAME "elf32-tilegx"
+#define TARGET_BIG_SYM bfd_elf32_tilegx_be_vec
+#define TARGET_BIG_NAME "elf32-tilegx-be"
+#define TARGET_LITTLE_SYM bfd_elf32_tilegx_le_vec
+#define TARGET_LITTLE_NAME "elf32-tilegx-le"
#define elf_backend_reloc_type_class tilegx_reloc_type_class
#define ELF_MAXPAGESIZE 0x10000
#define ELF_COMMONPAGESIZE 0x10000
-#define TARGET_LITTLE_SYM bfd_elf64_tilegx_vec
-#define TARGET_LITTLE_NAME "elf64-tilegx"
+
+#define TARGET_BIG_SYM bfd_elf64_tilegx_be_vec
+#define TARGET_BIG_NAME "elf64-tilegx-be"
+#define TARGET_LITTLE_SYM bfd_elf64_tilegx_le_vec
+#define TARGET_LITTLE_NAME "elf64-tilegx-le"
#define elf_backend_reloc_type_class tilegx_reloc_type_class
extern const bfd_target bfd_elf32_tic6x_elf_le_vec;
extern const bfd_target bfd_elf32_tic6x_linux_be_vec;
extern const bfd_target bfd_elf32_tic6x_linux_le_vec;
-extern const bfd_target bfd_elf32_tilegx_vec;
+extern const bfd_target bfd_elf32_tilegx_be_vec;
+extern const bfd_target bfd_elf32_tilegx_le_vec;
extern const bfd_target bfd_elf32_tilepro_vec;
extern const bfd_target bfd_elf32_tradbigmips_vec;
extern const bfd_target bfd_elf32_tradlittlemips_vec;
extern const bfd_target bfd_elf64_sparc_vec;
extern const bfd_target bfd_elf64_sparc_freebsd_vec;
extern const bfd_target bfd_elf64_sparc_sol2_vec;
-extern const bfd_target bfd_elf64_tilegx_vec;
+extern const bfd_target bfd_elf64_tilegx_be_vec;
+extern const bfd_target bfd_elf64_tilegx_le_vec;
extern const bfd_target bfd_elf64_tradbigmips_vec;
extern const bfd_target bfd_elf64_tradlittlemips_vec;
extern const bfd_target bfd_elf64_tradbigmips_freebsd_vec;
&bfd_elf32_spu_vec,
&bfd_elf32_tic6x_be_vec,
&bfd_elf32_tic6x_le_vec,
- &bfd_elf32_tilegx_vec,
+ &bfd_elf32_tilegx_be_vec,
+ &bfd_elf32_tilegx_le_vec,
&bfd_elf32_tilepro_vec,
&bfd_elf32_tradbigmips_vec,
&bfd_elf32_tradlittlemips_vec,
&bfd_elf64_sparc_vec,
&bfd_elf64_sparc_freebsd_vec,
&bfd_elf64_sparc_sol2_vec,
- &bfd_elf64_tilegx_vec,
+ &bfd_elf64_tilegx_be_vec,
+ &bfd_elf64_tilegx_le_vec,
&bfd_elf64_tradbigmips_vec,
&bfd_elf64_tradlittlemips_vec,
&bfd_elf64_tradbigmips_freebsd_vec,
+2012-02-25 Walter Lee <walt@tilera.com>
+
+ * binutils-all/objdump.exp (cpus_expected): Add tilegx.
+
2012-02-14 Alan Modra <amodra@gmail.com>
* binutils-all/dlltool.exp: Add setup_xfail.
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp ns32k pj powerpc pyramid
lappend cpus_expected romp rs6000 s390 sh sparc
-lappend cpus_expected tahoe tic54x tic80 tms320c30 tms320c4x tms320c54x v850
-lappend cpus_expected vax we32k x86-64 xscale xtensa z8k z8001 z8002
+lappend cpus_expected tahoe tic54x tic80 tilegx tms320c30 tms320c4x tms320c54x
+lappend cpus_expected v850 vax we32k x86-64 xscale xtensa z8k z8001 z8002
# Make sure the target CPU shows up in the list.
lappend cpus_expected ${target_cpu}
2012-02-25 Walter Lee <walt@tilera.com>
- * tc-tilegx.c (md_begin): set architecture and machine.
+ * tc-tilegx.c (md_begin): Set architecture and machine.
+ (tilegx_target_format): Handle big endian.
+ (OPTION_EB): Define.
+ (OPTION_EL): Define.
+ (md_longopts): Add entries for "EB" and "EL".
+ (md_parse_option): Handle OPTION_EB and OPTION_EL.
+ (md_show_usage): Add -EB and -EL.
+ (md_number_to_chars): New.
+ * tc-tilegx.h (TARGET_BYTES_BIG_ENDIAN): Guard definition with
+ ifndef.
+ (md_number_to_chars): Delete.
+ * configure.tgt (tilegx*be): Handle.
+ * doc/as.texinfo [TILE-Gx]: Document -EB and -EL.
+ * doc/c-tilegx.texi: Ditto.
2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
const char *
tilegx_target_format (void)
{
- return tilegx_arch_size == 64 ? "elf64-tilegx" : "elf32-tilegx";
+ if (target_big_endian) {
+ return tilegx_arch_size == 64 ? "elf64-tilegx-be" : "elf32-tilegx-be";
+ } else {
+ return tilegx_arch_size == 64 ? "elf64-tilegx-le" : "elf32-tilegx-le";
+ }
}
#define OPTION_32 (OPTION_MD_BASE + 0)
#define OPTION_64 (OPTION_MD_BASE + 1)
+#define OPTION_EB (OPTION_MD_BASE + 2)
+#define OPTION_EL (OPTION_MD_BASE + 3)
const char *md_shortopts = "VQ:";
{
{"32", no_argument, NULL, OPTION_32},
{"64", no_argument, NULL, OPTION_64},
+ {"EB", no_argument, NULL, OPTION_EB },
+ {"EL", no_argument, NULL, OPTION_EL },
{NULL, no_argument, NULL, 0}
};
tilegx_arch_size = 64;
break;
+ case OPTION_EB:
+ target_big_endian = 1;
+ break;
+
+ case OPTION_EL:
+ target_big_endian = 0;
+ break;
+
default:
return 0;
}
fprintf (stream, _("\
-Q ignored\n\
-V print assembler version number\n\
+ -EB/-EL generate big-endian/little-endian code\n\
--32/--64 generate 32bit/64bit code\n"));
}
/* Equal to MAX_PRECISION in atof-ieee.c */
#define MAX_LITTLENUMS 6
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+ if (target_big_endian)
+ number_to_chars_bigendian (buf, val, n);
+ else
+ number_to_chars_littleendian (buf, val, n);
+}
+
/* Turn the string pointed to by litP into a floating point constant
of type TYPE, and emit the appropriate bytes. The number of
LITTLENUMS emitted is stored in *SIZEP. An error message is
#define TC_TILEGX
+#ifndef TARGET_BYTES_BIG_ENDIAN
#define TARGET_BYTES_BIG_ENDIAN 0
+#endif
#define WORKING_DOT_WORD
#define DWARF2_LINE_MIN_INSN_LENGTH 8
-#define md_number_to_chars number_to_chars_littleendian
-
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
#define HANDLE_ALIGN(fragp) tilegx_handle_align (fragp)
sparclet*) cpu_type=sparc arch=sparclet ;;
sparclite*) cpu_type=sparc arch=sparclite ;;
sparc*) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
+ tilegx*be) cpu_type=tilegx endian=big ;;
+ tilegx*) cpu_type=tilegx endian=little ;;
v850*) cpu_type=v850 ;;
x86_64*) cpu_type=i386 arch=x86_64;;
xtensa*) cpu_type=xtensa arch=xtensa ;;
tic54x-*-* | c54x*-*-*) fmt=coff bfd_gas=yes need_libm=yes;;
tic6x-*-*) fmt=elf ;;
- tilepro-*-* | tilegx-*-*) fmt=elf ;;
+ tilepro-*-* | tilegx*-*-*) fmt=elf ;;
v850*-*-*) fmt=elf ;;
@ifset TILEGX
@emph{Target TILE-Gx options:}
- [@b{-m32}|@b{-m64}]
+ [@b{-m32}|@b{-m64}][@b{-EB}][@b{-EL}]
@end ifset
@ifset TILEPRO
@c TILEPro has no machine-dependent assembler options
@item -m32 | -m64
Select the word size, either 32 bits or 64 bits.
+@cindex @samp{-EB} option, TILE-Gx
+@cindex @samp{-EL} option, TILE-Gx
+@item -EB | -EL
+Select the endianness, either big-endian (-EB) or little-endian (-EL).
+
@end table
@c man end
+2012-02-25 Walter Lee <walt@tilera.com>
+
+ * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx_be.c.
+ (ALL_64_EMULATION_SOURCES): Add eelf64tilegx_be.c.
+ (eelf32tilegx_be.c): Add rule to build this file.
+ (eelf64tilegx_be.c): Ditto.
+ * Makefile.in: Regenerate.
+ * configure.tgt (tilegx-*-*): Support big endian.
+ (tilegxbe-*-*): New.
+ * emulparams/elf32tilegx.sh (OUTPUT_FORMAT): Rename.
+ (BIG_OUTPUT_FORMAT): Define.
+ (LITTLE_OUTPUT_FORMAT): Define.
+ * emulparams/elf32tilegx_be.sh: New.
+ * emulparams/elf64tilegx.sh (OUTPUT_FORMAT): Rename.
+ (BIG_OUTPUT_FORMAT): Define.
+ (LITTLE_OUTPUT_FORMAT): Define.
+ * emulparams/elf64tilegx_be.sh: New.
+
2012-02-24 Kai Tietz <ktietz@redhat.com>
PR binutils/13710
eelf32rl78.c \
eelf32rx.c \
eelf32tilegx.c \
+ eelf32tilegx_be.c \
eelf32tilepro.c \
eelf32vax.c \
eelf32xc16x.c \
eelf64ppc.c \
eelf64ppc_fbsd.c \
eelf64tilegx.c \
+ eelf64tilegx_be.c \
eelf_l1om.c \
eelf_l1om_fbsd.c \
eelf_k1om.c \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32tilegx "$(tdir_tilegx)"
+eelf32tilegx_be.c: $(srcdir)/emulparams/elf32tilegx_be.sh \
+ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32tilegx_be "$(tdir_tilegx_be)"
eelf32tilepro.c: $(srcdir)/emulparams/elf32tilepro.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64tilegx "$(tdir_tilegx)"
+eelf64tilegx_be.c: $(srcdir)/emulparams/elf64tilegx_be.sh \
+ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf64tilegx_be "$(tdir_tilegx_be)"
eelf_l1om.c: $(srcdir)/emulparams/elf_l1om.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf_l1om "$(tdir_elf_l1om)"
eelf32rl78.c \
eelf32rx.c \
eelf32tilegx.c \
+ eelf32tilegx_be.c \
eelf32tilepro.c \
eelf32vax.c \
eelf32xc16x.c \
eelf64ppc.c \
eelf64ppc_fbsd.c \
eelf64tilegx.c \
+ eelf64tilegx_be.c \
eelf_l1om.c \
eelf_l1om_fbsd.c \
eelf_k1om.c \
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rl78.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilegx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilegx_be.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilepro.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ppc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ppc_fbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64tilegx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64tilegx_be.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf_i386.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf_i386_be.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf_i386_chaos.Po@am__quote@
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32tilegx "$(tdir_tilegx)"
+eelf32tilegx_be.c: $(srcdir)/emulparams/elf32tilegx_be.sh \
+ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32tilegx_be "$(tdir_tilegx_be)"
eelf32tilepro.c: $(srcdir)/emulparams/elf32tilepro.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64tilegx "$(tdir_tilegx)"
+eelf64tilegx_be.c: $(srcdir)/emulparams/elf64tilegx_be.sh \
+ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf64tilegx_be "$(tdir_tilegx_be)"
eelf_l1om.c: $(srcdir)/emulparams/elf_l1om.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf_l1om "$(tdir_elf_l1om)"
tic80-*-*) targ_emul=tic80coff
;;
tilegx-*-*) targ_emul=elf64tilegx
- targ_extra_emuls="elf32tilegx"
+ targ_extra_emuls="elf64tilegx_be elf32tilegx elf32tilegx_be"
+ targ_extra_libpath=$targ_extra_emuls ;;
+tilegxbe-*-*) targ_emul=elf64tilegx_be
+ targ_extra_emuls="elf64tilegx elf32tilegx elf32tilegx_be"
targ_extra_libpath=$targ_extra_emuls ;;
tilepro-*-*) targ_emul=elf32tilepro ;;
v850*-*-*) targ_emul=v850
SCRIPT_NAME=elf
-OUTPUT_FORMAT="elf32-tilegx"
+OUTPUT_FORMAT="elf32-tilegx-le"
+BIG_OUTPUT_FORMAT="elf32-tilegx-be"
+LITTLE_OUTPUT_FORMAT="elf32-tilegx-le"
TEXT_START_ADDR=0x10000
NO_REL_RELOCS=yes
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
--- /dev/null
+. ${srcdir}/emulparams/elf32tilegx.sh
+OUTPUT_FORMAT="elf32-tilegx-be"
SCRIPT_NAME=elf
-OUTPUT_FORMAT="elf64-tilegx"
+OUTPUT_FORMAT="elf64-tilegx-le"
+BIG_OUTPUT_FORMAT="elf64-tilegx-be"
+LITTLE_OUTPUT_FORMAT="elf64-tilegx-le"
TEXT_START_ADDR=0x10000
NO_REL_RELOCS=yes
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
--- /dev/null
+. ${srcdir}/emulparams/elf64tilegx.sh
+OUTPUT_FORMAT="elf64-tilegx-be"
+2012-02-25 Walter Lee <walt@tilera.com>
+
+ * ld-tilegx/reloc-be.d: New.
+ * ld-tilegx/reloc-le.d: New.
+ * ld-tilegx/reloc.d: Delete.
+ * ld-tilegx/tilegx.exp: Test big and little endian.
+
2012-02-22 Nick Clifton <nickc@redhat.com>
PR ld/13683
--- /dev/null
+
+.*: file format .*tilegx.*
+
+Contents of section .text:
+ 100b0 .*
+ 100c0 .*
+ 100d0 .*
+ 100e0 .*
+ 100f0 .*
+ 10100 .*
+ 10110 .*
+ 10120 .*
+ 10130 .*
+ 10140 .*
+ 10150 .*
+ 10160 .*
+ 10170 .*
+ 10180 .*
+ 10190 .*
+ 101a0 .*
+ 101b0 .*
+ 101c0 .*
+Contents of section .data:
+ 201e0 000101b8 000101c0 827a4b64 11770000 .*
+ 201f0 0032002e 2c827a12 34567812 3456789a .*
+ 20200 bc123456 789abcde f0000000 00000000 .*
+ 20210 00000000 00000000 00000000 00000000 .*
+
+Disassembly of section .text:
+
+00000000000100b0 <_start>:
+ 100b0: [0-9a-f]* { add r2, zero, zero }
+ 100b8: [0-9a-f]* { j 101b8 <external1> }
+ 100c0: [0-9a-f]* { add r3, r2, r2 }
+ 100c8: [0-9a-f]* { beqzt zero, 101c0 <external2> }
+ 100d0: [0-9a-f]* { movei r2, 17 ; movei r3, 119 }
+ 100d8: [0-9a-f]* { movei r2, 17 ; movei r3, 119 ; ld zero, zero }
+ 100e0: [0-9a-f]* { mtspr 17, zero }
+ 100e8: [0-9a-f]* { mfspr zero, 17 }
+ 100f0: [0-9a-f]* { moveli r2, -32134 ; moveli r3, 19300 }
+ 100f8: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -30293 }
+ 10100: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -12816 }
+ 10108: [0-9a-f]* { moveli r2, 4660 ; moveli r3, 30292 }
+ 10110: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, 12816 }
+ 10118: [0-9a-f]* { shl16insli r2, r2, -25924 ; shl16insli r3, r3, -292 }
+ 10120: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -292 }
+ 10128: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -17768 }
+ 10130: [0-9a-f]* { shl16insli r2, r2, -25924 ; shl16insli r3, r3, 30292 }
+ 10138: [0-9a-f]* { shl16insli r2, r2, -8464 ; shl16insli r3, r3, 12816 }
+ 10140: [0-9a-f]* { ld_add r0, r0, 17 }
+ 10148: [0-9a-f]* { st_add r0, r0, 17 }
+ 10150: [0-9a-f]* { mm r2, r3, 19, 31 }
+ 10158: [0-9a-f]* { shli r2, r3, 19 ; shli r4, r5, 31 }
+ 10160: [0-9a-f]* { shli r2, r3, 19 ; shli r4, r5, 31 ; ld zero, zero }
+ 10168: [0-9a-f]* { moveli r0, 80 ; moveli r1, 80 }
+ 10170: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
+ 10178: [0-9a-f]* { moveli r0, 168 ; moveli r1, 168 }
+ 10180: [0-9a-f]* { moveli r0, 4096 ; moveli r1, 4096 }
+ 10188: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
+ 10190: [0-9a-f]* { moveli r0, 144 ; moveli r1, 144 }
+ 10198: [0-9a-f]* { moveli r0, 4096 ; moveli r1, 4096 }
+ 101a0: [0-9a-f]* { moveli r0, 0 ; moveli r1, 0 }
+ 101a8: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
+ 101b0: [0-9a-f]* { moveli r0, 112 ; moveli r1, 112 }
+
+00000000000101b8 <external1>:
+ 101b8: [0-9a-f]* { j 101b8 <external1> }
+
+00000000000101c0 <external2>:
+ 101c0: [0-9a-f]* { j 101b8 <external1> }
--- /dev/null
+
+.*: file format .*tilegx.*
+
+Contents of section .text:
+ 100b0 .*
+ 100c0 .*
+ 100d0 .*
+ 100e0 .*
+ 100f0 .*
+ 10100 .*
+ 10110 .*
+ 10120 .*
+ 10130 .*
+ 10140 .*
+ 10150 .*
+ 10160 .*
+ 10170 .*
+ 10180 .*
+ 10190 .*
+ 101a0 .*
+ 101b0 .*
+ 101c0 .*
+Contents of section .data:
+ 201e0 b8010100 c0010100 7a82644b 11773200 .*
+ 201f0 00002e00 2c7a8234 12785634 127856bc .*
+ 20200 9a341278 56bc9af0 de000000 00000000 .*
+ 20210 00000000 00000000 00000000 00000000 .*
+
+Disassembly of section .text:
+
+00000000000100b0 <_start>:
+ 100b0: [0-9a-f]* { add r2, zero, zero }
+ 100b8: [0-9a-f]* { j 101b8 <external1> }
+ 100c0: [0-9a-f]* { add r3, r2, r2 }
+ 100c8: [0-9a-f]* { beqzt zero, 101c0 <external2> }
+ 100d0: [0-9a-f]* { movei r2, 17 ; movei r3, 119 }
+ 100d8: [0-9a-f]* { movei r2, 17 ; movei r3, 119 ; ld zero, zero }
+ 100e0: [0-9a-f]* { mtspr 17, zero }
+ 100e8: [0-9a-f]* { mfspr zero, 17 }
+ 100f0: [0-9a-f]* { moveli r2, -32134 ; moveli r3, 19300 }
+ 100f8: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -30293 }
+ 10100: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -12816 }
+ 10108: [0-9a-f]* { moveli r2, 4660 ; moveli r3, 30292 }
+ 10110: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, 12816 }
+ 10118: [0-9a-f]* { shl16insli r2, r2, -25924 ; shl16insli r3, r3, -292 }
+ 10120: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -292 }
+ 10128: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -17768 }
+ 10130: [0-9a-f]* { shl16insli r2, r2, -25924 ; shl16insli r3, r3, 30292 }
+ 10138: [0-9a-f]* { shl16insli r2, r2, -8464 ; shl16insli r3, r3, 12816 }
+ 10140: [0-9a-f]* { ld_add r0, r0, 17 }
+ 10148: [0-9a-f]* { st_add r0, r0, 17 }
+ 10150: [0-9a-f]* { mm r2, r3, 19, 31 }
+ 10158: [0-9a-f]* { shli r2, r3, 19 ; shli r4, r5, 31 }
+ 10160: [0-9a-f]* { shli r2, r3, 19 ; shli r4, r5, 31 ; ld zero, zero }
+ 10168: [0-9a-f]* { moveli r0, 80 ; moveli r1, 80 }
+ 10170: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
+ 10178: [0-9a-f]* { moveli r0, 168 ; moveli r1, 168 }
+ 10180: [0-9a-f]* { moveli r0, 4096 ; moveli r1, 4096 }
+ 10188: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
+ 10190: [0-9a-f]* { moveli r0, 144 ; moveli r1, 144 }
+ 10198: [0-9a-f]* { moveli r0, 4096 ; moveli r1, 4096 }
+ 101a0: [0-9a-f]* { moveli r0, 0 ; moveli r1, 0 }
+ 101a8: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
+ 101b0: [0-9a-f]* { moveli r0, 112 ; moveli r1, 112 }
+
+00000000000101b8 <external1>:
+ 101b8: [0-9a-f]* { j 101b8 <external1> }
+
+00000000000101c0 <external2>:
+ 101c0: [0-9a-f]* { j 101b8 <external1> }
+++ /dev/null
-
-.*: file format elf64-tilegx.*
-
-Contents of section .text:
- 100b0 .*
- 100c0 .*
- 100d0 .*
- 100e0 .*
- 100f0 .*
- 10100 .*
- 10110 .*
- 10120 .*
- 10130 .*
- 10140 .*
- 10150 .*
- 10160 .*
- 10170 .*
- 10180 .*
- 10190 .*
- 101a0 .*
- 101b0 .*
- 101c0 .*
-Contents of section .data:
- 201e0 b8010100 c0010100 7a82644b 11773200 .*
- 201f0 00002e00 2c7a8234 12785634 127856bc .*
- 20200 9a341278 56bc9af0 de000000 00000000 .*
- 20210 00000000 00000000 00000000 00000000 .*
-
-Disassembly of section .text:
-
-00000000000100b0 <_start>:
- 100b0: [0-9a-f]* { add r2, zero, zero }
- 100b8: [0-9a-f]* { j 101b8 <external1> }
- 100c0: [0-9a-f]* { add r3, r2, r2 }
- 100c8: [0-9a-f]* { beqzt zero, 101c0 <external2> }
- 100d0: [0-9a-f]* { movei r2, 17 ; movei r3, 119 }
- 100d8: [0-9a-f]* { movei r2, 17 ; movei r3, 119 ; ld zero, zero }
- 100e0: [0-9a-f]* { mtspr 17, zero }
- 100e8: [0-9a-f]* { mfspr zero, 17 }
- 100f0: [0-9a-f]* { moveli r2, -32134 ; moveli r3, 19300 }
- 100f8: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -30293 }
- 10100: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -12816 }
- 10108: [0-9a-f]* { moveli r2, 4660 ; moveli r3, 30292 }
- 10110: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, 12816 }
- 10118: [0-9a-f]* { shl16insli r2, r2, -25924 ; shl16insli r3, r3, -292 }
- 10120: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -292 }
- 10128: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -17768 }
- 10130: [0-9a-f]* { shl16insli r2, r2, -25924 ; shl16insli r3, r3, 30292 }
- 10138: [0-9a-f]* { shl16insli r2, r2, -8464 ; shl16insli r3, r3, 12816 }
- 10140: [0-9a-f]* { ld_add r0, r0, 17 }
- 10148: [0-9a-f]* { st_add r0, r0, 17 }
- 10150: [0-9a-f]* { mm r2, r3, 19, 31 }
- 10158: [0-9a-f]* { shli r2, r3, 19 ; shli r4, r5, 31 }
- 10160: [0-9a-f]* { shli r2, r3, 19 ; shli r4, r5, 31 ; ld zero, zero }
- 10168: [0-9a-f]* { moveli r0, 80 ; moveli r1, 80 }
- 10170: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
- 10178: [0-9a-f]* { moveli r0, 168 ; moveli r1, 168 }
- 10180: [0-9a-f]* { moveli r0, 4096 ; moveli r1, 4096 }
- 10188: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
- 10190: [0-9a-f]* { moveli r0, 144 ; moveli r1, 144 }
- 10198: [0-9a-f]* { moveli r0, 4096 ; moveli r1, 4096 }
- 101a0: [0-9a-f]* { moveli r0, 0 ; moveli r1, 0 }
- 101a8: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
- 101b0: [0-9a-f]* { moveli r0, 112 ; moveli r1, 112 }
-
-00000000000101b8 <external1>:
- 101b8: [0-9a-f]* { j 101b8 <external1> }
-
-00000000000101c0 <external2>:
- 101c0: [0-9a-f]* { j 101b8 <external1> }
# Set up a list as described in ld-lib.exp
-set tilepro_tests {
- { "tilegx relocation resolution linker test"
- ""
- ""
+set tilegx_tests {
+ { "tilegx little-endian relocation resolution linker test"
+ "-EL"
+ "-EL"
{ "reloc.s" "external.s" }
- { {objdump -ds reloc.d} }
+ { {objdump -ds reloc-le.d} }
+ "reloc"
+ }
+ { "tilegx big-endian relocation resolution linker test"
+ "-EB"
+ "-EB"
+ { "reloc.s" "external.s" }
+ { {objdump -ds reloc-be.d} }
"reloc"
}
}
-run_ld_link_tests $tilepro_tests
+run_ld_link_tests $tilegx_tests
projects / binutils-gdb.git / commitdiff