serv: connect reset.

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index 4cda01d80bff24a5ee8e742b16c842a244ff970d..c919fb5326449e1c830de778f4aabd55a3142db0 100644 (file)
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -44,7 +44,7 @@ class SERV(CPU):
         self.cpu_params = dict(
             # clock / reset
             i_clk   = ClockSignal(),
-            i_i_rst = ResetSignal(),
+            i_i_rst = ResetSignal() | self.reset,
 
             # timer irq
             i_i_timer_irq = 0,