whoops, REMAP inverted

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index a73085cf6ea8cc648f6c24b674a0499bf2542e11..1ee2b51aa52a2807067565162cfa67b91e3ae1b4 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1240,6 +1240,8 @@ class ISACaller:
         # after that, settle down (combinatorial) to let Vector reg numbers
         # work themselves out
         yield Settle()
+        remap_active = yield self.dec2.remap_active
+        print ("remap active", remap_active)
 
         # main input registers (RT, RA ...)
         inputs = []

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 274cf228a8f89e0b1f61c193d4fb70bc5effc7a6..7df9ab5223285531b0979dafef487f3ebcdefba1 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1285,9 +1285,9 @@ class PowerDecode2(PowerDecodeSubset):
                     selectstep = dststep if out else srcstep
                     step = Signal(7, name="step_%s" % rname.lower())
                     with m.If(self.remap_active):
-                        comb += step.eq(selectstep)
-                    with m.Else():
                         comb += step.eq(remapstep)
+                    with m.Else():
+                        comb += step.eq(selectstep)
                     # reverse gear goes the opposite way
                     with m.If(self.rm_dec.reverse_gear):
                         comb += to_reg.data.eq(offs+svdec.reg_out+(vl-1-step))