code-comments on madded and divmod2du should say RS=RT+MAXVL now

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index b4a39fab4de3427a1fc913c7705a97a6d0b394c7..7dfd4c551a82962f53446b678ac58d7b95970cbd 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -7,7 +7,7 @@ VA-Form
 Pseudo-code:
 
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- EXTZ(RC) + prod
@@ -27,7 +27,7 @@ VA-Form
 Pseudo-code:
 
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
         dividend[0:(XLEN*2)-1] <- (RC) || (RA)