remove unused imports

diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py
index ae631c84c93bf70956cbcbd007bbc81ac000c83b..4ce94ce7618b826ff0641c73bee187a4f2f1aa95 100644 (file)
--- a/src/nmigen_gf/hdl/cldivrem.py
+++ b/src/nmigen_gf/hdl/cldivrem.py
@@ -10,7 +10,7 @@ https://bugs.libre-soc.org/show_bug.cgi?id=784
 """
 
 from nmigen.hdl.ir import Elaboratable
-from nmigen.hdl.ast import Signal, Cat
+from nmigen.hdl.ast import Signal
 from nmigen.hdl.dsl import Module
 
 

diff --git a/src/nmigen_gf/hdl/test/test_cldivrem.py b/src/nmigen_gf/hdl/test/test_cldivrem.py
index 5929f678d12e5501dd72be67e7dec3ee97f3aac5..b6e4cfb7b19d023fccc02e14a1e03dca28655e08 100644 (file)
--- a/src/nmigen_gf/hdl/test/test_cldivrem.py
+++ b/src/nmigen_gf/hdl/test/test_cldivrem.py
@@ -5,7 +5,7 @@
 # of Horizon 2020 EU Programme 957073.
 
 import unittest
-from nmigen.hdl.ast import (AnyConst, Assert, Signal, Const, unsigned, Cat)
+from nmigen.hdl.ast import AnyConst, Assert, Signal, Const, unsigned
 from nmigen.hdl.dsl import Module
 from nmutil.formaltest import FHDLTestCase
 from nmigen_gf.hdl.cldivrem import (equal_leading_zero_count_reference,