#include "nouveau/nouveau_resource.h"
#include "nouveau/nouveau_pushbuf.h"
+#define NOUVEAU_CAP_HW_VTXBUF (0xbeef0000)
+#define NOUVEAU_CAP_HW_IDXBUF (0xbeef0001)
+
+#define NOUVEAU_BUFFER_USAGE_TEXTURE (1 << 16)
+
struct nouveau_winsys {
struct nouveau_context *nv;
return 0;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 12;
+ case NOUVEAU_CAP_HW_VTXBUF:
+ case NOUVEAU_CAP_HW_IDXBUF:
+ return 0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0;
return 10;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 13;
+ case NOUVEAU_CAP_HW_VTXBUF:
+ case NOUVEAU_CAP_HW_IDXBUF:
+ return 0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0;
nv40_miptree_layout(mt);
- mt->buffer = ws->buffer_create(ws, 256, PIPE_BUFFER_USAGE_PIXEL,
+ mt->buffer = ws->buffer_create(ws, 256,
+ PIPE_BUFFER_USAGE_PIXEL |
+ NOUVEAU_BUFFER_USAGE_TEXTURE,
mt->total_size);
if (!mt->buffer) {
FREE(mt);
static int
nv40_screen_get_param(struct pipe_screen *pscreen, int param)
{
+ struct nv40_screen *screen = nv40_screen(pscreen);
+
switch (param) {
case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
return 16;
return 10;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 13;
+ case NOUVEAU_CAP_HW_VTXBUF:
+ return 1;
+ case NOUVEAU_CAP_HW_IDXBUF:
+ if (screen->curie->grclass == NV40TCL)
+ return 1;
+ return 0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0;
return 10;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 13;
+ case NOUVEAU_CAP_HW_VTXBUF:
+ case NOUVEAU_CAP_HW_IDXBUF:
+ return 0;
default:
NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
return 0;
#include "state_tracker/st_context.h"
#include "pipe/p_defines.h"
#include "pipe/p_context.h"
+#include "pipe/p_screen.h"
#include "nouveau_context.h"
#include "nouveau_dri.h"
/* G80 */
break;
default:
- NOUVEAU_ERR("Unsupported chipset: NV%02x\n", nv->chipset);
+ NOUVEAU_ERR("Unsupported chipset: NV%02x\n", (int)nv->chipset);
return GL_FALSE;
}
}
if (!getenv("NOUVEAU_FORCE_SOFTPIPE")) {
+ struct pipe_screen *pscreen;
+
pipe = nouveau_pipe_create(nv);
if (!pipe)
NOUVEAU_ERR("Couldn't create hw pipe\n");
+ pscreen = nvc->pscreen;
+
+ nv->cap.hw_vertex_buffer =
+ pscreen->get_param(pscreen, NOUVEAU_CAP_HW_VTXBUF);
+ nv->cap.hw_index_buffer =
+ pscreen->get_param(pscreen, NOUVEAU_CAP_HW_IDXBUF);
}
if (!pipe) {
struct nouveau_screen *nv_screen;
struct pipe_surface *frontbuffer;
+ struct {
+ int hw_vertex_buffer;
+ int hw_index_buffer;
+ } cap;
+
/* Hardware context */
struct nouveau_channel_context *nvc;
int pctx_id;
if (nvpb->base.remaining == nvpb->size)
return 0;
+ nouveau_fence_flush(chan);
+
nvpb->size -= nvpb->base.remaining;
nvchan->dma->cur += nvpb->size;
nvchan->dma->free -= nvpb->size;
unsigned usage, unsigned size)
{
struct nouveau_pipe_winsys *nvpws = (struct nouveau_pipe_winsys *)pws;
- struct nouveau_device *dev = nvpws->nv->nv_screen->device;
+ struct nouveau_context *nv = nvpws->nv;
+ struct nouveau_device *dev = nv->nv_screen->device;
struct nouveau_pipe_buffer *nvbuf;
- uint32_t flags = 0;
+ uint32_t flags;
nvbuf = calloc(1, sizeof(*nvbuf));
if (!nvbuf)
nvbuf->base.size = size;
flags = NOUVEAU_BO_LOCAL;
+
+ if (usage & PIPE_BUFFER_USAGE_PIXEL) {
+ if (usage & NOUVEAU_BUFFER_USAGE_TEXTURE)
+ flags |= NOUVEAU_BO_GART;
+ flags |= NOUVEAU_BO_VRAM;
+ }
+
+ if (usage & PIPE_BUFFER_USAGE_VERTEX) {
+ if (nv->cap.hw_vertex_buffer)
+ flags |= NOUVEAU_BO_GART;
+ }
+
+ if (usage & PIPE_BUFFER_USAGE_INDEX) {
+ if (nv->cap.hw_index_buffer)
+ flags |= NOUVEAU_BO_GART;
+ }
+
if (nouveau_bo_new(dev, flags, alignment, size, &nvbuf->bo)) {
free(nvbuf);
return NULL;