intel_bo_unreference(hw3d->kernel.bo);
hw3d->kernel.bo = intel_winsys_alloc_buffer(hw3d->cp->winsys,
- "kernel bo", new_size, INTEL_DOMAIN_CPU);
+ "kernel bo", new_size, true);
if (!hw3d->kernel.bo) {
ilo_err("failed to allocate kernel bo\n");
return false;
p->invalidate_flags = ILO_3D_PIPELINE_INVALIDATE_ALL;
p->workaround_bo = intel_winsys_alloc_buffer(p->cp->winsys,
- "PIPE_CONTROL workaround", 4096, INTEL_DOMAIN_INSTRUCTION);
+ "PIPE_CONTROL workaround", 4096, false);
if (!p->workaround_bo) {
ilo_warn("failed to allocate PIPE_CONTROL workaround bo\n");
FREE(p);
ilo_cp_write(cp, dw0);
ilo_cp_write(cp, dw1);
ilo_cp_write(cp, height << 16 | width);
- ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
- INTEL_DOMAIN_RENDER);
+ ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
ilo_cp_write(cp, pattern);
ilo_cp_end(cp);
}
ilo_cp_write(cp, dw1);
ilo_cp_write(cp, y1 << 16 | x1);
ilo_cp_write(cp, y2 << 16 | x2);
- ilo_cp_write_bo(cp, dst_offset, dst_bo,
- INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+ ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
ilo_cp_write(cp, pattern);
ilo_cp_end(cp);
}
ilo_cp_write(cp, dw0);
ilo_cp_write(cp, dw1);
ilo_cp_write(cp, height << 16 | width);
- ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
- INTEL_DOMAIN_RENDER);
+ ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
ilo_cp_write(cp, src_pitch);
- ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
+ ilo_cp_write_bo(cp, src_offset, src_bo, 0);
ilo_cp_end(cp);
}
ilo_cp_write(cp, dw1);
ilo_cp_write(cp, y1 << 16 | x1);
ilo_cp_write(cp, y2 << 16 | x2);
- ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_DOMAIN_RENDER,
- INTEL_DOMAIN_RENDER);
+ ilo_cp_write_bo(cp, dst_offset, dst_bo, INTEL_RELOC_WRITE);
ilo_cp_write(cp, src_y << 16 | src_x);
ilo_cp_write(cp, src_pitch >> src_pitch_shift);
- ilo_cp_write_bo(cp, src_offset, src_bo, INTEL_DOMAIN_RENDER, 0);
+ ilo_cp_write_bo(cp, src_offset, src_bo, 0);
ilo_cp_end(cp);
}
* won't point at the same address, which is needed for jmpbuf
*/
bo = intel_winsys_alloc_buffer(cp->winsys,
- "batch buffer", cp->bo_size * 4, INTEL_DOMAIN_CPU);
+ "batch buffer", cp->bo_size * 4, true);
if (unlikely(!bo)) {
/* reuse the old one */
bo = cp->bo;
* bo to the buffer, it also emits a relocation.
*/
static inline void
-ilo_cp_write_bo(struct ilo_cp *cp, uint32_t val, struct intel_bo *bo,
- uint32_t read_domains, uint32_t write_domain)
+ilo_cp_write_bo(struct ilo_cp *cp, uint32_t val,
+ struct intel_bo *bo, uint32_t flags)
{
uint64_t presumed_offset;
if (bo) {
- intel_bo_add_reloc(cp->bo, cp->cmd_cur * 4, bo, val,
- read_domains, write_domain, &presumed_offset);
+ intel_bo_add_reloc(cp->bo, cp->cmd_cur * 4, bo, val, flags,
+ &presumed_offset);
}
else {
presumed_offset = 0;
const uint8_t cmd_len = (store_qword) ? 5 : 4;
/* must use GGTT on GEN6 as in PIPE_CONTROL */
const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
- const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
- const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
ilo_cp_write(cp, 0);
- ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+ ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
ilo_cp_write(cp, (uint32_t) val);
if (store_qword)
const uint8_t cmd_len = 3;
/* must use GGTT on GEN6 as in PIPE_CONTROL */
const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
- const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
- const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
ilo_cp_write(cp, reg);
- ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+ ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
ilo_cp_end(cp);
}
{
const uint32_t cmd = ILO_GPE_MI(0x28);
const uint8_t cmd_len = 3;
- const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
- const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
- ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+ ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
ilo_cp_write(cp, report_id);
ilo_cp_end(cp);
}
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
- ilo_cp_write_bo(cp, 1, general_state_bo,
- INTEL_DOMAIN_RENDER,
- 0);
- ilo_cp_write_bo(cp, 1, surface_state_bo,
- INTEL_DOMAIN_SAMPLER,
- 0);
- ilo_cp_write_bo(cp, 1, dynamic_state_bo,
- INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION,
- 0);
- ilo_cp_write_bo(cp, 1, indirect_object_bo,
- 0,
- 0);
- ilo_cp_write_bo(cp, 1, instruction_bo,
- INTEL_DOMAIN_INSTRUCTION,
- 0);
+ ilo_cp_write_bo(cp, 1, general_state_bo, 0);
+ ilo_cp_write_bo(cp, 1, surface_state_bo, 0);
+ ilo_cp_write_bo(cp, 1, dynamic_state_bo, 0);
+ ilo_cp_write_bo(cp, 1, indirect_object_bo, 0);
+ ilo_cp_write_bo(cp, 1, instruction_bo, 0);
if (general_state_size) {
- ilo_cp_write_bo(cp, general_state_size | 1, general_state_bo,
- INTEL_DOMAIN_RENDER,
- 0);
+ ilo_cp_write_bo(cp, general_state_size | 1, general_state_bo, 0);
}
else {
/* skip range check */
}
if (dynamic_state_size) {
- ilo_cp_write_bo(cp, dynamic_state_size | 1, dynamic_state_bo,
- INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION,
- 0);
+ ilo_cp_write_bo(cp, dynamic_state_size | 1, dynamic_state_bo, 0);
}
else {
/* skip range check */
}
if (indirect_object_size) {
- ilo_cp_write_bo(cp, indirect_object_size | 1, indirect_object_bo,
- 0,
- 0);
+ ilo_cp_write_bo(cp, indirect_object_size | 1, indirect_object_bo, 0);
}
else {
/* skip range check */
}
if (instruction_size) {
- ilo_cp_write_bo(cp, instruction_size | 1, instruction_bo,
- INTEL_DOMAIN_INSTRUCTION,
- 0);
+ ilo_cp_write_bo(cp, instruction_size | 1, instruction_bo, 0);
}
else {
/* skip range check */
dw |= cso->stride << GEN6_VB_STATE_DW0_PITCH__SHIFT;
ilo_cp_write(cp, dw);
- ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
- ilo_cp_write_bo(cp, end_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
+ ilo_cp_write_bo(cp, start_offset, buf->bo, 0);
+ ilo_cp_write_bo(cp, end_offset, buf->bo, 0);
ilo_cp_write(cp, instance_divisor);
}
else {
ilo_cp_write(cp, cmd | (cmd_len - 2) |
((enable_cut_index) ? GEN6_IB_DW0_CUT_INDEX_ENABLE : 0) |
format);
- ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
- ilo_cp_write_bo(cp, end_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0);
+ ilo_cp_write_bo(cp, start_offset, buf->bo, 0);
+ ilo_cp_write_bo(cp, end_offset, buf->bo, 0);
ilo_cp_end(cp);
}
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
ilo_cp_write(cp, zs->payload[0]);
- ilo_cp_write_bo(cp, zs->payload[1], zs->bo,
- INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+ ilo_cp_write_bo(cp, zs->payload[1], zs->bo, INTEL_RELOC_WRITE);
ilo_cp_write(cp, zs->payload[2]);
ilo_cp_write(cp, zs->payload[3]);
ilo_cp_write(cp, zs->payload[4]);
ilo_cp_write(cp, cmd | (cmd_len - 2));
/* see ilo_gpe_init_zs_surface() */
ilo_cp_write(cp, zs->payload[6]);
- ilo_cp_write_bo(cp, zs->payload[7], zs->separate_s8_bo,
- INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+ ilo_cp_write_bo(cp, zs->payload[7], zs->separate_s8_bo, INTEL_RELOC_WRITE);
ilo_cp_end(cp);
}
ilo_cp_write(cp, cmd | (cmd_len - 2));
/* see ilo_gpe_init_zs_surface() */
ilo_cp_write(cp, zs->payload[8]);
- ilo_cp_write_bo(cp, zs->payload[9], zs->hiz_bo,
- INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+ ilo_cp_write_bo(cp, zs->payload[9], zs->hiz_bo, INTEL_RELOC_WRITE);
ilo_cp_end(cp);
}
{
const uint32_t cmd = ILO_GPE_CMD(0x3, 0x2, 0x00);
const uint8_t cmd_len = (write_qword) ? 5 : 4;
- const uint32_t read_domains = INTEL_DOMAIN_INSTRUCTION;
- const uint32_t write_domain = INTEL_DOMAIN_INSTRUCTION;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
ilo_cp_begin(cp, cmd_len);
ilo_cp_write(cp, cmd | (cmd_len - 2));
ilo_cp_write(cp, dw1);
- ilo_cp_write_bo(cp, bo_offset, bo, read_domains, write_domain);
+ ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
ilo_cp_write(cp, 0);
if (write_qword)
ilo_cp_write(cp, 0);
const int state_align = 32 / 4;
const int state_len = (dev->gen >= ILO_GEN(7)) ? 8 : 6;
uint32_t state_offset;
- uint32_t read_domains, write_domain;
ILO_GPE_VALID_GEN(dev, 6, 7.5);
- if (for_render) {
- read_domains = INTEL_DOMAIN_RENDER;
- write_domain = INTEL_DOMAIN_RENDER;
- }
- else {
- read_domains = INTEL_DOMAIN_SAMPLER;
- write_domain = 0;
- }
-
ilo_cp_steal(cp, "SURFACE_STATE", state_len, state_align, &state_offset);
STATIC_ASSERT(Elements(surf->payload) >= 8);
ilo_cp_write(cp, surf->payload[0]);
- ilo_cp_write_bo(cp, surf->payload[1],
- surf->bo, read_domains, write_domain);
+ ilo_cp_write_bo(cp, surf->payload[1], surf->bo,
+ (for_render) ? INTEL_RELOC_WRITE : 0);
ilo_cp_write(cp, surf->payload[2]);
ilo_cp_write(cp, surf->payload[3]);
ilo_cp_write(cp, surf->payload[4]);
ilo_cp_write(cp, cmd | (cmd_len - 2));
ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT |
stride);
- ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
- ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER);
+ ilo_cp_write_bo(cp, base, buf->bo, INTEL_RELOC_WRITE);
+ ilo_cp_write_bo(cp, end, buf->bo, INTEL_RELOC_WRITE);
ilo_cp_end(cp);
}
intel_bo_unreference(q->bo);
q->bo = intel_winsys_alloc_buffer(winsys,
- name, size, INTEL_DOMAIN_INSTRUCTION);
+ name, size, false);
q->reg_total = (q->bo) ? reg_total : 0;
}
return name;
}
-static enum intel_domain_flag
-resource_get_bo_initial_domain(const struct pipe_resource *templ)
+static bool
+resource_get_cpu_init(const struct pipe_resource *templ)
{
return (templ->bind & (PIPE_BIND_DEPTH_STENCIL |
PIPE_BIND_RENDER_TARGET |
- PIPE_BIND_STREAM_OUTPUT)) ?
- INTEL_DOMAIN_RENDER : 0;
+ PIPE_BIND_STREAM_OUTPUT)) ? false : true;
}
static void
{
struct ilo_screen *is = ilo_screen(tex->base.screen);
const char *name = resource_get_bo_name(&tex->base);
- const enum intel_domain_flag initial_domain =
- resource_get_bo_initial_domain(&tex->base);
+ const bool cpu_init = resource_get_cpu_init(&tex->base);
tex->bo = intel_winsys_alloc_bo(is->winsys, name, tex->layout.tiling,
- tex->layout.bo_stride, tex->layout.bo_height, initial_domain);
+ tex->layout.bo_stride, tex->layout.bo_height, cpu_init);
return (tex->bo != NULL);
}
tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "hiz texture",
INTEL_TILING_Y, tex->layout.aux_stride, tex->layout.aux_height,
- INTEL_DOMAIN_RENDER);
+ false);
if (!tex->aux_bo)
return false;
tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "mcs texture",
INTEL_TILING_Y, tex->layout.aux_stride, tex->layout.aux_height,
- INTEL_DOMAIN_RENDER);
+ false);
if (!tex->aux_bo)
return false;
{
struct ilo_screen *is = ilo_screen(buf->base.screen);
const char *name = resource_get_bo_name(&buf->base);
- const enum intel_domain_flag initial_domain =
- resource_get_bo_initial_domain(&buf->base);
+ const bool cpu_init = resource_get_cpu_init(&buf->base);
buf->bo = intel_winsys_alloc_buffer(is->winsys, name,
- buf->bo_size, initial_domain);
+ buf->bo_size, cpu_init);
return (buf->bo != NULL);
}
/*
* No need to implicitly set up a fence register for each non-linear reloc
- * entry. When a fence register is needed for a reloc entry,
- * drm_intel_bo_emit_reloc_fence() will be called explicitly.
- *
- * intel_bo_add_reloc() currently lacks "bool fenced" for this to work.
- * But we never need a fence register on GEN4+ so we do not need to worry
- * about it yet.
+ * entry. INTEL_RELOC_FENCE will be set on reloc entries that need them.
*/
drm_intel_bufmgr_gem_enable_fenced_relocs(winsys->bufmgr);
enum intel_tiling_mode tiling,
unsigned long pitch,
unsigned long height,
- uint32_t initial_domain)
+ bool cpu_init)
{
- const bool for_render =
- (initial_domain & (INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION));
const unsigned int alignment = 4096; /* always page-aligned */
unsigned long size;
drm_intel_bo *bo;
size = pitch * height;
- if (for_render) {
- bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
- name, size, alignment);
+ if (cpu_init) {
+ bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
}
else {
- bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
+ bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
+ name, size, alignment);
}
if (bo && tiling != INTEL_TILING_NONE) {
int
intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
struct intel_bo *target_bo, uint32_t target_offset,
- uint32_t read_domains, uint32_t write_domain,
- uint64_t *presumed_offset)
+ uint32_t flags, uint64_t *presumed_offset)
{
+ uint32_t read_domains, write_domain;
int err;
- err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
- gem_bo(target_bo), target_offset,
- read_domains, write_domain);
+ if (flags & INTEL_RELOC_WRITE) {
+ /*
+ * Because of the translation to domains, INTEL_RELOC_GGTT should only
+ * be set on GEN6 when the bo is written by MI_* or PIPE_CONTROL. The
+ * kernel will translate it back to INTEL_RELOC_GGTT.
+ */
+ write_domain = (flags & INTEL_RELOC_GGTT) ?
+ I915_GEM_DOMAIN_INSTRUCTION : I915_GEM_DOMAIN_RENDER;
+ read_domains = write_domain;
+ } else {
+ write_domain = 0;
+ read_domains = I915_GEM_DOMAIN_RENDER |
+ I915_GEM_DOMAIN_SAMPLER |
+ I915_GEM_DOMAIN_INSTRUCTION |
+ I915_GEM_DOMAIN_VERTEX;
+ }
+
+ if (flags & INTEL_RELOC_FENCE) {
+ err = drm_intel_bo_emit_reloc_fence(gem_bo(bo), offset,
+ gem_bo(target_bo), target_offset,
+ read_domains, write_domain);
+ } else {
+ err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
+ gem_bo(target_bo), target_offset,
+ read_domains, write_domain);
+ }
*presumed_offset = gem_bo(target_bo)->offset64 + target_offset;
};
/* this is compatible with i915_drm.h's definitions */
-enum intel_domain_flag {
- INTEL_DOMAIN_CPU = 0x00000001,
- INTEL_DOMAIN_RENDER = 0x00000002,
- INTEL_DOMAIN_SAMPLER = 0x00000004,
- INTEL_DOMAIN_COMMAND = 0x00000008,
- INTEL_DOMAIN_INSTRUCTION = 0x00000010,
- INTEL_DOMAIN_VERTEX = 0x00000020,
- INTEL_DOMAIN_GTT = 0x00000040,
+enum intel_reloc_flag {
+ INTEL_RELOC_FENCE = 1 << 0,
+ INTEL_RELOC_GGTT = 1 << 1,
+ INTEL_RELOC_WRITE = 1 << 2,
};
/* this is compatible with i915_drm.h's definitions */
* \param tiling Tiling mode.
* \param pitch Pitch of the bo.
* \param height Height of the bo.
- * \param initial_domain Initial (write) domain.
+ * \param cpu_init Will be initialized by CPU.
*/
struct intel_bo *
intel_winsys_alloc_bo(struct intel_winsys *winsys,
enum intel_tiling_mode tiling,
unsigned long pitch,
unsigned long height,
- uint32_t initial_domain);
+ bool cpu_init);
/**
* Allocate a linear buffer object.
intel_winsys_alloc_buffer(struct intel_winsys *winsys,
const char *name,
unsigned long size,
- uint32_t initial_domain)
+ bool cpu_init)
{
return intel_winsys_alloc_bo(winsys, name,
- INTEL_TILING_NONE, size, 1, initial_domain);
+ INTEL_TILING_NONE, size, 1, cpu_init);
}
/**
int
intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
struct intel_bo *target_bo, uint32_t target_offset,
- uint32_t read_domains, uint32_t write_domain,
- uint64_t *presumed_offset);
+ uint32_t flags, uint64_t *presumed_offset);
/**
* Return the current number of relocations.
projects / mesa.git / commitdiff