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diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index dbb5286649e3c6855051c5062c510047b7dac6d1..62a39b198539945a4ba52cf058e5dca1a368c1b6 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -487,12 +487,12 @@ in SVP64 when LRu=1).
 ```
 if (mode_is_64bit) then M <- 0
 else M <- 32
+ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
 ctrdec = ¬BO[2]
 if CTRtest & (cond_ok ^ CTi) then
    ctrdec = 0b0
 if ctrdec then CTR <- CTR - 1
-ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
 lr_ok <- SVRMmode.LRu
 if ctr_ok & cond_ok then
   if AA then NIA <-iea EXTS(BD || 0b00)
@@ -523,27 +523,31 @@ for srcstep in range(VL):
       # inverted CTR test skip mode
       if ¬BO[2] & CTRtest & ¬CTI then
         CTR = CTR - 1
-        continue # skip to next
+        continue # skip to next element
     else
         testbit = SVRMmode.SNZ
-    if ¬BO[2] then CTR <- CTR - 1
-    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
     # actual element test here
-    el_cond_ok <- BO[0] | ¬(testbit ^ BO[1]) & ctr_ok
+    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])   
+    el_cond_ok <- BO[0] | ¬(testbit ^ BO[1])
+    # check if CTR dec should occur
+    ctrdec = ¬BO[2]
+    if CTRtest & (el_cond_ok ^ CTi) then
+       ctrdec = 0b0
+    if ctrdec then CTR <- CTR - 1
     # merge in the test
     if SVRMmode.ALL:
-        cond_ok &= el_cond_ok
+        cond_ok &= (el_cond_ok & ctr_ok)
     else
-        cond_ok |= el_cond_ok
+        cond_ok |= (el_cond_ok & ctr_ok)
     # test for VL to be set (and exit)
-    if VLSET and VSb = el_cond_ok then
+    if VLSET and VSb = (el_cond_ok & ctr_ok) then
         if SVRMmode.VLI
             SVSTATE.VL = srcstep+1
         else
             SVSTATE.VL = srcstep
         break
     # early exit?
-    if SVRMmode.ALL != el_cond_ok:
+    if SVRMmode.ALL != (el_cond_ok & ctr_ok):
          break
     # SVP64 rules about Scalar registers still apply!
     if SVCRf.scalar: