note that mv is possible using addi.

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index 545a705d00eb7bfeb0d499aeb592c6f23cd07836..a3ee7b227b169d8d7d9f2a22ac581277507b7a02 100644 (file)
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -115,8 +115,10 @@ Further Notes:
 * bc also has an immediate mode, listed below in Branch section
 * for LD/ST, offset is aligned.  8-byte: i2||imm||0b000 4-byte: 0b00
 * SV Prefix over-rides help provide alternative bitwidths for LD/ST
-* RB|0 if RB is zero, addi. becomes "li" (this only works if RT takes
-  part of opcode).
+* RB|0 if RB is zero, addi. becomes "li"
+ - this only works if RT takes part of opcode
+ - mv is also possible by specifying an immediate of zero
+
 
 ### Branch