intel/blorp: Refactor the HiZ op interface

This commit does a few things:

 1) Now that BLORP can do HiZ ops on gen8+, drop the gen6 prefix.
 2) Switch parameters to uint32_t to match the rest of blorp.
 3) Take a range of layers and loop internally.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index ea3b8252a2ad92d85556adfc857fa2de8666a122..fe5dccdeb5904f4713bfb8364205d53f64567cfa 100644 (file)
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -286,60 +286,66 @@ blorp_ensure_sf_program(struct blorp_context *blorp,
 }
 
 void
-blorp_gen6_hiz_op(struct blorp_batch *batch,
-                  struct blorp_surf *surf, unsigned level, unsigned layer,
-                  enum blorp_hiz_op op)
+blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
+             uint32_t level, uint32_t start_layer, uint32_t num_layers,
+             enum blorp_hiz_op op)
 {
    struct blorp_params params;
    blorp_params_init(&params);
 
    params.hiz_op = op;
 
-   brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level, layer,
-                               surf->surf->format, true);
-
-   /* Align the rectangle primitive to 8x4 pixels.
-    *
-    * During fast depth clears, the emitted rectangle primitive  must be
-    * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
-    * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
-    * PRM):
-    *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
-    *     aligned to an 8x4 pixel block relative to the upper left corner
-    *     of the depth buffer [...]
-    *
-    * For hiz resolves, the rectangle must also be 8x4 aligned. Item
-    * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
-    * Ivybridge simulator require the alignment.
-    *
-    * To be safe, let's just align the rect for all hiz operations and all
-    * hardware generations.
-    *
-    * However, for some miptree slices of a Z24 texture, emitting an 8x4
-    * aligned rectangle that covers the slice may clobber adjacent slices if
-    * we strictly adhered to the texture alignments specified in the PRM.  The
-    * Ivybridge PRM, Section "Alignment Unit Size", states that
-    * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
-    * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
-    * prevents the clobbering.
-    */
-   params.x1 = minify(params.depth.surf.logical_level0_px.width,
-                      params.depth.view.base_level);
-   params.y1 = minify(params.depth.surf.logical_level0_px.height,
-                      params.depth.view.base_level);
-   params.x1 = ALIGN(params.x1, 8);
-   params.y1 = ALIGN(params.y1, 4);
-
-   if (params.depth.view.base_level == 0) {
-      /* TODO: What about MSAA? */
-      params.depth.surf.logical_level0_px.width = params.x1;
-      params.depth.surf.logical_level0_px.height = params.y1;
+   for (uint32_t a = 0; a < num_layers; a++) {
+      const uint32_t layer = start_layer + a;
+
+      brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level,
+                                  layer, surf->surf->format, true);
+
+      /* Align the rectangle primitive to 8x4 pixels.
+       *
+       * During fast depth clears, the emitted rectangle primitive  must be
+       * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
+       * 11.5.3.1 Depth Buffer Clear (and the matching section in the
+       * Sandybridge PRM):
+       *
+       *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
+       *     aligned to an 8x4 pixel block relative to the upper left corner
+       *     of the depth buffer [...]
+       *
+       * For hiz resolves, the rectangle must also be 8x4 aligned. Item
+       * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
+       * Ivybridge simulator require the alignment.
+       *
+       * To be safe, let's just align the rect for all hiz operations and all
+       * hardware generations.
+       *
+       * However, for some miptree slices of a Z24 texture, emitting an 8x4
+       * aligned rectangle that covers the slice may clobber adjacent slices
+       * if we strictly adhered to the texture alignments specified in the
+       * PRM.  The Ivybridge PRM, Section "Alignment Unit Size", states that
+       * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
+       * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
+       * 8, which prevents the clobbering.
+       */
+      params.x1 = minify(params.depth.surf.logical_level0_px.width,
+                         params.depth.view.base_level);
+      params.y1 = minify(params.depth.surf.logical_level0_px.height,
+                         params.depth.view.base_level);
+      params.x1 = ALIGN(params.x1, 8);
+      params.y1 = ALIGN(params.y1, 4);
+
+      if (params.depth.view.base_level == 0) {
+         /* TODO: What about MSAA? */
+         params.depth.surf.logical_level0_px.width = params.x1;
+         params.depth.surf.logical_level0_px.height = params.y1;
+      }
+
+      params.dst.surf.samples = params.depth.surf.samples;
+      params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
+      params.depth_format =
+         isl_format_get_depth_format(surf->surf->format, false);
+      params.num_samples = params.depth.surf.samples;
+
+      batch->blorp->exec(batch, &params);
    }
-
-   params.dst.surf.samples = params.depth.surf.samples;
-   params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
-   params.depth_format = isl_format_get_depth_format(surf->surf->format, false);
-   params.num_samples = params.depth.surf.samples;
-
-   batch->blorp->exec(batch, &params);
 }

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index eab75d70ab97ddd34717a8d6df3a27fdce9715d1..744c1b1ea0a2fe2ab8a7fbf87080caab43c3b663 100644 (file)
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -209,9 +209,9 @@ enum blorp_hiz_op {
 };
 
 void
-blorp_gen6_hiz_op(struct blorp_batch *batch,
-                  struct blorp_surf *surf, unsigned level, unsigned layer,
-                  enum blorp_hiz_op op);
+blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
+             uint32_t level, uint32_t start_layer, uint32_t num_layers,
+             enum blorp_hiz_op op);
 
 #ifdef __cplusplus
 } /* end extern "C" */

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 3ba65d40c5296918c07f322ef474ed81c730eb7c..d94a2f89fa512009bfc9fa2e4cad1d51193b3d43 100644 (file)
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1723,6 +1723,6 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
 
    surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
 
-   blorp_gen6_hiz_op(&batch, &surf, 0, 0, op);
+   blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
    blorp_batch_finish(&batch);
 }

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 7fd67600f18ab917dc950d2e3ed0547adc1fc94e..834f43249a9551789a403cbdfae58853a15e12cd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1074,8 +1074,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 
       struct blorp_batch batch;
       blorp_batch_init(&brw->blorp, &batch, brw, 0);
-      for (unsigned a = 0; a < num_layers; a++)
-         blorp_gen6_hiz_op(&batch, &surf, level, start_layer + a, op);
+      blorp_hiz_op(&batch, &surf, level, start_layer, num_layers, op);
       blorp_batch_finish(&batch);
    }