---------- Begin Simulation Statistics ----------
-sim_seconds 1.897858 # Number of seconds simulated
-sim_ticks 1897857556000 # Number of ticks simulated
-final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.901720 # Number of seconds simulated
+sim_ticks 1901719660500 # Number of ticks simulated
+final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 54087 # Simulator instruction rate (inst/s)
-host_op_rate 54087 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1829896991 # Simulator tick rate (ticks/s)
-host_mem_usage 335972 # Number of bytes of host memory used
-host_seconds 1037.14 # Real time elapsed on the host
-sim_insts 56096024 # Number of instructions simulated
-sim_ops 56096024 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 762816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 217920 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 980736 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7805952 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7805952 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 11919 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 379138 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3405 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 14924 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 450802 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 121968 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 121968 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 401935 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12785381 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1396640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 503271 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15202051 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 401935 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 516760 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4113034 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4113034 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4113034 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 401935 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12785381 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1396640 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 503271 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19315085 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 450802 # Total number of read requests seen
-system.physmem.writeReqs 121968 # Total number of write requests seen
-system.physmem.cpureqs 580318 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28851328 # Total number of bytes read from memory
-system.physmem.bytesWritten 7805952 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28851328 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7805952 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 52 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3354 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28275 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28002 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28406 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 28112 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28525 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 28215 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27879 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27987 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28166 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28504 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 28315 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 28066 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 28252 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27814 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7745 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7549 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7514 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7914 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7617 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7558 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7984 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7855 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7634 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7769 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7378 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis
+host_inst_rate 128809 # Simulator instruction rate (inst/s)
+host_op_rate 128809 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4317556960 # Simulator tick rate (ticks/s)
+host_mem_usage 340604 # Number of bytes of host memory used
+host_seconds 440.46 # Real time elapsed on the host
+sim_insts 56735321 # Number of instructions simulated
+sim_ops 56735321 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24596992 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 118720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 533440 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28758656 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 118720 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7726912 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7726912 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 384328 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1855 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8335 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 449354 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120733 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120733 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 450960 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12934079 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1394477 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 62428 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 280504 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15122448 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 450960 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 62428 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 513388 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4063118 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4063118 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4063118 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 450960 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12934079 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1394477 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 62428 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 280504 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19185566 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 449354 # Total number of read requests seen
+system.physmem.writeReqs 120733 # Total number of write requests seen
+system.physmem.cpureqs 587676 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28758656 # Total number of bytes read from memory
+system.physmem.bytesWritten 7726912 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28758656 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7726912 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4987 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28470 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 27991 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28541 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 28079 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28255 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 28278 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27951 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27937 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28148 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28118 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28117 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 28100 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27877 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27868 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27749 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7940 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7547 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7751 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7437 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7736 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7593 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7293 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7361 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7614 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7612 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7616 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7622 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7539 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7418 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7408 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7246 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 525 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1897852967000 # Total gap between requests
+system.physmem.numWrRetry 393 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1901668058000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 450802 # Categorize read packet sizes
+system.physmem.readPktSize::6 449354 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 122493 # categorize write packet sizes
+system.physmem.writePktSize::6 121126 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 3354 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4987 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 322811 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66355 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 31450 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 6565 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2903 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2442 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1811 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2029 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1666 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1950 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1569 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1659 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1496 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 916 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 256 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 143 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 322670 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66093 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 30768 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 6525 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2881 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2394 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1668 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1927 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1563 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1537 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1779 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1228 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1454 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 894 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4091 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 5028 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 5125 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 5174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 5249 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5292 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5292 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5302 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1212 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 178 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4050 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4973 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 5082 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 5135 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5198 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5217 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 277 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 115 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 6654880960 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13976960960 # Sum of mem lat for all requests
-system.physmem.totBusLat 1803000000 # Total cycles spent in databus access
-system.physmem.totBankLat 5519080000 # Total cycles spent in bank access
-system.physmem.avgQLat 14764.02 # Average queueing delay per request
-system.physmem.avgBankLat 12244.22 # Average bank access latency per request
+system.physmem.totQLat 6361514382 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13649024382 # Sum of mem lat for all requests
+system.physmem.totBusLat 1797116000 # Total cycles spent in databus access
+system.physmem.totBankLat 5490394000 # Total cycles spent in bank access
+system.physmem.avgQLat 14159.39 # Average queueing delay per request
+system.physmem.avgBankLat 12220.46 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31008.23 # Average memory access latency
-system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 30379.84 # Average memory access latency
+system.physmem.avgRdBW 15.12 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 4.06 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 15.12 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 4.06 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 7.39 # Average write queue length over time
-system.physmem.readRowHits 429728 # Number of row buffer hits during reads
-system.physmem.writeRowHits 77127 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.34 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes
-system.physmem.avgGap 3313464.33 # Average gap between requests
-system.l2c.replacements 343886 # number of replacements
-system.l2c.tagsinuse 65330.449226 # Cycle average of tags in use
-system.l2c.total_refs 2612992 # Total number of references to valid blocks.
-system.l2c.sampled_refs 408910 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.390140 # Average number of references to valid blocks.
+system.physmem.avgWrQLen 13.85 # Average write queue length over time
+system.physmem.readRowHits 429052 # Number of row buffer hits during reads
+system.physmem.writeRowHits 77896 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.50 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 64.52 # Row buffer hit rate for writes
+system.physmem.avgGap 3335750.61 # Average gap between requests
+system.l2c.replacements 342488 # number of replacements
+system.l2c.tagsinuse 65273.985795 # Cycle average of tags in use
+system.l2c.total_refs 2579319 # Total number of references to valid blocks.
+system.l2c.sampled_refs 407454 # Sample count of references to valid blocks.
+system.l2c.avg_refs 6.330332 # Average number of references to valid blocks.
system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53692.952391 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4245.749457 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 5529.153379 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 1310.829137 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 551.764862 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.819289 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.064785 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.084368 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.020002 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.008419 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.996864 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 779502 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 594261 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 294591 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 226328 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1894682 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 840085 # number of Writeback hits
-system.l2c.Writeback_hits::total 840085 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 143 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 80 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 223 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 34 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 147131 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 42889 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 190020 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 779502 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 741392 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 294591 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 269217 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2084702 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 779502 # number of overall hits
-system.l2c.overall_hits::cpu0.data 741392 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 294591 # number of overall hits
-system.l2c.overall_hits::cpu1.data 269217 # number of overall hits
-system.l2c.overall_hits::total 2084702 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 11921 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 272257 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 3421 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 1751 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 289350 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 2525 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 517 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3042 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 47 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 90 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 137 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 107281 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 13452 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 120733 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 11921 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 379538 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 3421 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 15203 # number of demand (read+write) misses
-system.l2c.demand_misses::total 410083 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 11921 # number of overall misses
-system.l2c.overall_misses::cpu0.data 379538 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 3421 # number of overall misses
-system.l2c.overall_misses::cpu1.data 15203 # number of overall misses
-system.l2c.overall_misses::total 410083 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 712478500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 11719521500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 222220000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 113744499 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 12767964499 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 468000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 936000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 1404000 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 313000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 113500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 426500 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 7724029500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 1451007500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 9175037000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 712478500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 19443551000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 222220000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 1564751999 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 21943001499 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 712478500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 19443551000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 222220000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 1564751999 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 21943001499 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 791423 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 866518 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 298012 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 228079 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2184032 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 840085 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 840085 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 2668 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 597 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3265 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 119 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 200 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 254412 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 56341 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 310753 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 791423 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1120930 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 298012 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 284420 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2494785 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 791423 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1120930 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 298012 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 284420 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2494785 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015063 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.314197 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.011479 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.007677 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.132484 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946402 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.865997 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.931700 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.580247 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.756303 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.685000 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.421682 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.238760 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.388518 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015063 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.338592 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.011479 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.053453 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.164376 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015063 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.338592 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.011479 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.053453 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.164376 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 59766.672259 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 43045.804148 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64957.614733 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 64959.736722 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 44126.367717 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 185.346535 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1810.444874 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 461.538462 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6659.574468 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1261.111111 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 3113.138686 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71998.112434 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 107865.559025 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 75994.442282 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 59766.672259 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 51229.523789 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 64957.614733 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 102923.896534 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53508.683606 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 59766.672259 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 51229.523789 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 64957.614733 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 102923.896534 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53508.683606 # average overall miss latency
+system.l2c.occ_blocks::writebacks 53688.105683 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 5378.814643 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 5989.071273 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 150.579784 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 67.414412 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.819215 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.082074 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.091386 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.002298 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.996002 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 855139 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 732341 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 222061 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 70684 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1880225 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 820780 # number of Writeback hits
+system.l2c.Writeback_hits::total 820780 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 274 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 437 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 155166 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 26038 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 181204 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst 855139 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 887507 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 222061 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 96722 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2061429 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 855139 # number of overall hits
+system.l2c.overall_hits::cpu0.data 887507 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 222061 # number of overall hits
+system.l2c.overall_hits::cpu1.data 96722 # number of overall hits
+system.l2c.overall_hits::total 2061429 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 13402 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 273000 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 1871 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 879 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 2698 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 1127 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 3825 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 423 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 448 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 871 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 111862 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 7571 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 119433 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 13402 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 384862 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 1871 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 8450 # number of demand (read+write) misses
+system.l2c.demand_misses::total 408585 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst 13402 # number of overall misses
+system.l2c.overall_misses::cpu0.data 384862 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 1871 # number of overall misses
+system.l2c.overall_misses::cpu1.data 8450 # number of overall misses
+system.l2c.overall_misses::total 408585 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst 813261500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 11720735498 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 126107500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 66824498 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 12726928996 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 1011000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 4739996 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 5750996 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1139500 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 1253500 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 7926259499 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 948720500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 8874979999 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 813261500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 19646994997 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 126107500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 1015544998 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 21601908995 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 813261500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 19646994997 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 126107500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 1015544998 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 21601908995 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst 868541 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 1005341 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 223932 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 71563 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2169377 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 820780 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 820780 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 2861 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 1401 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 4262 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 471 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 945 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 267028 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 33609 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 300637 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst 868541 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 1272369 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 223932 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 105172 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2470014 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 868541 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 1272369 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 223932 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 105172 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2470014 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015430 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.271550 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.008355 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.012283 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.133288 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943027 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.804425 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.897466 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.898089 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945148 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.921693 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.418915 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.225267 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.397266 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015430 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.302477 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.008355 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.080345 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.165418 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015430 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.302477 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.008355 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.080345 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.165418 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 60682.099687 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 42933.097062 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 67401.122394 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76023.319681 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 44014.667013 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 374.722016 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4205.852706 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 1503.528366 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2693.853428 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 254.464286 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 1439.150402 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70857.480637 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 125309.800555 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74309.277997 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 60682.099687 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 51049.454082 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 67401.122394 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 120182.840000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52870.049060 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 60682.099687 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 51049.454082 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 67401.122394 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 120182.840000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52870.049060 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 80445 # number of writebacks
-system.l2c.writebacks::total 80445 # number of writebacks
+system.l2c.writebacks::writebacks 79213 # number of writebacks
+system.l2c.writebacks::total 79213 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst 11920 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 272257 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 3405 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 1750 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 289332 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 2525 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 517 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 3042 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 47 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 90 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 137 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 107281 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 13452 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 120733 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 11920 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 379538 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 3405 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 15202 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 410065 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 11920 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 379538 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 3405 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 15202 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 410065 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561911095 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8192955588 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 178565558 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 113324293 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 9046756534 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25301493 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5294512 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 30596005 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 516543 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 904088 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 1420631 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6410159669 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1283732505 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 7693892174 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 561911095 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 14603115257 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 178565558 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 1397056798 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 16740648708 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 561911095 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 14603115257 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 178565558 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 1397056798 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 16740648708 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 936053000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 455620500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 1391673500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1587348000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 874199500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 2461547500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2523401000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1329820000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 3853221000 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.314197 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007673 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.132476 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.946402 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865997 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.931700 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.580247 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.756303 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.685000 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421682 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.238760 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.388518 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.164369 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.164369 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.727048 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64756.738857 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 31267.735798 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10020.393267 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10240.835590 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10057.858317 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10990.276596 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.422222 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10369.569343 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59751.117803 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 95430.605486 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63726.505380 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu0.inst 13401 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 273000 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 1855 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 878 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 2698 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 1127 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 3825 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 423 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 448 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 871 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 111862 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 7571 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 119433 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 13401 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 384862 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 1855 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 8449 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 408567 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 13401 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 384862 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 1855 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 8449 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 408567 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 644081442 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8187744767 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 101989522 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 55676772 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 8989492503 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27208158 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11300121 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 38508279 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4442418 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4488947 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 8931365 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6555553694 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 854426889 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 7409980583 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 644081442 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 14743298461 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 101989522 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 910103661 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 16399473086 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 644081442 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 14743298461 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 101989522 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 910103661 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 16399473086 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363910000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28770000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 1392680000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2007132500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 609318500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 2616451000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3371042500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 638088500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 4009131000 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271550 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012269 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.133280 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943027 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.804425 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.897466 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.898089 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.945148 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.921693 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.418915 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.225267 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.397266 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.302477 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.080335 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.165411 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.302477 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.080335 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.165411 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29991.739073 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63413.179954 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 31091.094451 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10084.565604 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10026.726708 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10067.523922 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10502.170213 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10019.970982 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10254.150402 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58603.937834 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 112855.222428 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 62042.991326 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38308.012901 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 107717.322878 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40139.005563 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38308.012901 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 107717.322878 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40139.005563 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 41695 # number of replacements
-system.iocache.tagsinuse 0.486173 # Cycle average of tags in use
+system.iocache.replacements 41699 # number of replacements
+system.iocache.tagsinuse 0.510808 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 41715 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1705465376000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 0.486173 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.030386 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.030386 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide 172 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 172 # number of ReadReq misses
+system.iocache.warmup_cycle 1705448726000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 0.510808 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.031925 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.031925 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide 41724 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41724 # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide 41724 # number of overall misses
-system.iocache.overall_misses::total 41724 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 20816998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 20816998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 9540304806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 9540304806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 9561121804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 9561121804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 9561121804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 9561121804 # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide 172 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses
+system.iocache.demand_misses::total 41731 # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses
+system.iocache.overall_misses::total 41731 # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide 21606998 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 21606998 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 9515470806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 9515470806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 9537077804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 9537077804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 9537077804 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 9537077804 # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide 41724 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide 41724 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121029.058140 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 121029.058140 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229599.172266 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 229599.172266 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 229151.610680 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 229151.610680 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 192730 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120709.486034 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120709.486034 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229001.511504 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 229001.511504 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 228537.006158 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 228537.006158 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 228537.006158 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 228537.006158 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 190616 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 23021 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 22877 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.371921 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.332211 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 41523 # number of writebacks
-system.iocache.writebacks::total 41523 # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide 172 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks 41520 # number of writebacks
+system.iocache.writebacks::total 41520 # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide 41724 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 41724 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide 41724 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 41724 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11872000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11872000 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7377518046 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7377518046 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 7389390046 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7389390046 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 7389390046 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7389390046 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12298000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12298000 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7352694535 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7352694535 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 7364992535 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7364992535 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 7364992535 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7364992535 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69023.255814 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 69023.255814 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177549.048084 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 177549.048084 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68703.910615 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68703.910615 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176951.639753 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 176951.639753 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 7996955 # DTB read hits
-system.cpu0.dtb.read_misses 29938 # DTB read misses
-system.cpu0.dtb.read_acv 553 # DTB read access violations
-system.cpu0.dtb.read_accesses 624438 # DTB read accesses
-system.cpu0.dtb.write_hits 5309744 # DTB write hits
-system.cpu0.dtb.write_misses 7955 # DTB write misses
-system.cpu0.dtb.write_acv 319 # DTB write access violations
-system.cpu0.dtb.write_accesses 207916 # DTB write accesses
-system.cpu0.dtb.data_hits 13306699 # DTB hits
-system.cpu0.dtb.data_misses 37893 # DTB misses
-system.cpu0.dtb.data_acv 872 # DTB access violations
-system.cpu0.dtb.data_accesses 832354 # DTB accesses
-system.cpu0.itb.fetch_hits 944692 # ITB hits
-system.cpu0.itb.fetch_misses 28693 # ITB misses
-system.cpu0.itb.fetch_acv 988 # ITB acv
-system.cpu0.itb.fetch_accesses 973385 # ITB accesses
+system.cpu0.dtb.read_hits 8796431 # DTB read hits
+system.cpu0.dtb.read_misses 31428 # DTB read misses
+system.cpu0.dtb.read_acv 541 # DTB read access violations
+system.cpu0.dtb.read_accesses 625134 # DTB read accesses
+system.cpu0.dtb.write_hits 5759616 # DTB write hits
+system.cpu0.dtb.write_misses 8293 # DTB write misses
+system.cpu0.dtb.write_acv 340 # DTB write access violations
+system.cpu0.dtb.write_accesses 208056 # DTB write accesses
+system.cpu0.dtb.data_hits 14556047 # DTB hits
+system.cpu0.dtb.data_misses 39721 # DTB misses
+system.cpu0.dtb.data_acv 881 # DTB access violations
+system.cpu0.dtb.data_accesses 833190 # DTB accesses
+system.cpu0.itb.fetch_hits 984271 # ITB hits
+system.cpu0.itb.fetch_misses 30098 # ITB misses
+system.cpu0.itb.fetch_acv 957 # ITB acv
+system.cpu0.itb.fetch_accesses 1014369 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 92901317 # number of cpu cycles simulated
+system.cpu0.numCycles 101814962 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 11220993 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 9498823 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 301088 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 7731310 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 4807164 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 12372868 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 10433314 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 330387 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 8151024 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 5278103 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 696053 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 31347 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 22682478 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 57580156 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 11220993 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 5503217 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10836671 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1573403 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 32658351 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 28974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 198560 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 186652 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 190 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6976582 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 207142 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 67595352 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.851836 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.189286 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 784011 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 32544 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 6062114 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 11958171 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1721751 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 36639586 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 31996 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 197160 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 291451 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 250 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7650026 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 223701 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 75155119 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.846620 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.185016 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 56758681 83.97% 83.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 707820 1.05% 85.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1385949 2.05% 87.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 615643 0.91% 87.98% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2401218 3.55% 91.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 457628 0.68% 92.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 501258 0.74% 92.95% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 784291 1.16% 94.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3982864 5.89% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 63196948 84.09% 84.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 760434 1.01% 85.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1555219 2.07% 87.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 695943 0.93% 88.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2597980 3.46% 91.55% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 515321 0.69% 92.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 570202 0.76% 93.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 825200 1.10% 94.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4437872 5.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 67595352 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.120784 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.619799 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 23783356 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 32156359 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9819480 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 864593 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 971563 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 447466 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 32236 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 56434658 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 99123 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 971563 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 24717335 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 12372612 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 16597679 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9220139 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3716022 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 53261468 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6752 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 462341 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1402867 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 35633564 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 64862965 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 64519168 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 343797 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 31292257 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4341299 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1345733 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 201778 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 10181749 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 8375667 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5571987 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1008121 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 649590 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 47223004 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1661663 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 46145441 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 96356 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5312296 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 2839377 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1124463 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 67595352 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.682672 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.326673 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 75155119 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.121523 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.624936 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 26159678 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 36134055 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 10861438 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 929510 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1070437 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 506952 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 35177 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 62384726 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 105081 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1070437 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 27188236 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 14621537 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 18000496 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 10158555 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 4115856 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 58951339 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 6767 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 643786 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1455498 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 39478397 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 71801839 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 71417626 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 384213 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 34623741 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4854648 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1439423 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 209577 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 11309679 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 9204846 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6035425 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1140474 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 743155 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 52262338 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1790513 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 51072320 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 91453 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5903524 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 3097982 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 1211963 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 75155119 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.679559 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.328921 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 46917740 69.41% 69.41% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 9524699 14.09% 83.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4257234 6.30% 89.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2757377 4.08% 93.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2128651 3.15% 97.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1105682 1.64% 98.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 579516 0.86% 99.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 281591 0.42% 99.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 42862 0.06% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 52460165 69.80% 69.80% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10326519 13.74% 83.54% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4642920 6.18% 89.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3073584 4.09% 93.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2437230 3.24% 97.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1208862 1.61% 98.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 646282 0.86% 99.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 308169 0.41% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 51388 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 67595352 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 75155119 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 67879 11.08% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 286167 46.73% 57.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 258352 42.19% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 82854 12.32% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 1 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 311669 46.35% 58.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 277938 41.33% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 31627354 68.54% 68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 48263 0.10% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 14877 0.03% 68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 8323640 18.04% 86.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5371898 11.64% 98.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 753768 1.63% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 35204584 68.93% 68.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 56105 0.11% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9153958 17.92% 87.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5827340 11.41% 98.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 808994 1.58% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 46145441 # Type of FU issued
-system.cpu0.iq.rate 0.496715 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 612398 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 160102230 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 53968976 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 45199549 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 492757 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 238910 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 232575 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 46496253 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 257824 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 502915 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 51072320 # Type of FU issued
+system.cpu0.iq.rate 0.501619 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 672462 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 177512873 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 59702358 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 50032811 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 550800 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 266343 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 260046 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 51452584 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 288424 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 541788 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1032397 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 11166 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 416538 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1120800 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2789 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 12579 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 457772 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 13927 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 141497 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 147130 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 971563 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 8614462 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 715502 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 51740003 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 598208 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 8375667 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5571987 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1467274 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 578076 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 5429 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 11166 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 147373 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 320873 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 468246 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 45797277 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 8048095 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 348163 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1070437 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10393328 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 793846 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 57261563 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 642303 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 9204846 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6035425 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1577054 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 582295 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 5281 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 12579 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 164111 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 347239 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 511350 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 50686887 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8851053 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 385432 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 2855336 # number of nop insts executed
-system.cpu0.iew.exec_refs 13377753 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 7249094 # Number of branches executed
-system.cpu0.iew.exec_stores 5329658 # Number of stores executed
-system.cpu0.iew.exec_rate 0.492967 # Inst execution rate
-system.cpu0.iew.wb_sent 45516467 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 45432124 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 22555336 # num instructions producing a value
-system.cpu0.iew.wb_consumers 30242853 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3208712 # number of nop insts executed
+system.cpu0.iew.exec_refs 14632506 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 8068479 # Number of branches executed
+system.cpu0.iew.exec_stores 5781453 # Number of stores executed
+system.cpu0.iew.exec_rate 0.497833 # Inst execution rate
+system.cpu0.iew.wb_sent 50383937 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 50292857 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 25094352 # num instructions producing a value
+system.cpu0.iew.wb_consumers 33818001 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.489036 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.745807 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.493963 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.742041 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 5732411 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 537200 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 438547 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 66623789 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.689159 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.608194 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6371688 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 578550 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 477828 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 74084682 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.685601 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.604018 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 49353923 74.08% 74.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7278183 10.92% 85.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 3860099 5.79% 90.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2143933 3.22% 94.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1188584 1.78% 95.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 481737 0.72% 96.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 414393 0.62% 97.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 388678 0.58% 97.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1514259 2.27% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 55026515 74.28% 74.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7939418 10.72% 84.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4342581 5.86% 90.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2354466 3.18% 94.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1312338 1.77% 95.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 550007 0.74% 96.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 466229 0.63% 97.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 437204 0.59% 97.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1655924 2.24% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 66623789 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 45914377 # Number of instructions committed
-system.cpu0.commit.committedOps 45914377 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 74084682 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 50792559 # Number of instructions committed
+system.cpu0.commit.committedOps 50792559 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 12498719 # Number of memory references committed
-system.cpu0.commit.loads 7343270 # Number of loads committed
-system.cpu0.commit.membars 179286 # Number of memory barriers committed
-system.cpu0.commit.branches 6902899 # Number of branches committed
-system.cpu0.commit.fp_insts 230540 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 42546523 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 573621 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1514259 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 13661699 # Number of memory references committed
+system.cpu0.commit.loads 8084046 # Number of loads committed
+system.cpu0.commit.membars 197074 # Number of memory barriers committed
+system.cpu0.commit.branches 7671683 # Number of branches committed
+system.cpu0.commit.fp_insts 257823 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 47034170 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 648346 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1655924 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 116563585 # The number of ROB reads
-system.cpu0.rob.rob_writes 104266102 # The number of ROB writes
-system.cpu0.timesIdled 937015 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 25305965 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3702808960 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 43304295 # Number of Instructions Simulated
-system.cpu0.committedOps 43304295 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 43304295 # Number of Instructions Simulated
-system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads
-system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes
+system.cpu0.rob.rob_reads 129398549 # The number of ROB reads
+system.cpu0.rob.rob_writes 115399767 # The number of ROB writes
+system.cpu0.timesIdled 1054205 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 26659843 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3701617819 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 47867129 # Number of Instructions Simulated
+system.cpu0.committedOps 47867129 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 47867129 # Number of Instructions Simulated
+system.cpu0.cpi 2.127033 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.127033 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.470138 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.470138 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 66695316 # number of integer regfile reads
+system.cpu0.int_regfile_writes 36408183 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 127649 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 129302 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 1695809 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 808592 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 790851 # number of replacements
-system.cpu0.icache.tagsinuse 510.328171 # Cycle average of tags in use
-system.cpu0.icache.total_refs 6144778 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 791359 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 7.764843 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 20315369000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 510.328171 # Average occupied blocks per requestor
+system.cpu0.icache.replacements 867960 # number of replacements
+system.cpu0.icache.tagsinuse 510.328414 # Cycle average of tags in use
+system.cpu0.icache.total_refs 6737923 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 868472 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 7.758365 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 20312098000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 510.328414 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 6144778 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6144778 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 6144778 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6144778 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 6144778 # number of overall hits
-system.cpu0.icache.overall_hits::total 6144778 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 831804 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 831804 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 831804 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 831804 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 831804 # number of overall misses
-system.cpu0.icache.overall_misses::total 831804 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11563264492 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 11563264492 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 11563264492 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 11563264492 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 11563264492 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 11563264492 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 6976582 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 6976582 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 6976582 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 6976582 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 6976582 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 6976582 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119228 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.119228 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119228 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.119228 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119228 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.119228 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13901.429293 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13901.429293 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13901.429293 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13901.429293 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2068 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 1976 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.031008 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 988 # average number of cycles each access was blocked
+system.cpu0.icache.ReadReq_hits::cpu0.inst 6737923 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 6737923 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 6737923 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 6737923 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 6737923 # number of overall hits
+system.cpu0.icache.overall_hits::total 6737923 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 912101 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 912101 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 912101 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 912101 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 912101 # number of overall misses
+system.cpu0.icache.overall_misses::total 912101 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12723011493 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 12723011493 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 12723011493 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 12723011493 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 12723011493 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 12723011493 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 7650024 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 7650024 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 7650024 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 7650024 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 7650024 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 7650024 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119229 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.119229 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119229 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.119229 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119229 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.119229 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13949.125692 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13949.125692 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13949.125692 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13949.125692 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 3314 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.013889 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets 438 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40285 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 40285 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 40285 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 40285 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 40285 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 40285 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791519 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 791519 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 791519 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 791519 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 791519 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 791519 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9521125993 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 9521125993 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9521125993 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 9521125993 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9521125993 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 9521125993 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113454 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.113454 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.113454 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12028.929177 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43445 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 43445 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 43445 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 43445 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 43445 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 43445 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868656 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 868656 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 868656 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 868656 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 868656 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 868656 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10487782996 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 10487782996 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10487782996 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 10487782996 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10487782996 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 10487782996 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113549 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.113549 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.113549 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12073.574575 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1122816 # number of replacements
-system.cpu0.dcache.tagsinuse 467.302243 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 9451134 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 1123328 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 8.413512 # Average number of references to valid blocks.
+system.cpu0.dcache.replacements 1274576 # number of replacements
+system.cpu0.dcache.tagsinuse 505.658053 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 10359284 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 1275088 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 8.124368 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 467.302243 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.912700 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.912700 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 5816576 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 5816576 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3291002 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3291002 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156681 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 156681 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 180603 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 180603 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 9107578 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 9107578 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 9107578 # number of overall hits
-system.cpu0.dcache.overall_hits::total 9107578 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 1395487 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1395487 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1670757 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1670757 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17192 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 17192 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 672 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 672 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 3066244 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 3066244 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 3066244 # number of overall misses
-system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 173873 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 173873 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181275 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 181275 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 12173822 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 12173822 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 12173822 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 12173822 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193493 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.193493 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.336727 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.336727 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098877 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098877 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003707 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003707 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251872 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.251872 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked
+system.cpu0.dcache.occ_blocks::cpu0.data 505.658053 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.987613 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.987613 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6368256 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6368256 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3633863 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3633863 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160621 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 160621 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185111 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 185111 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 10002119 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 10002119 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 10002119 # number of overall hits
+system.cpu0.dcache.overall_hits::total 10002119 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 1588144 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1588144 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1741180 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1741180 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20406 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 20406 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2921 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 2921 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 3329324 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 3329324 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 3329324 # number of overall misses
+system.cpu0.dcache.overall_misses::total 3329324 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34092049500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 34092049500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69554473067 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 69554473067 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288471000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 288471000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21390500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 21390500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 103646522567 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 103646522567 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 103646522567 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 103646522567 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 7956400 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 7956400 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 5375043 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5375043 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181027 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 181027 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188032 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 188032 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 13331443 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 13331443 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 13331443 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 13331443 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199606 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.199606 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323938 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.323938 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112724 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112724 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015535 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015535 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249735 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.249735 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249735 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.249735 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21466.598432 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 21466.598432 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39946.744775 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 39946.744775 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14136.577477 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14136.577477 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7323.005820 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7323.005820 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 31131.401620 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 31131.401620 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 2393556 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 1763 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 48538 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.599082 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 131.285714 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 49.313033 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 251.857143 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 614637 # number of writebacks
-system.cpu0.dcache.writebacks::total 614637 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 536909 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 536909 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1412908 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1412908 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3986 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3986 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1949817 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1949817 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1949817 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1949817 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 858578 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 858578 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257849 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 257849 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13206 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13206 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 672 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 672 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1116427 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1116427 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051967 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051967 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075952 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075952 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 749955 # number of writebacks
+system.cpu0.dcache.writebacks::total 749955 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 587926 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 587926 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1468148 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1468148 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4517 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4517 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 2056074 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 2056074 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 2056074 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 2056074 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1000218 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 1000218 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273032 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 273032 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15889 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15889 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2921 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 2921 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1273250 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1273250 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1273250 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1273250 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21325955000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21325955000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10169026713 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10169026713 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181062500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181062500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15548500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15548500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31494981713 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 31494981713 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31494981713 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 31494981713 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1455479000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1455479000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128324998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128324998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3583803998 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3583803998 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125712 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125712 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050796 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050796 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087771 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087771 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015535 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015535 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.095507 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.095507 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21321.306955 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21321.306955 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37244.816406 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37244.816406 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11395.462269 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.462269 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5323.005820 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5323.005820 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2657978 # DTB read hits
-system.cpu1.dtb.read_misses 12789 # DTB read misses
-system.cpu1.dtb.read_acv 27 # DTB read access violations
-system.cpu1.dtb.read_accesses 325192 # DTB read accesses
-system.cpu1.dtb.write_hits 1642917 # DTB write hits
-system.cpu1.dtb.write_misses 2443 # DTB write misses
+system.cpu1.dtb.read_hits 1943067 # DTB read hits
+system.cpu1.dtb.read_misses 10795 # DTB read misses
+system.cpu1.dtb.read_acv 23 # DTB read access violations
+system.cpu1.dtb.read_accesses 324453 # DTB read accesses
+system.cpu1.dtb.write_hits 1254400 # DTB write hits
+system.cpu1.dtb.write_misses 2201 # DTB write misses
system.cpu1.dtb.write_acv 63 # DTB write access violations
-system.cpu1.dtb.write_accesses 132832 # DTB write accesses
-system.cpu1.dtb.data_hits 4300895 # DTB hits
-system.cpu1.dtb.data_misses 15232 # DTB misses
-system.cpu1.dtb.data_acv 90 # DTB access violations
-system.cpu1.dtb.data_accesses 458024 # DTB accesses
-system.cpu1.itb.fetch_hits 468004 # ITB hits
-system.cpu1.itb.fetch_misses 6860 # ITB misses
-system.cpu1.itb.fetch_acv 223 # ITB acv
-system.cpu1.itb.fetch_accesses 474864 # ITB accesses
+system.cpu1.dtb.write_accesses 132933 # DTB write accesses
+system.cpu1.dtb.data_hits 3197467 # DTB hits
+system.cpu1.dtb.data_misses 12996 # DTB misses
+system.cpu1.dtb.data_acv 86 # DTB access violations
+system.cpu1.dtb.data_accesses 457386 # DTB accesses
+system.cpu1.itb.fetch_hits 434450 # ITB hits
+system.cpu1.itb.fetch_misses 7705 # ITB misses
+system.cpu1.itb.fetch_acv 232 # ITB acv
+system.cpu1.itb.fetch_accesses 442155 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 24425153 # number of cpu cycles simulated
+system.cpu1.numCycles 16039611 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 3729082 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 2617746 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 2161338 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 77903 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 1516620 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 873996 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 182212 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 8242 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1056208 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 2219979 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 406574 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 6282819 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 27064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 67109 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 53469 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 1501296 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 52568 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 14943285 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.828159 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.202626 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 12723306 85.14% 85.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 143447 0.96% 86.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 238457 1.60% 87.70% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 178791 1.20% 88.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 308600 2.07% 90.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 118341 0.79% 91.75% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 133550 0.89% 92.65% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 199066 1.33% 93.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 899727 6.02% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.152674 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.732653 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 8206589 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 10101487 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 617828 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 13962547 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 36109 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 2150385 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 1081456 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 443630 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 21892478 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.637778 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.318020 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 14943285 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.163205 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.771553 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 5967965 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 6534138 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 2076282 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 111928 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 252971 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 114663 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 7593 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 12129871 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 22496 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 252971 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 6175430 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 499012 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 5393527 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 1978606 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 643737 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 11250530 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 66 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 56207 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 157985 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 7407591 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 13449617 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 13309138 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 140479 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 6324692 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1082899 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 450684 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 43314 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 1976964 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2055976 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1329039 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 193469 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 109268 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 9879442 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 495628 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 9611427 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 29957 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1443490 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 718060 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 356268 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 14943285 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.643194 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.319140 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 15854245 72.42% 72.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 2672796 12.21% 84.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 1184242 5.41% 90.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 847687 3.87% 93.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 726248 3.32% 97.23% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 300582 1.37% 98.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 191038 0.87% 99.47% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 101044 0.46% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 14596 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 10722627 71.76% 71.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 1934278 12.94% 84.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 829364 5.55% 90.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 551304 3.69% 93.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 470726 3.15% 97.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 216087 1.45% 98.54% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 139402 0.93% 99.47% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 71218 0.48% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 8279 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 21892478 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 14943285 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 17685 7.13% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 130361 52.59% 59.73% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 99827 40.27% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 3634 1.84% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 107033 54.32% 56.16% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 86373 43.84% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 9165178 65.64% 65.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 22201 0.16% 65.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 10896 0.08% 65.90% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 2775695 19.88% 85.80% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1670228 11.96% 97.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 313060 2.24% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 5997328 62.40% 62.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 16465 0.17% 62.61% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 10793 0.11% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2032935 21.15% 83.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1277891 13.30% 97.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 270726 2.82% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 13962547 # Type of FU issued
-system.cpu1.iq.rate 0.571646 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 247873 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.017753 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 49890568 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 17097827 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 13608739 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 210986 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 102380 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 99816 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 14096605 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 110289 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 133191 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 9611427 # Type of FU issued
+system.cpu1.iq.rate 0.599231 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 197040 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.020501 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 34189984 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 11721176 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 9344184 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 203152 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 99152 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 96176 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 9699010 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 105931 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 93506 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 414475 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 850 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 286352 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 1028 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 1836 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 129863 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 382 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 9210 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 188335 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 13825969 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 2678414 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 136578 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 252971 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 330484 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 40597 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 10884350 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 145943 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2055976 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1329039 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 449000 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 33362 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2246 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 1836 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 35752 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 100142 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 135894 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 9521603 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 1961135 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 89824 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 825136 # number of nop insts executed
-system.cpu1.iew.exec_refs 4329493 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 2168898 # Number of branches executed
-system.cpu1.iew.exec_stores 1651079 # Number of stores executed
-system.cpu1.iew.exec_rate 0.566055 # Inst execution rate
-system.cpu1.iew.wb_sent 13745874 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 13708555 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 6651311 # num instructions producing a value
-system.cpu1.iew.wb_consumers 9340604 # num instructions consuming a value
+system.cpu1.iew.exec_nop 509280 # number of nop insts executed
+system.cpu1.iew.exec_refs 3223669 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 1421889 # Number of branches executed
+system.cpu1.iew.exec_stores 1262534 # Number of stores executed
+system.cpu1.iew.exec_rate 0.593631 # Inst execution rate
+system.cpu1.iew.wb_sent 9469121 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 9440360 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 4419848 # num instructions producing a value
+system.cpu1.iew.wb_consumers 6207573 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.561247 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.712086 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.588565 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.712009 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 2293261 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 174198 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 176022 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 21515613 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.628195 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.562431 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1489613 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 139360 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 127942 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 14690314 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.634143 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.577922 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 16491806 76.65% 76.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 2174989 10.11% 86.76% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1058158 4.92% 91.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 548223 2.55% 94.23% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 352308 1.64% 95.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 166690 0.77% 96.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 160522 0.75% 97.38% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 129128 0.60% 97.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 433789 2.02% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 11205689 76.28% 76.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 1626477 11.07% 87.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 606444 4.13% 91.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 368240 2.51% 93.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 264133 1.80% 95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 104886 0.71% 96.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 108759 0.74% 97.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 107326 0.73% 97.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 298360 2.03% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 21515613 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 13515996 # Number of instructions committed
-system.cpu1.commit.committedOps 13515996 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 14690314 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 9315763 # Number of instructions committed
+system.cpu1.commit.committedOps 9315763 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 3973553 # Number of memory references committed
-system.cpu1.commit.loads 2406453 # Number of loads committed
-system.cpu1.commit.membars 57533 # Number of memory barriers committed
-system.cpu1.commit.branches 2017672 # Number of branches committed
-system.cpu1.commit.fp_insts 98521 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 12496541 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 216490 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 433789 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 2968800 # Number of memory references committed
+system.cpu1.commit.loads 1769624 # Number of loads committed
+system.cpu1.commit.membars 44277 # Number of memory barriers committed
+system.cpu1.commit.branches 1334383 # Number of branches committed
+system.cpu1.commit.fp_insts 94889 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 8635888 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 148923 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 298360 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 36803153 # The number of ROB reads
-system.cpu1.rob.rob_writes 31994561 # The number of ROB writes
-system.cpu1.timesIdled 237566 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 2532675 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3770663279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 12791729 # Number of Instructions Simulated
-system.cpu1.committedOps 12791729 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 12791729 # Number of Instructions Simulated
-system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads
-system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes
-system.cpu1.icache.replacements 297472 # number of replacements
-system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use
-system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits
-system.cpu1.icache.overall_hits::total 1814153 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses
-system.cpu1.icache.overall_misses::total 311692 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13820.779795 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13820.779795 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 806 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 423 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 43 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.744186 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets 423 # average number of cycles each access was blocked
+system.cpu1.rob.rob_reads 25106022 # The number of ROB reads
+system.cpu1.rob.rob_writes 21862282 # The number of ROB writes
+system.cpu1.timesIdled 131003 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 1096326 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 3786825078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 8868192 # Number of Instructions Simulated
+system.cpu1.committedOps 8868192 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 8868192 # Number of Instructions Simulated
+system.cpu1.cpi 1.808668 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.808668 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.552893 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.552893 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 12288735 # number of integer regfile reads
+system.cpu1.int_regfile_writes 6719305 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 52595 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 52295 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 519807 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 218837 # number of misc regfile writes
+system.cpu1.icache.replacements 223384 # number of replacements
+system.cpu1.icache.tagsinuse 470.911172 # Cycle average of tags in use
+system.cpu1.icache.total_refs 1268764 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 223896 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 5.666756 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1876151234000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 470.911172 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.919748 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.919748 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 1268764 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 1268764 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 1268764 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 1268764 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 1268764 # number of overall hits
+system.cpu1.icache.overall_hits::total 1268764 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 232532 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 232532 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 232532 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 232532 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 232532 # number of overall misses
+system.cpu1.icache.overall_misses::total 232532 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3191119498 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 3191119498 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 3191119498 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 3191119498 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 3191119498 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 3191119498 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 1501296 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 1501296 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 1501296 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 1501296 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 1501296 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 1501296 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154888 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.154888 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154888 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.154888 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154888 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.154888 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13723.356347 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13723.356347 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13723.356347 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13723.356347 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 852 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 37.043478 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 13650 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 13650 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 13650 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 13650 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 13650 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 13650 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 298042 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 298042 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 298042 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 298042 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 298042 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 298042 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3567181997 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 3567181997 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3567181997 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 3567181997 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3567181997 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 3567181997 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140199 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.140199 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.140199 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11968.722519 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223964 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 223964 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 223964 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 223964 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 223964 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 223964 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2651052998 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 2651052998 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2651052998 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 2651052998 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2651052998 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 2651052998 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.149180 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.149180 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.149180 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11836.960395 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 296647 # number of replacements
-system.cpu1.dcache.tagsinuse 497.527759 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 3293413 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 297044 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 11.087290 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 36352469000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 497.527759 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.971734 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.971734 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 2035773 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 2035773 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 1175370 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 1175370 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40064 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 40064 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 42523 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 42523 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 3211143 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 3211143 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 3211143 # number of overall hits
-system.cpu1.dcache.overall_hits::total 3211143 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 433262 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 433262 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 718 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 718 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses
-system.cpu1.dcache.overall_misses::total 774607 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736455500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 6736455500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 20256380174 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 20256380174 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 20256380174 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 20256380174 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43241 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 43241 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 3985750 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.175478 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.175478 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225055 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7069.637883 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7069.637883 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 67.523742 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 3 # average number of cycles each access was blocked
+system.cpu1.dcache.replacements 107089 # number of replacements
+system.cpu1.dcache.tagsinuse 492.773988 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 2615920 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 107493 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 24.335724 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 38980492000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 492.773988 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.962449 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.962449 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 1604976 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 1604976 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 940707 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 940707 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33481 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 33481 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32051 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 32051 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 2545683 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 2545683 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 2545683 # number of overall hits
+system.cpu1.dcache.overall_hits::total 2545683 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 206048 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 206048 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 217271 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 217271 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5237 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 5237 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3060 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 3060 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 423319 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 423319 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 423319 # number of overall misses
+system.cpu1.dcache.overall_misses::total 423319 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3148302000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 3148302000 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8860772084 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 8860772084 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54690000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 54690000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22134000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 22134000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 12009074084 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 12009074084 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 12009074084 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 12009074084 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 1811024 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 1811024 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 1157978 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 1157978 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38718 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 38718 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35111 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 35111 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 2969002 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 2969002 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 2969002 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 2969002 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.113774 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.113774 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187630 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.187630 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135260 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135260 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087152 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087152 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.142580 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.142580 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.142580 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.142580 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15279.459155 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15279.459155 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40782.120412 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 40782.120412 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10443.001719 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10443.001719 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7233.333333 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7233.333333 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28368.852057 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 28368.852057 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28368.852057 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 28368.852057 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 339060 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 3910 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 86.716113 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 225448 # number of writebacks
-system.cpu1.dcache.writebacks::total 225448 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 193837 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 193837 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 283225 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 283225 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1368 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1368 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 477062 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 477062 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 477062 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 477062 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 239425 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 239425 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58120 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 58120 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 70825 # number of writebacks
+system.cpu1.dcache.writebacks::total 70825 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 127864 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 127864 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 178553 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 178553 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 567 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 567 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 306417 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 306417 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 306417 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 306417 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 78184 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 78184 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 38718 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 38718 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4670 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4670 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3058 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 3058 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 116902 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 116902 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 116902 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 116902 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 956868500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 956868500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1322831987 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1322831987 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38016500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38016500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16018000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16018000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2279700487 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2279700487 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2279700487 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2279700487 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30982500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30982500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 645432500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 645432500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676415000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676415000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043171 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043171 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033436 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033436 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120616 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120616 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087095 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087095 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.039374 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.039374 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12238.674153 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12238.674153 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34165.814014 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34165.814014 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8140.578158 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.578158 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5238.064094 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5238.064094 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 169372 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 58506 39.88% 39.88% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 135 0.09% 39.97% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1925 1.31% 41.28% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 16 0.01% 41.29% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 86127 58.71% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 146709 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 57513 49.12% 49.12% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 135 0.12% 49.23% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1925 1.64% 50.88% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 16 0.01% 50.89% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 57499 49.11% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 117088 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1866028984500 98.32% 98.32% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 63917500 0.00% 98.33% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 571228500 0.03% 98.36% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 8802500 0.00% 98.36% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 31183758000 1.64% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1897856691000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.983027 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6541 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 182292 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 64399 40.43% 40.43% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 137 0.09% 40.52% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1928 1.21% 41.73% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 188 0.12% 41.85% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 92618 58.15% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 159270 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 63397 49.20% 49.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 137 0.11% 49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1928 1.50% 50.80% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 63212 49.05% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 128862 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1866521704000 98.15% 98.15% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 63425000 0.00% 98.15% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 571234500 0.03% 98.18% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 91794500 0.00% 98.19% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 34470644500 1.81% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1901718802500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.984441 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.667607 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.798097 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed
-system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed
-system.cpu0.kern.syscall::4 4 1.91% 13.40% # number of syscalls executed
-system.cpu0.kern.syscall::6 29 13.88% 27.27% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.48% 27.75% # number of syscalls executed
-system.cpu0.kern.syscall::17 9 4.31% 32.06% # number of syscalls executed
-system.cpu0.kern.syscall::19 7 3.35% 35.41% # number of syscalls executed
-system.cpu0.kern.syscall::20 4 1.91% 37.32% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.48% 37.80% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.44% 39.23% # number of syscalls executed
-system.cpu0.kern.syscall::33 7 3.35% 42.58% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.96% 43.54% # number of syscalls executed
-system.cpu0.kern.syscall::45 37 17.70% 61.24% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.44% 62.68% # number of syscalls executed
-system.cpu0.kern.syscall::48 8 3.83% 66.51% # number of syscalls executed
-system.cpu0.kern.syscall::54 9 4.31% 70.81% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.48% 71.29% # number of syscalls executed
-system.cpu0.kern.syscall::59 5 2.39% 73.68% # number of syscalls executed
-system.cpu0.kern.syscall::71 27 12.92% 86.60% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.44% 88.04% # number of syscalls executed
-system.cpu0.kern.syscall::74 7 3.35% 91.39% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed
-system.cpu0.kern.syscall::90 2 0.96% 92.82% # number of syscalls executed
-system.cpu0.kern.syscall::92 7 3.35% 96.17% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.96% 97.13% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.96% 98.09% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.48% 98.56% # number of syscalls executed
-system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 209 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.682502 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.809079 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed
+system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed
+system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed
+system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed
+system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed
+system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed
+system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed
+system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed
+system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed
+system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed
+system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed
+system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed
+system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed
+system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed
+system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed
+system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed
+system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed
+system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed
+system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed
+system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed
+system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed
+system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed
+system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed
+system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed
+system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 202 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 100 0.06% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3082 1.99% 2.06% # number of callpals executed
-system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 140299 90.69% 92.78% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6336 4.10% 96.88% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 96.88% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed
-system.cpu0.kern.callpal::rti 4335 2.80% 99.69% # number of callpals executed
-system.cpu0.kern.callpal::callsys 342 0.22% 99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 154704 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6439 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1272 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 291 0.17% 0.17% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3482 2.08% 2.25% # number of callpals executed
+system.cpu0.kern.callpal::tbi 48 0.03% 2.28% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 152520 91.05% 93.34% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6170 3.68% 97.03% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 97.03% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 97.03% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed
+system.cpu0.kern.callpal::rti 4499 2.69% 99.72% # number of callpals executed
+system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 167505 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 7002 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1256 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1271
-system.cpu0.kern.mode_good::user 1272
+system.cpu0.kern.mode_good::kernel 1255
+system.cpu0.kern.mode_good::user 1256
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.197391 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.179235 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.329789 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1895973773500 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1882909500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.304069 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1899848666000 99.90% 99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 1870128500 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3083 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3483 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 3800 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 68195 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 23112 38.67% 38.67% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1924 3.22% 41.89% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 100 0.17% 42.06% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 34629 57.94% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 59765 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 22728 47.97% 47.97% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1924 4.06% 52.03% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 100 0.21% 52.24% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 22629 47.76% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 47381 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1870052426500 98.55% 98.55% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 533448500 0.03% 98.58% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 47034500 0.00% 98.58% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 26913191500 1.42% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1897546101000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.983385 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 57520 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 17961 36.86% 36.86% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1928 3.96% 40.82% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 291 0.60% 41.41% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 28549 58.59% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 48729 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 17586 47.40% 47.40% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1928 5.20% 52.60% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 291 0.78% 53.38% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 17296 46.62% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 37101 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1876762048000 98.70% 98.70% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 532687000 0.03% 98.73% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 132052500 0.01% 98.74% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 24006771500 1.26% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1901433559000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.979121 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.653470 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.792788 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed
-system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed
-system.cpu1.kern.syscall::6 13 11.11% 23.08% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 0.85% 23.93% # number of syscalls executed
-system.cpu1.kern.syscall::17 6 5.13% 29.06% # number of syscalls executed
-system.cpu1.kern.syscall::19 3 2.56% 31.62% # number of syscalls executed
-system.cpu1.kern.syscall::20 2 1.71% 33.33% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 2.56% 35.90% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 2.56% 38.46% # number of syscalls executed
-system.cpu1.kern.syscall::33 4 3.42% 41.88% # number of syscalls executed
-system.cpu1.kern.syscall::45 17 14.53% 56.41% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 2.56% 58.97% # number of syscalls executed
-system.cpu1.kern.syscall::48 2 1.71% 60.68% # number of syscalls executed
-system.cpu1.kern.syscall::54 1 0.85% 61.54% # number of syscalls executed
-system.cpu1.kern.syscall::59 2 1.71% 63.25% # number of syscalls executed
-system.cpu1.kern.syscall::71 27 23.08% 86.32% # number of syscalls executed
-system.cpu1.kern.syscall::74 9 7.69% 94.02% # number of syscalls executed
-system.cpu1.kern.syscall::90 1 0.85% 94.87% # number of syscalls executed
-system.cpu1.kern.syscall::92 2 1.71% 96.58% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.56% 99.15% # number of syscalls executed
-system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 117 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.605836 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.761374 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed
+system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed
+system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed
+system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed
+system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed
+system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed
+system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed
+system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed
+system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed
+system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed
+system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed
+system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed
+system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed
+system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed
+system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed
+system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 124 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 16 0.03% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1165 1.89% 1.92% # number of callpals executed
-system.cpu1.kern.callpal::tbi 6 0.01% 1.93% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 1.94% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 54867 89.09% 91.04% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2419 3.93% 94.96% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 94.96% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 94.97% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 1 0.00% 94.97% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 94.98% # number of callpals executed
-system.cpu1.kern.callpal::rti 2874 4.67% 99.64% # number of callpals executed
-system.cpu1.kern.callpal::callsys 175 0.28% 99.93% # number of callpals executed
-system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1118 2.21% 2.58% # number of callpals executed
+system.cpu1.kern.callpal::tbi 6 0.01% 2.60% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 43429 85.72% 88.33% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2596 5.12% 93.45% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 93.45% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 93.46% # number of callpals executed
+system.cpu1.kern.callpal::rdusp 1 0.00% 93.46% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.01% 93.47% # number of callpals executed
+system.cpu1.kern.callpal::rti 3081 6.08% 99.55% # number of callpals executed
+system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed
+system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 61585 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1629 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 476 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 537
-system.cpu1.kern.mode_good::user 476
-system.cpu1.kern.mode_good::idle 61
-system.cpu1.kern.mode_switch_good::kernel 0.329650 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 50665 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1406 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 488 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2430 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 704
+system.cpu1.kern.mode_good::user 488
+system.cpu1.kern.mode_good::idle 216
+system.cpu1.kern.mode_switch_good::kernel 0.500711 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.029814 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.258733 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 37752222500 1.99% 1.99% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 817466500 0.04% 2.03% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1858966004500 97.97% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1166 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.088889 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.325624 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 4780653500 0.25% 0.25% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 828450500 0.04% 0.29% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1895813783000 99.71% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1119 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.854350 # Number of seconds simulated
-sim_ticks 1854349611000 # Number of ticks simulated
-final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.854344 # Number of seconds simulated
+sim_ticks 1854344296500 # Number of ticks simulated
+final_tick 1854344296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55480 # Simulator instruction rate (inst/s)
-host_op_rate 55480 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1941178876 # Simulator tick rate (ticks/s)
-host_mem_usage 331452 # Number of bytes of host memory used
-host_seconds 955.27 # Real time elapsed on the host
-sim_insts 52998188 # Number of instructions simulated
-sim_ops 52998188 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory
+host_inst_rate 131278 # Simulator instruction rate (inst/s)
+host_op_rate 131278 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4595190559 # Simulator tick rate (ticks/s)
+host_mem_usage 336376 # Number of bytes of host memory used
+host_seconds 403.54 # Real time elapsed on the host
+sim_insts 52976017 # Number of instructions simulated
+sim_ops 52976017 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 964864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24879424 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28499904 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7518592 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7518592 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28496576 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 964864 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 964864 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7516416 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15076 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388741 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 445311 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117478 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117478 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 521567 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13417345 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1430306 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15369218 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 521567 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 521567 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4054571 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4054571 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4054571 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 521567 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13417345 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1430306 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19423789 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 445311 # Total number of read requests seen
-system.physmem.writeReqs 117478 # Total number of write requests seen
-system.physmem.cpureqs 564077 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28499904 # Total number of bytes read from memory
-system.physmem.bytesWritten 7518592 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28499904 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7518592 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28171 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 27744 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 27861 # Track reads on a per bank basis
+system.physmem.num_reads::total 445259 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 117444 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 520326 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13416831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1430310 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15367468 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 520326 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 520326 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4053409 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4053409 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4053409 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 520326 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13416831 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1430310 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19420877 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 445259 # Total number of read requests seen
+system.physmem.writeReqs 117444 # Total number of write requests seen
+system.physmem.cpureqs 564803 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28496576 # Total number of bytes read from memory
+system.physmem.bytesWritten 7516416 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28496576 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 63 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28168 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 27749 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 27864 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28325 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 28126 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27859 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28323 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 28119 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27841 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 27840 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27508 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 27634 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27843 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27857 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27753 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27753 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27902 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7651 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7405 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7296 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6891 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7793 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7560 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7306 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7405 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7055 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7167 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7397 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7475 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7357 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::8 27856 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27503 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27630 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27839 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27855 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27734 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27743 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27895 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7646 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7409 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7290 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6889 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7790 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7556 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7291 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7179 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7418 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7047 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7168 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7402 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7478 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7343 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7329 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7328 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 554 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1854344226000 # Total gap between requests
+system.physmem.numWrRetry 1365 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1854338900000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 445311 # Categorize read packet sizes
+system.physmem.readPktSize::6 445259 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 118032 # categorize write packet sizes
+system.physmem.writePktSize::6 118809 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 175 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 176 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 331896 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 65179 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 18458 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 6410 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2875 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2427 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1797 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2003 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1654 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1944 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1608 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1627 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1778 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1217 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1424 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 888 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 331910 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 65137 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 18515 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 6392 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2870 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1760 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2006 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1645 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1906 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1549 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1660 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1745 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1229 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1437 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 898 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 276 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 159 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3926 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4929 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4979 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 5052 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5068 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3944 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4840 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4990 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5050 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5066 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5100 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5101 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 5108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 5108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 5108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 5108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 5108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 5108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 5108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1163 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 267 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 171 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 57 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 6253510302 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13461286302 # Sum of mem lat for all requests
-system.physmem.totBusLat 1781012000 # Total cycles spent in databus access
-system.physmem.totBankLat 5426764000 # Total cycles spent in bank access
-system.physmem.avgQLat 14044.85 # Average queueing delay per request
-system.physmem.avgBankLat 12188.05 # Average bank access latency per request
+system.physmem.totQLat 6228802493 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13434068493 # Sum of mem lat for all requests
+system.physmem.totBusLat 1780784000 # Total cycles spent in databus access
+system.physmem.totBankLat 5424482000 # Total cycles spent in bank access
+system.physmem.avgQLat 13991.15 # Average queueing delay per request
+system.physmem.avgBankLat 12184.48 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30232.89 # Average memory access latency
+system.physmem.avgMemAccLat 30175.63 # Average memory access latency
system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 11.07 # Average write queue length over time
-system.physmem.readRowHits 425296 # Number of row buffer hits during reads
-system.physmem.writeRowHits 76454 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 65.08 # Row buffer hit rate for writes
-system.physmem.avgGap 3294919.10 # Average gap between requests
+system.physmem.avgWrQLen 11.37 # Average write queue length over time
+system.physmem.readRowHits 425317 # Number of row buffer hits during reads
+system.physmem.writeRowHits 76610 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.53 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 65.23 # Row buffer hit rate for writes
+system.physmem.avgGap 3295413.21 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.265413 # Cycle average of tags in use
+system.iocache.tagsinuse 1.265367 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1704469740000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.079088 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 1704469917000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.265367 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.079085 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.079085 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 9494924806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 9494924806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 9515852804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 9515852804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 9515852804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 9515852804 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 9519862806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 9519862806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 9540790804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 9540790804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 9540790804 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 9540790804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228507.046737 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 228507.046737 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 228061.181642 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 228061.181642 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 189089 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229107.210387 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 229107.210387 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 228658.856896 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 228658.856896 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 228658.856896 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 228658.856896 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 189620 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 22862 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 22696 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.270886 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.354776 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7332138561 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7332138561 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 7344069561 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7344069561 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 7344069561 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7344069561 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7357096000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7357096000 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 7369027000 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7369027000 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 7369027000 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7369027000 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176456.934949 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 176456.934949 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177057.566423 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 177057.566423 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176609.394847 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 176609.394847 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176609.394847 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 176609.394847 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9959916 # DTB read hits
-system.cpu.dtb.read_misses 41524 # DTB read misses
-system.cpu.dtb.read_acv 557 # DTB read access violations
-system.cpu.dtb.read_accesses 942700 # DTB read accesses
-system.cpu.dtb.write_hits 6603148 # DTB write hits
-system.cpu.dtb.write_misses 10669 # DTB write misses
-system.cpu.dtb.write_acv 409 # DTB write access violations
-system.cpu.dtb.write_accesses 338186 # DTB write accesses
-system.cpu.dtb.data_hits 16563064 # DTB hits
-system.cpu.dtb.data_misses 52193 # DTB misses
-system.cpu.dtb.data_acv 966 # DTB access violations
-system.cpu.dtb.data_accesses 1280886 # DTB accesses
-system.cpu.itb.fetch_hits 1308562 # ITB hits
-system.cpu.itb.fetch_misses 36917 # ITB misses
-system.cpu.itb.fetch_acv 1051 # ITB acv
-system.cpu.itb.fetch_accesses 1345479 # ITB accesses
+system.cpu.dtb.read_hits 9948747 # DTB read hits
+system.cpu.dtb.read_misses 41658 # DTB read misses
+system.cpu.dtb.read_acv 544 # DTB read access violations
+system.cpu.dtb.read_accesses 942034 # DTB read accesses
+system.cpu.dtb.write_hits 6596243 # DTB write hits
+system.cpu.dtb.write_misses 10259 # DTB write misses
+system.cpu.dtb.write_acv 405 # DTB write access violations
+system.cpu.dtb.write_accesses 337916 # DTB write accesses
+system.cpu.dtb.data_hits 16544990 # DTB hits
+system.cpu.dtb.data_misses 51917 # DTB misses
+system.cpu.dtb.data_acv 949 # DTB access violations
+system.cpu.dtb.data_accesses 1279950 # DTB accesses
+system.cpu.itb.fetch_hits 1308175 # ITB hits
+system.cpu.itb.fetch_misses 37074 # ITB misses
+system.cpu.itb.fetch_acv 1064 # ITB acv
+system.cpu.itb.fetch_accesses 1345249 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 108866981 # number of cpu cycles simulated
+system.cpu.numCycles 108725026 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 13878911 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11630816 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 403232 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9482716 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 5833581 # Number of BTB hits
+system.cpu.BPredUnit.lookups 13851594 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11614390 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 401305 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9533712 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 5819078 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 911561 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 38998 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 28184398 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 70994195 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13878911 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6745142 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 13311939 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2031019 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37417570 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 255429 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 315513 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8617973 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 269432 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 80827249 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.878345 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.221663 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 909714 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 39020 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 28116472 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 70876145 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13851594 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6728792 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 13285208 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2019522 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 37381794 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 31979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 254614 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 318469 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 142 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8594512 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 267109 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 80688804 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.878389 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.221787 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67515310 83.53% 83.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 859289 1.06% 84.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1709305 2.11% 86.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 824937 1.02% 87.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2774546 3.43% 91.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 565272 0.70% 91.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 652347 0.81% 92.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1007085 1.25% 93.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4919158 6.09% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 67403596 83.54% 83.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 853020 1.06% 84.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1704381 2.11% 86.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 825297 1.02% 87.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2770281 3.43% 91.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 565024 0.70% 91.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 647860 0.80% 92.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1009692 1.25% 93.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4909653 6.08% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 80827249 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.127485 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.652119 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29306094 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37119542 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 12159527 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 975132 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1266953 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 590499 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 43097 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 69660736 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 130298 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1266953 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 30443941 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 13656496 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19805604 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 11392846 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4261407 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 65802441 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 6765 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 504009 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1491914 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 43932847 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 79894315 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79415060 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 479255 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38191269 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5741570 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1687796 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 244874 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12188114 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10482106 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6925475 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1313213 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 855117 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58302952 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2055207 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 56888280 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 110464 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6988476 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3659625 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1390229 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 80827249 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.703826 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.364551 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 80688804 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.127400 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.651884 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29267449 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 37052866 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 12136986 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 973710 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1257792 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 584936 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 69563521 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 129851 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1257792 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 30404358 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 13652369 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 19747652 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 11366309 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4260322 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 65705710 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 6891 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 503348 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1491459 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 43870153 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 79781182 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 79301924 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 479258 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38177024 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 5693121 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1683221 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 240085 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12184382 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10464940 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6914709 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1324795 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 859458 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58224316 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2050276 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 56824991 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 109552 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6935340 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3625371 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1389407 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 80688804 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.704249 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.364971 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56119293 69.43% 69.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10851228 13.43% 82.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5175866 6.40% 89.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3389461 4.19% 93.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2645582 3.27% 96.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1466047 1.81% 98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 750476 0.93% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 332850 0.41% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 96446 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56018871 69.43% 69.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10823549 13.41% 82.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5172467 6.41% 89.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3386571 4.20% 93.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2641337 3.27% 96.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1466438 1.82% 98.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 753039 0.93% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 331233 0.41% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 95299 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 80827249 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 80688804 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 91026 11.51% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 373270 47.20% 58.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 326472 41.29% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 89852 11.44% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 373396 47.53% 58.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 322395 41.04% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 38768679 68.15% 68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61732 0.11% 68.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 38724808 68.15% 68.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10391331 18.27% 86.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6681118 11.74% 98.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 948891 1.67% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10379587 18.27% 86.59% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6673501 11.74% 98.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 948876 1.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 56888280 # Type of FU issued
-system.cpu.iq.rate 0.522549 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 790768 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013900 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 194812399 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 67023826 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55617934 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 692641 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 336620 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 327880 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 57310327 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 361435 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 598219 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 56824991 # Type of FU issued
+system.cpu.iq.rate 0.522649 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 785643 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013826 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 194541335 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 66886966 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55559556 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 692645 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 336736 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 327839 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 57241937 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 361411 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 597577 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1386761 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3497 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 544022 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1373561 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3601 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 537300 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17955 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 206298 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17953 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 206148 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1266953 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 9965004 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 682330 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 63888752 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 694377 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10482106 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6925475 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1810071 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 511236 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 18909 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 204344 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 411597 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 615941 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 56420713 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 10029634 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 467566 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1257792 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 9964029 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 681966 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 63803743 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 689880 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10464940 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 6914709 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1805552 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 511141 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 18669 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 204181 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 411284 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 615465 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 56359720 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 10018596 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 465270 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3530593 # number of nop insts executed
-system.cpu.iew.exec_refs 16658677 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8937468 # Number of branches executed
-system.cpu.iew.exec_stores 6629043 # Number of stores executed
-system.cpu.iew.exec_rate 0.518254 # Inst execution rate
-system.cpu.iew.wb_sent 56060470 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 55945814 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 27785553 # num instructions producing a value
-system.cpu.iew.wb_consumers 37633865 # num instructions consuming a value
+system.cpu.iew.exec_nop 3529151 # number of nop insts executed
+system.cpu.iew.exec_refs 16640307 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8921025 # Number of branches executed
+system.cpu.iew.exec_stores 6621711 # Number of stores executed
+system.cpu.iew.exec_rate 0.518369 # Inst execution rate
+system.cpu.iew.wb_sent 56002392 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 55887395 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 27763328 # num instructions producing a value
+system.cpu.iew.wb_consumers 37600496 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.513891 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.738313 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.514025 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.738377 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7580888 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 664978 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 571532 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 79560296 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.706241 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.634825 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 7517612 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 660869 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 569940 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 79431012 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.707112 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.636757 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58754657 73.85% 73.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8628270 10.84% 84.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4624578 5.81% 90.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2529268 3.18% 93.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1515738 1.91% 95.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 609533 0.77% 96.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 524421 0.66% 97.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 524312 0.66% 97.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1849519 2.32% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 58662505 73.85% 73.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8598581 10.83% 84.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4616252 5.81% 90.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2527219 3.18% 93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1515396 1.91% 95.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 608578 0.77% 96.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 519366 0.65% 97.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 531746 0.67% 97.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1851369 2.33% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 79560296 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56188709 # Number of instructions committed
-system.cpu.commit.committedOps 56188709 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 79431012 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 56166586 # Number of instructions committed
+system.cpu.commit.committedOps 56166586 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 15476798 # Number of memory references committed
-system.cpu.commit.loads 9095345 # Number of loads committed
-system.cpu.commit.membars 226320 # Number of memory barriers committed
-system.cpu.commit.branches 8447896 # Number of branches committed
+system.cpu.commit.refs 15468788 # Number of memory references committed
+system.cpu.commit.loads 9091379 # Number of loads committed
+system.cpu.commit.membars 226331 # Number of memory barriers committed
+system.cpu.commit.branches 8439881 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 52034633 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740447 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 1849519 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 52016583 # Number of committed integer instructions.
+system.cpu.commit.function_calls 740455 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 1851369 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 141230883 # The number of ROB reads
-system.cpu.rob.rob_writes 128808067 # The number of ROB writes
-system.cpu.timesIdled 1177683 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 28039732 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3599825806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52998188 # Number of Instructions Simulated
-system.cpu.committedOps 52998188 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 52998188 # Number of Instructions Simulated
-system.cpu.cpi 2.054164 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.054164 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.486816 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.486816 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 73962724 # number of integer regfile reads
-system.cpu.int_regfile_writes 40347354 # number of integer regfile writes
-system.cpu.fp_regfile_reads 166024 # number of floating regfile reads
-system.cpu.fp_regfile_writes 167429 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1994989 # number of misc regfile reads
-system.cpu.misc_regfile_writes 947074 # number of misc regfile writes
+system.cpu.rob.rob_reads 141014350 # The number of ROB reads
+system.cpu.rob.rob_writes 128628080 # The number of ROB writes
+system.cpu.timesIdled 1177475 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 28036222 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 3599957129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52976017 # Number of Instructions Simulated
+system.cpu.committedOps 52976017 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 52976017 # Number of Instructions Simulated
+system.cpu.cpi 2.052344 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.052344 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.487248 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.487248 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 73894396 # number of integer regfile reads
+system.cpu.int_regfile_writes 40308039 # number of integer regfile writes
+system.cpu.fp_regfile_reads 165978 # number of floating regfile reads
+system.cpu.fp_regfile_writes 167424 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1987130 # number of misc regfile reads
+system.cpu.misc_regfile_writes 938828 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 1012720 # number of replacements
-system.cpu.icache.tagsinuse 510.299473 # Cycle average of tags in use
-system.cpu.icache.total_refs 7548318 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1013228 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.449772 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 20110483000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.299473 # Average occupied blocks per requestor
+system.cpu.icache.replacements 1010112 # number of replacements
+system.cpu.icache.tagsinuse 510.299453 # Cycle average of tags in use
+system.cpu.icache.total_refs 7527432 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1010620 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 7.448331 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 20108875000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 510.299453 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996679 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996679 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7548319 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7548319 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7548319 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7548319 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7548319 # number of overall hits
-system.cpu.icache.overall_hits::total 7548319 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1069652 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1069652 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1069652 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1069652 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1069652 # number of overall misses
-system.cpu.icache.overall_misses::total 1069652 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14542561994 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14542561994 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14542561994 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14542561994 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14542561994 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14542561994 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 8617971 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8617971 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 8617971 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8617971 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 8617971 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8617971 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124119 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.124119 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.124119 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.124119 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.124119 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.124119 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.601181 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13595.601181 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13595.601181 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13595.601181 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 4808 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 175 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 27.474286 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_hits::cpu.inst 7527433 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7527433 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 7527433 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 7527433 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 7527433 # number of overall hits
+system.cpu.icache.overall_hits::total 7527433 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1067079 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1067079 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1067079 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1067079 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1067079 # number of overall misses
+system.cpu.icache.overall_misses::total 1067079 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14519095993 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14519095993 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14519095993 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14519095993 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14519095993 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14519095993 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 8594512 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 8594512 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 8594512 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 8594512 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 8594512 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 8594512 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124158 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.124158 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.124158 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.124158 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.124158 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.124158 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.392772 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13606.392772 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.392772 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13606.392772 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.392772 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13606.392772 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 4279 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 166 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 25.777108 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56203 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 56203 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 56203 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 56203 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 56203 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 56203 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013449 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1013449 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1013449 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1013449 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1013449 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1013449 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11948814497 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11948814497 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11948814497 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11948814497 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11948814497 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11948814497 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117597 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.117597 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.117597 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.247459 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.247459 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56239 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 56239 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 56239 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 56239 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 56239 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 56239 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010840 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1010840 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1010840 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1010840 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1010840 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1010840 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11925850497 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11925850497 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11925850497 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11925850497 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11925850497 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11925850497 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117615 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117615 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117615 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.117615 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117615 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.117615 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11797.960604 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11797.960604 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11797.960604 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11797.960604 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11797.960604 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11797.960604 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 338368 # number of replacements
-system.cpu.l2cache.tagsinuse 65364.962205 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2548619 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 403534 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 6.315748 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 338316 # number of replacements
+system.cpu.l2cache.tagsinuse 65366.388920 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2545796 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 403484 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 6.309534 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 4043215002 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 54020.981996 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 5337.307261 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6006.672948 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.824295 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.081441 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.091655 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.997390 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 998214 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 826620 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1824834 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 840489 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 840489 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
+system.cpu.l2cache.occ_blocks::writebacks 54012.841717 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 5326.780623 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6026.766580 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.824171 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.081280 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.091961 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.997412 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 995646 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 826421 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1822067 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 840422 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 840422 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 185505 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 185505 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 998214 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1012125 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2010339 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 998214 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1012125 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2010339 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 15114 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 273846 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 288960 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 36 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 36 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 115406 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 115406 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 389252 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 404366 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 389252 # number of overall misses
-system.cpu.l2cache.overall_misses::total 404366 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 909377000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11791174000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 12700551000 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8601240000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 8601240000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 909377000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 20392414000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 21301791000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 909377000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 20392414000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 21301791000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1013328 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1100466 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2113794 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 840489 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 840489 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_hits::cpu.data 185485 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 185485 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 995646 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1011906 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2007552 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 995646 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1011906 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2007552 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 15078 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 273811 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 288889 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 115423 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 115423 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 15078 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 389234 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 404312 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 15078 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 389234 # number of overall misses
+system.cpu.l2cache.overall_misses::total 404312 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 915536500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11794969500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 12710506000 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 273500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 273500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8550291000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 8550291000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 915536500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 20345260500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 21260797000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 915536500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 20345260500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 21260797000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010724 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1100232 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2110956 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 840422 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 840422 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 300911 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 300911 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1013328 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1401377 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2414705 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1013328 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1401377 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2414705 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014915 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248845 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.136702 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.580645 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.580645 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383522 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.383522 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014915 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.277764 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.167460 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014915 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.277764 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.167460 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60167.857615 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43057.682055 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 43952.626661 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74530.267057 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74530.267057 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52679.480965 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52679.480965 # average overall miss latency
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 300908 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 300908 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 1010724 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1401140 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2411864 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1010724 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1401140 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2411864 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014918 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248867 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.136852 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.619048 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.619048 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383582 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.383582 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014918 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.277798 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.167635 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014918 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.277798 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.167635 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60720.022549 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43077.047672 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 43997.888462 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7012.820513 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7012.820513 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74077.878759 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74077.878759 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60720.022549 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52269.998253 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52585.124854 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60720.022549 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52269.998253 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52585.124854 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 75966 # number of writebacks
-system.cpu.l2cache.writebacks::total 75966 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 75932 # number of writebacks
+system.cpu.l2cache.writebacks::total 75932 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273846 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 288959 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115406 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 115406 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 389252 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 404365 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 389252 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 404365 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 718571789 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8247220261 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8965792050 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7172240815 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7172240815 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 718571789 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15419461076 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16138032865 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 718571789 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15419461076 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16138032865 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333809500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333809500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882195500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882195500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216005000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216005000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248845 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136702 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.580645 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.580645 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383522 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383522 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.167459 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.167459 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47546.601535 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30116.270681 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31027.903786 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62147.902319 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62147.902319 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15077 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273811 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 288888 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115423 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 115423 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 15077 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 389234 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 404311 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 15077 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 389234 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 404311 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725191735 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8251461653 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8976653388 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 555033 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 555033 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7120922957 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7120922957 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725191735 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15372384610 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16097576345 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725191735 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15372384610 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16097576345 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333795500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333795500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882091500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882091500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3215887000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3215887000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014917 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248867 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136852 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383582 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383582 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014917 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277798 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.167634 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014917 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277798 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.167634 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48099.206407 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30135.610523 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31073.126568 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14231.615385 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14231.615385 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61694.142043 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61694.142043 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48099.206407 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39493.940946 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39814.836463 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48099.206407 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39493.940946 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39814.836463 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1400783 # number of replacements
+system.cpu.dcache.replacements 1400546 # number of replacements
system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use
-system.cpu.dcache.total_refs 11827578 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1401295 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 8.440463 # Average number of references to valid blocks.
+system.cpu.dcache.total_refs 11813976 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1401058 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 8.432182 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7213661 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7213661 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4203894 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4203894 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 190181 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 190181 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 219613 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 219613 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 11417555 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 11417555 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 11417555 # number of overall hits
-system.cpu.dcache.overall_hits::total 11417555 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1801125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1801125 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1943246 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1943246 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_hits::cpu.data 7207955 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7207955 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4204220 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4204220 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 186078 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 186078 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 215492 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 215492 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 11412175 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 11412175 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 11412175 # number of overall hits
+system.cpu.dcache.overall_hits::total 11412175 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1800587 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1800587 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1942997 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1942997 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 22666 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 22666 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3744371 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3744371 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3744371 # number of overall misses
-system.cpu.dcache.overall_misses::total 3744371 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 33805478000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 33805478000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 71113991647 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 71113991647 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303653500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 303653500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 3743584 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3743584 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3743584 # number of overall misses
+system.cpu.dcache.overall_misses::total 3743584 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 33818200500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 33818200500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 70794455130 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 70794455130 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303687500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 303687500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 104919469647 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 104919469647 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 104919469647 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 104919469647 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 9014786 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9014786 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6147140 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6147140 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 212866 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 212866 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 219615 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 219615 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15161926 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15161926 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15161926 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15161926 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199797 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.199797 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316122 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.316122 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.106569 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.106569 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 104612655630 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 104612655630 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 104612655630 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 104612655630 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 9008542 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9008542 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6147217 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6147217 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208744 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 208744 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 215494 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 215494 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 15155759 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15155759 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15155759 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15155759 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199876 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.199876 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316078 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.316078 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108583 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108583 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.246959 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.246959 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.246959 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.246959 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18769.090430 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 18769.090430 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36595.465344 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36595.465344 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13385.651311 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13385.651311 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.247007 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.247007 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.247007 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.247007 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18781.764225 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18781.764225 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36435.699659 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36435.699659 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13398.372011 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13398.372011 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28020.586007 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28020.586007 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 2640119 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 587 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 95652 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.601294 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 73.375000 # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 27944.519378 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 27944.519378 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27944.519378 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27944.519378 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2603227 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 567 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 95613 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.226706 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 81 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 840489 # number of writebacks
-system.cpu.dcache.writebacks::total 840489 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717559 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 717559 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642936 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1642936 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2360495 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2360495 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2360495 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2360495 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083566 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1083566 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300310 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 300310 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17562 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17562 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 840422 # number of writebacks
+system.cpu.dcache.writebacks::total 840422 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717194 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 717194 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642682 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1642682 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5172 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5172 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2359876 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2359876 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2359876 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2359876 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083393 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1083393 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300315 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 300315 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17494 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17494 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1383876 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1383876 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1383876 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1383876 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21170477000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21170477000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10817290277 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10817290277 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199800500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199800500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 1383708 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1383708 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1383708 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1383708 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21171794000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21171794000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10766258774 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10766258774 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199318000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199318000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31987767277 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 31987767277 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31987767277 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 31987767277 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423886500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423886500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997350998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997350998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421237498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421237498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120199 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120199 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31938052774 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 31938052774 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31938052774 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 31938052774 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423872500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423872500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997246998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997246998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421119498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421119498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120263 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120263 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082503 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082503 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083806 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083806 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19537.782655 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19537.782655 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36020.413163 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36020.413163 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11376.864822 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.864822 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091299 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091299 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091299 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091299 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19542.118142 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19542.118142 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35849.886865 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35849.886865 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11393.506345 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11393.506345 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23081.497523 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23081.497523 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23081.497523 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23081.497523 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 210973 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74651 40.97% 40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 210969 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74649 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105545 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182205 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73284 49.32% 49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31 105543 57.93% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182201 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73282 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73284 49.32% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 148577 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1818516202000 98.07% 98.07% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 64252000 0.00% 98.07% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 558035000 0.03% 98.10% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 35210286000 1.90% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1854348775000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_good::31 73282 49.32% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 148573 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1818511438500 98.07% 98.07% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 63990000 0.00% 98.07% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 557700000 0.03% 98.10% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 35210339500 1.90% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1854343468000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694339 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.694333 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175092 91.23% 93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175088 91.22% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 191934 # number of callpals executed
+system.cpu.kern.callpal::total 191930 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches
system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 29709775500 1.60% 1.60% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2660669000 0.14% 1.75% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1821978322500 98.25% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel 29685190500 1.60% 1.60% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2663206500 0.14% 1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1821995063000 98.26% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.841682 # Number of seconds simulated
-sim_ticks 1841681669500 # Number of ticks simulated
-final_tick 1841681669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.841687 # Number of seconds simulated
+sim_ticks 1841687115500 # Number of ticks simulated
+final_tick 1841687115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 340900 # Simulator instruction rate (inst/s)
-host_op_rate 340900 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9082220288 # Simulator tick rate (ticks/s)
-host_mem_usage 309920 # Number of bytes of host memory used
-host_seconds 202.78 # Real time elapsed on the host
-sim_insts 69127289 # Number of instructions simulated
-sim_ops 69127289 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 474944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 19316864 # Number of bytes read from this memory
+host_inst_rate 299654 # Simulator instruction rate (inst/s)
+host_op_rate 299654 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8001020229 # Simulator tick rate (ticks/s)
+host_mem_usage 317816 # Number of bytes of host memory used
+host_seconds 230.18 # Real time elapsed on the host
+sim_insts 68974794 # Number of instructions simulated
+sim_ops 68974794 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 474496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 19299136 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2832832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 295936 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2722176 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28444928 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 474944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 295936 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 920768 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7479680 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7479680 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 7421 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 301826 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 150016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2831040 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 294592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2739200 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28440768 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 474496 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 150016 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 294592 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 919104 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7474752 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7474752 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 7414 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 301549 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 44263 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 4624 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 42534 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 444452 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 116870 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 116870 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 257886 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 10488709 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1440145 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 81386 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1538177 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 160688 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 1478093 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15445084 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 257886 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 81386 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 160688 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 499960 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4061332 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4061332 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4061332 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 257886 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 10488709 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1440145 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 81386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1538177 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 160688 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1478093 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19506416 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 111038 # Total number of read requests seen
-system.physmem.writeReqs 46173 # Total number of write requests seen
-system.physmem.cpureqs 157553 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 7106432 # Total number of bytes read from memory
-system.physmem.bytesWritten 2955072 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 7106432 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 2955072 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 7 # Number of read reqs serviced by write Q
+system.physmem.num_reads::cpu1.inst 2344 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 44235 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 4603 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 42800 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 444387 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 116793 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 116793 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 257642 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 10479053 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1440140 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 81456 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1537199 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 159958 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 1487332 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15442779 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 257642 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 81456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 159958 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 499055 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4058644 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4058644 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4058644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 257642 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 10479053 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1440140 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 81456 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1537199 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 159958 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1487332 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19501423 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 111257 # Total number of read requests seen
+system.physmem.writeReqs 46272 # Total number of write requests seen
+system.physmem.cpureqs 157922 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 7120448 # Total number of bytes read from memory
+system.physmem.bytesWritten 2961408 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 7120448 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2961408 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 8 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 7075 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 6835 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 6921 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 6580 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 7013 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 7160 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 7199 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 7200 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 6995 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 6907 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 6539 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 7006 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 7093 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 7124 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 7176 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 6821 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 6547 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 6956 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 7030 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 7021 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 7068 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 6779 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 6850 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 3087 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 2885 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 2926 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 2583 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 2986 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 3014 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 3032 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 2994 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 2761 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 2529 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 2745 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 2938 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 3117 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 3088 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 2763 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 2725 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::8 6877 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 6675 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 6909 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 6929 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 7088 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 7137 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 6752 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 6842 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 3139 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 2979 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 2910 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 2542 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 2976 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 2976 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 3003 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 2801 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 2642 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 2700 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 2850 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 3184 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 3157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 2742 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 2711 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 141 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1840669582000 # Total gap between requests
+system.physmem.numWrRetry 191 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1840675056500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 111038 # Categorize read packet sizes
+system.physmem.readPktSize::6 111257 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 46314 # categorize write packet sizes
+system.physmem.writePktSize::6 46463 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 41 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 82621 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 10884 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5829 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1945 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1200 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 997 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 753 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 844 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 697 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 809 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 664 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 650 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 82762 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 10991 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5832 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1968 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1184 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 985 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 747 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 824 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 699 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 800 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 670 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 662 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 686 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 750 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 521 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 613 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 369 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 53 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 38 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 742 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 511 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 379 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 51 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 37 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1636 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1922 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1953 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1976 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1648 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1933 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1959 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1982 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2005 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2005 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2016 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2010 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 2008 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 2007 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 2004 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 2002 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 2001 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1999 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1997 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1996 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1995 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 1993 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 1992 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 1989 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 1988 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 1988 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 1986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 425 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 76 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2011 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2019 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2012 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2012 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 2012 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 2011 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 2007 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 2006 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 2005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 2003 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2002 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2001 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 1998 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 1996 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 1995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 1993 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 1993 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 1992 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 419 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 70 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1659441821 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 3549387821 # Sum of mem lat for all requests
-system.physmem.totBusLat 444124000 # Total cycles spent in databus access
-system.physmem.totBankLat 1445822000 # Total cycles spent in bank access
-system.physmem.avgQLat 14945.75 # Average queueing delay per request
-system.physmem.avgBankLat 13021.79 # Average bank access latency per request
+system.physmem.totQLat 1656369284 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 3548083284 # Sum of mem lat for all requests
+system.physmem.totBusLat 444996000 # Total cycles spent in databus access
+system.physmem.totBankLat 1446718000 # Total cycles spent in bank access
+system.physmem.avgQLat 14888.85 # Average queueing delay per request
+system.physmem.avgBankLat 13004.32 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31967.54 # Average memory access latency
-system.physmem.avgRdBW 3.86 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 3.86 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.60 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31893.17 # Average memory access latency
+system.physmem.avgRdBW 3.87 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3.87 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.61 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 0.18 # Average write queue length over time
-system.physmem.readRowHits 102865 # Number of row buffer hits during reads
-system.physmem.writeRowHits 29619 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 92.65 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 64.15 # Row buffer hit rate for writes
-system.physmem.avgGap 11708274.75 # Average gap between requests
-system.l2c.replacements 337510 # number of replacements
-system.l2c.tagsinuse 65417.862524 # Cycle average of tags in use
-system.l2c.total_refs 2476071 # Total number of references to valid blocks.
-system.l2c.sampled_refs 402672 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.149102 # Average number of references to valid blocks.
+system.physmem.avgWrQLen 0.16 # Average write queue length over time
+system.physmem.readRowHits 103154 # Number of row buffer hits during reads
+system.physmem.writeRowHits 29694 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 92.72 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 64.17 # Row buffer hit rate for writes
+system.physmem.avgGap 11684674.29 # Average gap between requests
+system.l2c.replacements 337448 # number of replacements
+system.l2c.tagsinuse 65419.156627 # Cycle average of tags in use
+system.l2c.total_refs 2475278 # Total number of references to valid blocks.
+system.l2c.sampled_refs 402610 # Sample count of references to valid blocks.
+system.l2c.avg_refs 6.148079 # Average number of references to valid blocks.
system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 54764.758873 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 2313.964866 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2687.926844 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 585.029609 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 664.408286 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst 2261.220547 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data 2140.553499 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.835644 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.035308 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.041015 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.008927 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.010138 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst 0.034503 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.data 0.032662 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.998197 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 513879 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 491618 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 126890 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 82632 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 299640 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 242724 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1757383 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 835771 # number of Writeback hits
-system.l2c.Writeback_hits::total 835771 # number of Writeback hits
+system.l2c.occ_blocks::writebacks 54789.861613 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 2314.148306 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 2668.498131 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 587.791758 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 634.013412 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst 2247.784204 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data 2177.059202 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.836027 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.035311 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.040718 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.008969 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.009674 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst 0.034298 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data 0.033219 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.998217 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 513779 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 490694 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 126874 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 82522 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 299074 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 243605 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1756548 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 835817 # number of Writeback hits
+system.l2c.Writeback_hits::total 835817 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 91841 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 27111 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 67748 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 186700 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 513879 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 583459 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 126890 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 109743 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 299640 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 310472 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1944083 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 513879 # number of overall hits
-system.l2c.overall_hits::cpu0.data 583459 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 126890 # number of overall hits
-system.l2c.overall_hits::cpu1.data 109743 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 299640 # number of overall hits
-system.l2c.overall_hits::cpu2.data 310472 # number of overall hits
-system.l2c.overall_hits::total 1944083 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 7421 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 224850 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 2342 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 23206 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 4624 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 25196 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 287639 # number of ReadReq misses
+system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 91844 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 27079 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 67852 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 186775 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst 513779 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 582538 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 126874 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 109601 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 299074 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 311457 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1943323 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 513779 # number of overall hits
+system.l2c.overall_hits::cpu0.data 582538 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 126874 # number of overall hits
+system.l2c.overall_hits::cpu1.data 109601 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 299074 # number of overall hits
+system.l2c.overall_hits::cpu2.data 311457 # number of overall hits
+system.l2c.overall_hits::total 1943323 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 7414 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 224846 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 2344 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 23166 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 4603 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 25201 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 287574 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 77252 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 21108 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 17439 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 115799 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 7421 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 302102 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 2342 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 44314 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 4624 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 42635 # number of demand (read+write) misses
-system.l2c.demand_misses::total 403438 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 7421 # number of overall misses
-system.l2c.overall_misses::cpu0.data 302102 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 2342 # number of overall misses
-system.l2c.overall_misses::cpu1.data 44314 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 4624 # number of overall misses
-system.l2c.overall_misses::cpu2.data 42635 # number of overall misses
-system.l2c.overall_misses::total 403438 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst 130356500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 1043168500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 266603500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 1103490500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 2543619000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 292500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 292500 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 1001535000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 1445654500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 2447189500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 130356500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 2044703500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 266603500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 2549145000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 4990808500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 130356500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 2044703500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 266603500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 2549145000 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 4990808500 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 521300 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 716468 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 129232 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 105838 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 304264 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 267920 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2045022 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 835771 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 835771 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_misses::cpu2.data 12 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 20 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 76978 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 21120 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 17698 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 115796 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 7414 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 301824 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 2344 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 44286 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 4603 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 42899 # number of demand (read+write) misses
+system.l2c.demand_misses::total 403370 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst 7414 # number of overall misses
+system.l2c.overall_misses::cpu0.data 301824 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 2344 # number of overall misses
+system.l2c.overall_misses::cpu1.data 44286 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 4603 # number of overall misses
+system.l2c.overall_misses::cpu2.data 42899 # number of overall misses
+system.l2c.overall_misses::total 403370 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst 130575500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 1037683000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 271330500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 1103654000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 2543243000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data 365500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 365500 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 1000890500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 1441454500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 2442345000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 130575500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 2038573500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 271330500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 2545108500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 4985588000 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 130575500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 2038573500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 271330500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 2545108500 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 4985588000 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst 521193 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 715540 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 129218 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 105688 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 303677 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 268806 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2044122 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 835817 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 835817 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 169093 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 48219 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 85187 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 302499 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 521300 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 885561 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 129232 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 154057 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 304264 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 353107 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2347521 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 521300 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 885561 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 129232 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 154057 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 304264 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 353107 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2347521 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.014236 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.313831 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.018122 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.219260 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.015197 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.094043 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.140653 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 168822 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 48199 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 85550 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 302571 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst 521193 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 884362 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 129218 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 153887 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 303677 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 354356 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2346693 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 521193 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 884362 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 129218 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 153887 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 303677 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 354356 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2346693 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.014225 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.314233 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.018140 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.219192 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.015158 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.093752 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.140683 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.785714 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.730769 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.456861 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.437753 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.204714 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.382808 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.014236 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.341142 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.018122 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.287647 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.015197 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.120742 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.171857 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.014236 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.341142 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.018122 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.287647 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.015197 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.120742 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.171857 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55660.333049 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 44952.533827 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 57656.466263 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 43796.257342 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 8843.094991 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26590.909091 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 15394.736842 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47448.123934 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82897.786570 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 21133.079733 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 55660.333049 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 46141.253329 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 57656.466263 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 59789.961299 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 12370.695125 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 55660.333049 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 46141.253329 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 57656.466263 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 59789.961299 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 12370.695125 # average overall miss latency
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.750000 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.714286 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.455971 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.438183 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.206873 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.382707 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.014225 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.341290 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.018140 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.287783 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.015158 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.121062 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.171889 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.014225 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.341290 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.018140 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.287783 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.015158 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.121062 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.171889 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55706.271331 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 44793.360960 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 58946.447969 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 43794.055791 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 8843.786295 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 30458.333333 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 18275 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47390.648674 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81447.310431 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 21091.790735 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 55706.271331 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 46032.007858 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 58946.447969 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 59327.921397 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 12359.838362 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 55706.271331 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 46032.007858 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 58946.447969 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 59327.921397 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 12359.838362 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 75358 # number of writebacks
-system.l2c.writebacks::total 75358 # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu1.inst 2342 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 23206 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 4624 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 25196 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 55368 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 21108 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 17439 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 38547 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 2342 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 44314 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 4624 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 42635 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 93915 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 2342 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 44314 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 4624 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 42635 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 93915 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 100735600 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 741824698 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 208189401 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 781867294 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1832616993 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 268008 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 268008 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 729164916 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1230457925 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 1959622841 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 100735600 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 1470989614 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 208189401 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 2012325219 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 3792239834 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 100735600 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 1470989614 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 208189401 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 2012325219 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 3792239834 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 271229500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 318212500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 589442000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 338412000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 391990000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 730402000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 609641500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 710202500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 1319844000 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018122 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.219260 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.094043 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.027075 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.785714 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.423077 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.437753 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.204714 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.127429 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018122 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.287647 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.120742 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.040006 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018122 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.287647 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015197 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.120742 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.040006 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43012.638770 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 31966.935189 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 45023.659386 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 31031.405541 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 33098.847583 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 24364.363636 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 24364.363636 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34544.481524 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70557.825850 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 50837.233533 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43012.638770 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33194.692738 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45023.659386 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 47198.902756 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40379.490326 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43012.638770 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33194.692738 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45023.659386 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 47198.902756 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40379.490326 # average overall mshr miss latency
+system.l2c.writebacks::writebacks 75281 # number of writebacks
+system.l2c.writebacks::total 75281 # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.inst 2344 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 23166 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst 4603 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data 25201 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 55314 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 12 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 21120 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 17698 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 38818 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 2344 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 44286 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 4603 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 42899 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 94132 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 2344 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 44286 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 4603 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 42899 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 94132 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 100921088 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 736853128 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 213196842 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 781711328 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1832682386 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 328508 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 328508 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 728366430 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1222975272 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 1951341702 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 100921088 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 1465219558 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 213196842 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 2004686600 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 3784024088 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 100921088 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 1465219558 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 213196842 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 2004686600 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 3784024088 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269964000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 317506000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 587470000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337351500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 390944000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 728295500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 607315500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 708450000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 1315765500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018140 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.219192 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015158 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.093752 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.027060 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750000 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.438183 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.206873 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.128294 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018140 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.287783 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015158 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.121062 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.040113 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018140 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.287783 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015158 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.121062 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.040113 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43055.071672 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 31807.525166 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 46316.932870 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 31019.059879 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 33132.342373 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27375.666667 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27375.666667 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34487.046875 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69102.456323 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 50268.991241 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43055.071672 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33085.389468 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 46316.932870 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46730.380662 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40199.125568 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43055.071672 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33085.389468 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 46316.932870 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46730.380662 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40199.125568 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.255489 # Cycle average of tags in use
+system.iocache.tagsinuse 1.255760 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1693868794000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.255489 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.078468 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.078468 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 1693868074000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.255760 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.078485 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.078485 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 3943215289 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 3943215289 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 3952393287 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 3952393287 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 3952393287 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 3952393287 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 3948648289 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 3948648289 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 3957826287 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 3957826287 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 3957826287 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 3957826287 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 94898.327132 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 94898.327132 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 94724.824134 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 94724.824134 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 94724.824134 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 94724.824134 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 78884 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 95029.078961 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 95029.078961 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 94855.033841 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 94855.033841 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 94855.033841 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 94855.033841 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 78872 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 9633 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 9708 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.188934 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.124433 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5589000 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3043794338 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 3043794338 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 3049383338 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 3049383338 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 3049383338 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 3049383338 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3049248779 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 3049248779 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 3054837779 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 3054837779 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 3054837779 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 3054837779 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses
system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 81000 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176145.505671 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 176145.505671 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175767.095395 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 175767.095395 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175767.095395 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 175767.095395 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176461.156192 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 176461.156192 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176081.490518 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 176081.490518 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176081.490518 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 176081.490518 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 4863195 # DTB read hits
+system.cpu0.dtb.read_hits 4860289 # DTB read hits
system.cpu0.dtb.read_misses 5912 # DTB read misses
system.cpu0.dtb.read_acv 109 # DTB read access violations
-system.cpu0.dtb.read_accesses 426831 # DTB read accesses
-system.cpu0.dtb.write_hits 3494205 # DTB write hits
-system.cpu0.dtb.write_misses 658 # DTB write misses
+system.cpu0.dtb.read_accesses 426830 # DTB read accesses
+system.cpu0.dtb.write_hits 3490049 # DTB write hits
+system.cpu0.dtb.write_misses 657 # DTB write misses
system.cpu0.dtb.write_acv 81 # DTB write access violations
-system.cpu0.dtb.write_accesses 163149 # DTB write accesses
-system.cpu0.dtb.data_hits 8357400 # DTB hits
-system.cpu0.dtb.data_misses 6570 # DTB misses
+system.cpu0.dtb.write_accesses 163148 # DTB write accesses
+system.cpu0.dtb.data_hits 8350338 # DTB hits
+system.cpu0.dtb.data_misses 6569 # DTB misses
system.cpu0.dtb.data_acv 190 # DTB access violations
-system.cpu0.dtb.data_accesses 589980 # DTB accesses
-system.cpu0.itb.fetch_hits 2736814 # ITB hits
+system.cpu0.dtb.data_accesses 589978 # DTB accesses
+system.cpu0.itb.fetch_hits 2736650 # ITB hits
system.cpu0.itb.fetch_misses 2973 # ITB misses
system.cpu0.itb.fetch_acv 97 # ITB acv
-system.cpu0.itb.fetch_accesses 2739787 # ITB accesses
+system.cpu0.itb.fetch_accesses 2739623 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 928581953 # number of cpu cycles simulated
+system.cpu0.numCycles 928580994 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 32231633 # Number of instructions committed
-system.cpu0.committedOps 32231633 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 30115221 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 167520 # Number of float alu accesses
-system.cpu0.num_func_calls 807051 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4228078 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 30115221 # number of integer instructions
-system.cpu0.num_fp_insts 167520 # number of float instructions
-system.cpu0.num_int_register_reads 41941415 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 22024555 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 86513 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 88077 # number of times the floating registers were written
-system.cpu0.num_mem_refs 8386802 # number of memory refs
-system.cpu0.num_load_insts 4883995 # Number of load instructions
-system.cpu0.num_store_insts 3502807 # Number of store instructions
-system.cpu0.num_idle_cycles 214040611553.999786 # Number of idle cycles
-system.cpu0.num_busy_cycles -213112029600.999786 # Number of busy cycles
-system.cpu0.not_idle_fraction -229.502661 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 230.502661 # Percentage of idle cycles
+system.cpu0.committedInsts 32061485 # Number of instructions committed
+system.cpu0.committedOps 32061485 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 29946926 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 167785 # Number of float alu accesses
+system.cpu0.num_func_calls 806855 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4176537 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 29946926 # number of integer instructions
+system.cpu0.num_fp_insts 167785 # number of float instructions
+system.cpu0.num_int_register_reads 41669823 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 21912533 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 86645 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 88213 # number of times the floating registers were written
+system.cpu0.num_mem_refs 8379762 # number of memory refs
+system.cpu0.num_load_insts 4881104 # Number of load instructions
+system.cpu0.num_store_insts 3498658 # Number of store instructions
+system.cpu0.num_idle_cycles 214035268696.310638 # Number of idle cycles
+system.cpu0.num_busy_cycles -213106687702.310638 # Number of busy cycles
+system.cpu0.not_idle_fraction -229.497146 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 230.497146 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 211372 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 74800 40.97% 40.97% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 211380 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 74799 40.97% 40.97% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 205 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 105685 57.89% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 182566 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 73433 49.30% 49.30% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 182573 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 73432 49.30% 49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 205 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 148947 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1818611622000 98.75% 98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 39272500 0.00% 98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 363381500 0.02% 98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 22666637000 1.23% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1841680913000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::total 148948 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1818622166500 98.75% 98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 39746000 0.00% 98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 363817000 0.02% 98.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 22660629500 1.23% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1841686359000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.694829 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.815853 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 175309 91.20% 93.41% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 175314 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
+system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 192221 # number of callpals executed
+system.cpu0.kern.callpal::total 192228 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1736 # number of protection mode switches
-system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1905
-system.cpu0.kern.mode_good::user 1736
-system.cpu0.kern.mode_good::idle 169
-system.cpu0.kern.mode_switch_good::kernel 0.321682 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
+system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches
+system.cpu0.kern.mode_good::kernel 1908
+system.cpu0.kern.mode_good::user 1738
+system.cpu0.kern.mode_good::idle 170
+system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.390689 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 29776947000 1.62% 1.62% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2543344500 0.14% 1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle 1809360618000 98.25% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 4176 # number of times the context was actually changed
+system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 29768907500 1.62% 1.62% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2544697000 0.14% 1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle 1809372751000 98.25% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 4177 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 954146 # number of replacements
-system.cpu0.icache.tagsinuse 511.198138 # Cycle average of tags in use
-system.cpu0.icache.total_refs 41733941 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 954657 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 43.716163 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 10235539000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 257.559886 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 79.204756 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu2.inst 174.433495 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.503047 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu1.inst 0.154697 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu2.inst 0.340690 # Average percentage of cache occupancy
+system.cpu0.icache.replacements 953436 # number of replacements
+system.cpu0.icache.tagsinuse 511.198067 # Cycle average of tags in use
+system.cpu0.icache.total_refs 41560742 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 953947 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 43.567139 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 10234504000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 256.477356 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst 79.519770 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu2.inst 175.200941 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.500932 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst 0.155312 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu2.inst 0.342189 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.998434 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 31717072 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 7719142 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 2297727 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 41733941 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 31717072 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 7719142 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 2297727 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 41733941 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 31717072 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 7719142 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 2297727 # number of overall hits
-system.cpu0.icache.overall_hits::total 41733941 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 521321 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 129232 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 321175 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 971728 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 521321 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 129232 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 321175 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 971728 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 521321 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 129232 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 321175 # number of overall misses
-system.cpu0.icache.overall_misses::total 971728 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1794278000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4429709988 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 6223987988 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 1794278000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 4429709988 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 6223987988 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 1794278000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 4429709988 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 6223987988 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 32238393 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 7848374 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 2618902 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 42705669 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 32238393 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 7848374 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 2618902 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 42705669 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 32238393 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 7848374 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 2618902 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 42705669 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016171 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016466 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122637 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.022754 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016171 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016466 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122637 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.022754 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016171 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016466 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122637 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.022754 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13884.161818 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13792.200476 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 6405.072189 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13884.161818 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13792.200476 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 6405.072189 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13884.161818 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13792.200476 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 6405.072189 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 1920 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 179 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 117 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.410256 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 179 # average number of cycles each access was blocked
+system.cpu0.icache.ReadReq_hits::cpu0.inst 31547031 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 7721485 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 2292226 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 41560742 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 31547031 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 7721485 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 2292226 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 41560742 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 31547031 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 7721485 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 2292226 # number of overall hits
+system.cpu0.icache.overall_hits::total 41560742 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 521213 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 129218 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 320460 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 970891 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 521213 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 129218 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 320460 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 970891 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 521213 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 129218 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 320460 # number of overall misses
+system.cpu0.icache.overall_misses::total 970891 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1794259500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4426264489 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 6220523989 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 1794259500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 4426264489 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 6220523989 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 1794259500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 4426264489 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 6220523989 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 32068244 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 7850703 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 2612686 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 42531633 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 32068244 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 7850703 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 2612686 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 42531633 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 32068244 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 7850703 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 2612686 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 42531633 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016253 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016459 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122655 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.022828 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016253 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016459 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122655 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.022828 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016253 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016459 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122655 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.022828 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13885.522915 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.221460 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 6407.026112 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13885.522915 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.221460 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 6407.026112 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13885.522915 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.221460 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 6407.026112 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 1940 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 125 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.520000 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16896 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 16896 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 16896 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 16896 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 16896 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 16896 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129232 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 304279 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 433511 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 129232 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 304279 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 433511 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 129232 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 304279 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 433511 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1535814000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3651354490 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 5187168490 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1535814000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3651354490 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 5187168490 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1535814000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3651354490 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 5187168490 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016466 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116186 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010151 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016466 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116186 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.010151 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016466 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116186 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.010151 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11884.161818 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12000.021329 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11965.482975 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11884.161818 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12000.021329 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11965.482975 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11884.161818 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12000.021329 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11965.482975 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16767 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 16767 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst 16767 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 16767 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst 16767 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 16767 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129218 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303693 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 432911 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 129218 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 303693 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 432911 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 129218 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 303693 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 432911 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1535823500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3649123991 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 5184947491 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1535823500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3649123991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 5184947491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1535823500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3649123991 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 5184947491 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016459 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116238 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010179 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016459 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116238 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.010179 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016459 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116238 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.010179 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11885.522915 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12015.831748 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11976.936347 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11885.522915 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12015.831748 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11976.936347 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11885.522915 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12015.831748 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11976.936347 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1392176 # number of replacements
+system.cpu0.dcache.replacements 1392058 # number of replacements
system.cpu0.dcache.tagsinuse 511.997817 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13319375 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 1392688 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 9.563790 # Average number of references to valid blocks.
+system.cpu0.dcache.total_refs 13312306 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 1392570 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 9.559524 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 250.475263 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu1.data 85.370425 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu2.data 176.152129 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.489209 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu1.data 0.166739 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu2.data 0.344047 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::cpu0.data 249.308176 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data 86.874382 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu2.data 175.815259 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.486930 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data 0.169677 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu2.data 0.343389 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 4041121 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 1096850 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 2424578 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7562549 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3198610 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 859334 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 1312800 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5370744 # number of WriteReq hits
+system.cpu0.dcache.ReadReq_hits::cpu0.data 4039145 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 1097317 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 2422916 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7559378 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3194729 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 858607 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 1315997 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 5369333 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116325 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19408 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 49694 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 185427 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125372 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21487 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data 53741 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 200600 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 7239731 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 1956184 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 3737378 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12933293 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 7239731 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 1956184 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 3737378 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12933293 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 706861 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 103630 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 548850 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1359341 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 169104 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 48220 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 560755 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 778079 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9607 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2208 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7000 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 18815 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 875965 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 151850 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 1109605 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2137420 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 875965 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 151850 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 1109605 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2137420 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2161032000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9421132500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 11582164500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1417971000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 15685694174 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 17103665174 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29185500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 103516500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 132702000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 3579003000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 25106826674 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 28685829674 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 3579003000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 25106826674 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 28685829674 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 4747982 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 1200480 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 2973428 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8921890 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 3367714 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 907554 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 1873555 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 6148823 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125932 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21616 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 56694 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 204242 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125372 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21487 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 53742 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 200601 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 8115696 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 2108034 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 4846983 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 15070713 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 8115696 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 2108034 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 4846983 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 15070713 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148876 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086324 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184585 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.152360 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050213 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053132 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.299300 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.126541 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076287 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102147 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.123470 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092121 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107935 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.072034 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.228927 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.141826 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107935 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.072034 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.228927 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.141826 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20853.343626 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17165.222738 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 8520.426074 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29406.283700 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27972.455304 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 21981.913371 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13218.070652 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14788.071429 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7052.989636 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19416 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48495 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 184236 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125365 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21489 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52431 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 199285 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 7233874 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 1955924 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 3738913 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 12928711 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 7233874 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 1955924 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 3738913 # number of overall hits
+system.cpu0.dcache.overall_hits::total 12928711 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 705940 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 103484 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 550231 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1359655 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 168833 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 48200 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 562641 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 779674 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9600 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2204 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7141 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 18945 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 874773 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 151684 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 1112872 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 2139329 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 874773 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 151684 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 1112872 # number of overall misses
+system.cpu0.dcache.overall_misses::total 2139329 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2154110500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9456795000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 11610905500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1416943000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 15644055577 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 17060998577 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29039000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 106906000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 135945000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 3571053500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 25100850577 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 28671904077 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 3571053500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 25100850577 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 28671904077 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 4745085 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 1200801 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 2973147 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8919033 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 3363562 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 906807 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 1878638 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 6149007 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125925 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21620 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55636 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 203181 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125365 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21489 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52433 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 199287 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 8108647 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 2107608 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 4851785 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 15068040 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 8108647 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 2107608 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 4851785 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 15068040 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148773 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086179 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.185067 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.152444 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050195 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053154 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.299494 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.126797 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076236 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101943 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.128352 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093242 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000038 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107881 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.071970 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229374 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.141978 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107881 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.071970 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229374 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.141978 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20815.879750 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17186.954207 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 8539.596809 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29397.157676 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27804.684651 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 21882.220745 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13175.589837 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14970.732390 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7175.771971 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23569.331577 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22626.814654 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13420.773490 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23569.331577 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22626.814654 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13420.773490 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 505614 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 672 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 16873 # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23542.717096 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22555.020323 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13402.288324 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23542.717096 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22555.020323 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13402.288324 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 496552 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 580 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 17061 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.965863 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 96 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.104507 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 82.857143 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 835771 # number of writebacks
-system.cpu0.dcache.writebacks::total 835771 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 286220 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 286220 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 475804 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 475804 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1462 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1462 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 762024 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 762024 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 762024 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 762024 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 103630 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 262630 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 366260 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48220 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 84951 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 133171 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2208 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5538 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7746 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 151850 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 347581 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 499431 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 151850 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 347581 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 499431 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1953772000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4295599000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6249371000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321531000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2301660126 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3623191126 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24769500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70346000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95115500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3275303000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6597259126 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 9872562126 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3275303000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6597259126 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 9872562126 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 289521000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 340019500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629540500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 358537000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 415967500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 774504500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 648058000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 755987000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1404045000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086324 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088326 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041052 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053132 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045342 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021658 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102147 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.097682 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037926 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072034 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071711 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.033139 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072034 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071711 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.033139 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18853.343626 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16356.086510 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17062.663135 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27406.283700 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27093.973302 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27207.058038 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11218.070652 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12702.419646 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12279.305448 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 835817 # number of writebacks
+system.cpu0.dcache.writebacks::total 835817 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 286842 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 286842 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 477332 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 477332 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1469 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1469 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 764174 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 764174 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 764174 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 764174 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 103484 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 263389 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 366873 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48200 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85309 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 133509 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2204 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5672 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7876 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 151684 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 348698 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 500382 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 151684 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 348698 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 500382 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1947142500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4307606000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6254748500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1320543000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2299251630 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3619794630 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24631000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72250500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96881500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3267685500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6606857630 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 9874543130 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3267685500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6606857630 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 9874543130 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 288177500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 339273500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 627451000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357416500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 414861500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 772278000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645594000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 754135000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1399729000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086179 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088589 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041134 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053154 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045410 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021712 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101943 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101948 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038763 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000038 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071970 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071870 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.033208 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071970 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071870 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.033208 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18815.879750 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16354.540243 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17048.811169 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27397.157676 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26952.040582 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27112.738692 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.589837 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12738.099436 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12300.850686 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21569.331577 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18980.494118 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19767.619803 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21569.331577 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18980.494118 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19767.619803 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21542.717096 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18947.219743 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19734.009477 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21542.717096 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18947.219743 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19734.009477 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1219761 # DTB read hits
+system.cpu1.dtb.read_hits 1220100 # DTB read hits
system.cpu1.dtb.read_misses 1488 # DTB read misses
system.cpu1.dtb.read_acv 40 # DTB read access violations
system.cpu1.dtb.read_accesses 143779 # DTB read accesses
-system.cpu1.dtb.write_hits 929431 # DTB write hits
+system.cpu1.dtb.write_hits 928690 # DTB write hits
system.cpu1.dtb.write_misses 201 # DTB write misses
system.cpu1.dtb.write_acv 24 # DTB write access violations
system.cpu1.dtb.write_accesses 59743 # DTB write accesses
-system.cpu1.dtb.data_hits 2149192 # DTB hits
+system.cpu1.dtb.data_hits 2148790 # DTB hits
system.cpu1.dtb.data_misses 1689 # DTB misses
system.cpu1.dtb.data_acv 64 # DTB access violations
system.cpu1.dtb.data_accesses 203522 # DTB accesses
-system.cpu1.itb.fetch_hits 873235 # ITB hits
+system.cpu1.itb.fetch_hits 872643 # ITB hits
system.cpu1.itb.fetch_misses 756 # ITB misses
system.cpu1.itb.fetch_acv 43 # ITB acv
-system.cpu1.itb.fetch_accesses 873991 # ITB accesses
+system.cpu1.itb.fetch_accesses 873399 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 953535739 # number of cpu cycles simulated
+system.cpu1.numCycles 953546573 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7846620 # Number of instructions committed
-system.cpu1.committedOps 7846620 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 7299077 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 45739 # Number of float alu accesses
-system.cpu1.num_func_calls 212215 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 957639 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 7299077 # number of integer instructions
-system.cpu1.num_fp_insts 45739 # number of float instructions
-system.cpu1.num_int_register_reads 10142741 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5309758 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 24689 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 24953 # number of times the floating registers were written
-system.cpu1.num_mem_refs 2156913 # number of memory refs
-system.cpu1.num_load_insts 1225031 # Number of load instructions
-system.cpu1.num_store_insts 931882 # Number of store instructions
-system.cpu1.num_idle_cycles -1658749274.077502 # Number of idle cycles
-system.cpu1.num_busy_cycles 2612285013.077502 # Number of busy cycles
-system.cpu1.not_idle_fraction 2.739577 # Percentage of non-idle cycles
-system.cpu1.idle_fraction -1.739577 # Percentage of idle cycles
+system.cpu1.committedInsts 7848949 # Number of instructions committed
+system.cpu1.committedOps 7848949 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 7301756 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 45390 # Number of float alu accesses
+system.cpu1.num_func_calls 212250 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 958041 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 7301756 # number of integer instructions
+system.cpu1.num_fp_insts 45390 # number of float instructions
+system.cpu1.num_int_register_reads 10145726 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5312805 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 24524 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 24770 # number of times the floating registers were written
+system.cpu1.num_mem_refs 2156479 # number of memory refs
+system.cpu1.num_load_insts 1225350 # Number of load instructions
+system.cpu1.num_store_insts 931129 # Number of store instructions
+system.cpu1.num_idle_cycles -1690648572.086683 # Number of idle cycles
+system.cpu1.num_busy_cycles 2644195145.086683 # Number of busy cycles
+system.cpu1.not_idle_fraction 2.773011 # Percentage of non-idle cycles
+system.cpu1.idle_fraction -1.773011 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 3234016 # DTB read hits
-system.cpu2.dtb.read_misses 12170 # DTB read misses
-system.cpu2.dtb.read_acv 136 # DTB read access violations
-system.cpu2.dtb.read_accesses 218383 # DTB read accesses
-system.cpu2.dtb.write_hits 2000862 # DTB write hits
-system.cpu2.dtb.write_misses 2630 # DTB write misses
-system.cpu2.dtb.write_acv 139 # DTB write access violations
-system.cpu2.dtb.write_accesses 81465 # DTB write accesses
-system.cpu2.dtb.data_hits 5234878 # DTB hits
-system.cpu2.dtb.data_misses 14800 # DTB misses
-system.cpu2.dtb.data_acv 275 # DTB access violations
-system.cpu2.dtb.data_accesses 299848 # DTB accesses
-system.cpu2.itb.fetch_hits 374542 # ITB hits
-system.cpu2.itb.fetch_misses 5731 # ITB misses
-system.cpu2.itb.fetch_acv 284 # ITB acv
-system.cpu2.itb.fetch_accesses 380273 # ITB accesses
+system.cpu2.dtb.read_hits 3233315 # DTB read hits
+system.cpu2.dtb.read_misses 12189 # DTB read misses
+system.cpu2.dtb.read_acv 135 # DTB read access violations
+system.cpu2.dtb.read_accesses 219207 # DTB read accesses
+system.cpu2.dtb.write_hits 2006633 # DTB write hits
+system.cpu2.dtb.write_misses 2635 # DTB write misses
+system.cpu2.dtb.write_acv 145 # DTB write access violations
+system.cpu2.dtb.write_accesses 81760 # DTB write accesses
+system.cpu2.dtb.data_hits 5239948 # DTB hits
+system.cpu2.dtb.data_misses 14824 # DTB misses
+system.cpu2.dtb.data_acv 280 # DTB access violations
+system.cpu2.dtb.data_accesses 300967 # DTB accesses
+system.cpu2.itb.fetch_hits 374893 # ITB hits
+system.cpu2.itb.fetch_misses 5781 # ITB misses
+system.cpu2.itb.fetch_acv 261 # ITB acv
+system.cpu2.itb.fetch_accesses 380674 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.numCycles 30548805 # number of cpu cycles simulated
+system.cpu2.numCycles 30553382 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 8364028 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 7669410 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 129868 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 6711241 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 5709819 # Number of BTB hits
+system.cpu2.BPredUnit.lookups 8367198 # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted 7675066 # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect 129021 # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups 6898028 # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits 5713360 # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 287796 # Number of times the RAS was used to get a target.
-system.cpu2.BPredUnit.RASInCorrect 15290 # Number of incorrect RAS predictions.
-system.cpu2.fetch.icacheStallCycles 8565342 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 34820498 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 8364028 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 5997615 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 8085140 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 623390 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 9684769 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 10169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 1946 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 65267 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 78430 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 219 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2618903 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 90402 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 26897224 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.294576 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.310232 # Number of instructions fetched each cycle (Total)
+system.cpu2.BPredUnit.usedRAS 286292 # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.RASInCorrect 15213 # Number of incorrect RAS predictions.
+system.cpu2.fetch.icacheStallCycles 8548806 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 34839646 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 8367198 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 5999652 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 8085881 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 623525 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 9702754 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 9910 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 1956 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 78066 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 227 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 2612689 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 89635 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 26899441 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.295181 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.310992 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 18812084 69.94% 69.94% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 275091 1.02% 70.96% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 443313 1.65% 72.61% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 4200168 15.62% 88.23% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 736557 2.74% 90.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 167312 0.62% 91.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 197037 0.73% 92.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 432029 1.61% 93.93% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1633633 6.07% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 18813560 69.94% 69.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 273460 1.02% 70.96% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 442537 1.65% 72.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 4198605 15.61% 88.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 738968 2.75% 90.96% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 167733 0.62% 91.58% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 196064 0.73% 92.31% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 433736 1.61% 93.92% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1634778 6.08% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 26897224 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.273792 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.139832 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8682356 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 9793254 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 7488405 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 293704 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 393556 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 170875 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 13042 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 34420320 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 40663 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 393556 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 9037496 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 2819097 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 5808677 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 7346220 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1246237 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 33260279 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2326 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 233903 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 407997 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 22331754 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 41424509 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 41259136 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 165373 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 20496437 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 1835317 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 510420 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 61593 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3691952 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 3399315 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 2093436 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 371907 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 254715 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 30727225 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 632539 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 30272118 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 35753 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2189784 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 1100567 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 445757 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 26897224 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.125474 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.564893 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 26899441 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.273855 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.140288 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 8679846 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 9796545 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 7488897 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 294076 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 394122 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 169250 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 12966 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 34438242 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 40605 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 394122 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 9036155 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 2833856 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 5793548 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 7343930 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1251886 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 33280862 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 235752 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 410323 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 22341851 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 41449381 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 41284168 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 165213 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 20505105 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 1836746 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 509428 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 60335 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3708993 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 3395949 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 2096293 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 374269 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 256431 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 30745321 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 631973 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 30290863 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 30934 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 2196077 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 1091992 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 446408 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 26899441 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.126078 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.565187 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 15350394 57.07% 57.07% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3115885 11.58% 68.65% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 1557090 5.79% 74.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 5021564 18.67% 93.11% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 911830 3.39% 96.50% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 491728 1.83% 98.33% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 288005 1.07% 99.40% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 142453 0.53% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 18275 0.07% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 15349062 57.06% 57.06% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3113388 11.57% 68.64% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 1556519 5.79% 74.42% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 5024470 18.68% 93.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 916558 3.41% 96.51% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 490691 1.82% 98.33% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 288280 1.07% 99.40% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 142124 0.53% 99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 18349 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 26897224 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 26899441 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 35285 14.01% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 113269 44.96% 58.96% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 103382 41.04% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 35139 13.92% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 113314 44.90% 58.82% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 103925 41.18% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 24555706 81.12% 81.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 20320 0.07% 81.19% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 24571272 81.12% 81.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 20288 0.07% 81.19% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 8506 0.03% 81.22% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 8510 0.03% 81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.22% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 3366886 11.12% 92.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 2024055 6.69% 99.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 292961 0.97% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 3364677 11.11% 92.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 2029119 6.70% 99.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 293313 0.97% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 30272118 # Type of FU issued
-system.cpu2.iq.rate 0.990943 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 251936 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.008322 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 87492046 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 33437480 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 29866501 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 237103 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 115982 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 112325 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 30398156 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 123442 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 190063 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 30290863 # Type of FU issued
+system.cpu2.iq.rate 0.991408 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 252378 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.008332 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 87527172 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 33461701 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 29889528 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 237307 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 115799 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 112442 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 30417117 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 123668 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 190380 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 422258 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 952 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 4004 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 162752 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 417328 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 909 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4219 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 161835 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 4980 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 23112 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5028 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 23504 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 393556 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 2038103 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 212197 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32647760 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 228888 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 3399315 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 2093436 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 561709 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 150503 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2400 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 4004 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 66845 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 130356 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 197201 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 30107405 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 3254707 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 164713 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 394122 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 2048539 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 212384 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32667767 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 225947 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 3395949 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 2096293 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 561038 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 149803 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2446 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4219 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 66256 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 130204 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 196460 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 30129770 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 3254028 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 161093 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 1287996 # number of nop insts executed
-system.cpu2.iew.exec_refs 5262746 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 6765344 # Number of branches executed
-system.cpu2.iew.exec_stores 2008039 # Number of stores executed
-system.cpu2.iew.exec_rate 0.985551 # Inst execution rate
-system.cpu2.iew.wb_sent 30012235 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 29978826 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 17295143 # num instructions producing a value
-system.cpu2.iew.wb_consumers 20538847 # num instructions consuming a value
+system.cpu2.iew.exec_nop 1290473 # number of nop insts executed
+system.cpu2.iew.exec_refs 5267847 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 6767321 # Number of branches executed
+system.cpu2.iew.exec_stores 2013819 # Number of stores executed
+system.cpu2.iew.exec_rate 0.986135 # Inst execution rate
+system.cpu2.iew.wb_sent 30034994 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 30001970 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 17305763 # num instructions producing a value
+system.cpu2.iew.wb_consumers 20552521 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.981342 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.842070 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.981953 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.842026 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 2374409 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 186782 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 183048 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 26503668 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.140514 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.850633 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 2377399 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 185565 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 182360 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 26505319 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.141095 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.851284 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 16405527 61.90% 61.90% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 2337415 8.82% 70.72% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1218938 4.60% 75.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 4753611 17.94% 93.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 502619 1.90% 95.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 186793 0.70% 95.85% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 180491 0.68% 96.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 181897 0.69% 97.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 736377 2.78% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 16405167 61.89% 61.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 2334119 8.81% 70.70% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1221930 4.61% 75.31% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 4753276 17.93% 93.24% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 503631 1.90% 95.14% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 187421 0.71% 95.85% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 180293 0.68% 96.53% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 181960 0.69% 97.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 737522 2.78% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 26503668 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 30227806 # Number of instructions committed
-system.cpu2.commit.committedOps 30227806 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 26505319 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 30245090 # Number of instructions committed
+system.cpu2.commit.committedOps 30245090 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 4907741 # Number of memory references committed
-system.cpu2.commit.loads 2977057 # Number of loads committed
-system.cpu2.commit.membars 65125 # Number of memory barriers committed
-system.cpu2.commit.branches 6615814 # Number of branches committed
-system.cpu2.commit.fp_insts 111064 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 28762873 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 231817 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 736377 # number cycles where commit BW limit reached
+system.cpu2.commit.refs 4913079 # Number of memory references committed
+system.cpu2.commit.loads 2978621 # Number of loads committed
+system.cpu2.commit.membars 65145 # Number of memory barriers committed
+system.cpu2.commit.branches 6616794 # Number of branches committed
+system.cpu2.commit.fp_insts 111215 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 28779164 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 231926 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 737522 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 58294713 # The number of ROB reads
-system.cpu2.rob.rob_writes 65597739 # The number of ROB writes
-system.cpu2.timesIdled 244101 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 3651581 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 1745276463 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 29049036 # Number of Instructions Simulated
-system.cpu2.committedOps 29049036 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 29049036 # Number of Instructions Simulated
-system.cpu2.cpi 1.051629 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.051629 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.950906 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.950906 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 39585060 # number of integer regfile reads
-system.cpu2.int_regfile_writes 21198431 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 68487 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 68830 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 4557721 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 264115 # number of misc regfile writes
+system.cpu2.rob.rob_reads 58315466 # The number of ROB reads
+system.cpu2.rob.rob_writes 65639010 # The number of ROB writes
+system.cpu2.timesIdled 244602 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 3653941 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 1745271968 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 29064360 # Number of Instructions Simulated
+system.cpu2.committedOps 29064360 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 29064360 # Number of Instructions Simulated
+system.cpu2.cpi 1.051232 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.051232 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.951265 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.951265 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 39620111 # number of integer regfile reads
+system.cpu2.int_regfile_writes 21211926 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 68528 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 68903 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 4553685 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 261693 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.523518 # Number of seconds simulated
-sim_ticks 2523517846500 # Number of ticks simulated
-final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.523205 # Number of seconds simulated
+sim_ticks 2523204701000 # Number of ticks simulated
+final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 18924 # Simulator instruction rate (inst/s)
-host_op_rate 24341 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 788054860 # Simulator tick rate (ticks/s)
-host_mem_usage 403628 # Number of bytes of host memory used
-host_seconds 3202.21 # Real time elapsed on the host
-sim_insts 60597240 # Number of instructions simulated
-sim_ops 77945362 # Number of ops (including micro ops) simulated
+host_inst_rate 55288 # Simulator instruction rate (inst/s)
+host_op_rate 71140 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2313219719 # Simulator tick rate (ticks/s)
+host_mem_usage 409988 # Number of bytes of host memory used
+host_seconds 1090.78 # Real time elapsed on the host
+sim_insts 60306320 # Number of instructions simulated
+sim_ops 77597310 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096842 # Total number of read requests seen
-system.physmem.writeReqs 813129 # Total number of write requests seen
-system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966197888 # Total number of bytes read from memory
-system.physmem.bytesWritten 52040256 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis
+system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096856 # Total number of read requests seen
+system.physmem.writeReqs 813138 # Total number of write requests seen
+system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966198784 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040832 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2523516727500 # Total gap between requests
+system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2523203522000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154598 # Categorize read packet sizes
+system.physmem.readPktSize::6 154612 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1937150 # categorize write packet sizes
+system.physmem.writePktSize::2 1943854 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59111 # categorize write packet sizes
+system.physmem.writePktSize::6 59120 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests
-system.physmem.totBusLat 60385948000 # Total cycles spent in databus access
-system.physmem.totBankLat 16343502000 # Total cycles spent in bank access
-system.physmem.avgQLat 21736.41 # Average queueing delay per request
-system.physmem.avgBankLat 1082.60 # Average bank access latency per request
+system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests
+system.physmem.totBusLat 60386192000 # Total cycles spent in databus access
+system.physmem.totBankLat 16356620000 # Total cycles spent in bank access
+system.physmem.avgQLat 21743.10 # Average queueing delay per request
+system.physmem.avgBankLat 1083.47 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26819.01 # Average memory access latency
-system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26826.57 # Average memory access latency
+system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.52 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.16 # Average read queue length over time
-system.physmem.avgWrQLen 11.85 # Average write queue length over time
-system.physmem.readRowHits 15052691 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784814 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 10.68 # Average write queue length over time
+system.physmem.readRowHits 15052450 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784654 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes
-system.physmem.avgGap 158612.28 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes
+system.physmem.avgGap 158592.36 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15048937 # DTB read hits
-system.cpu.checker.dtb.read_misses 7310 # DTB read misses
-system.cpu.checker.dtb.write_hits 11294198 # DTB write hits
+system.cpu.checker.dtb.read_hits 14986991 # DTB read hits
+system.cpu.checker.dtb.read_misses 7307 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227488 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15056247 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11296387 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994298 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229677 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26343135 # DTB hits
-system.cpu.checker.dtb.misses 9499 # DTB misses
-system.cpu.checker.dtb.accesses 26352634 # DTB accesses
-system.cpu.checker.itb.inst_hits 61775993 # ITB inst hits
+system.cpu.checker.dtb.hits 26214479 # DTB hits
+system.cpu.checker.dtb.misses 9496 # DTB misses
+system.cpu.checker.dtb.accesses 26223975 # DTB accesses
+system.cpu.checker.itb.inst_hits 61480313 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61780464 # ITB inst accesses
-system.cpu.checker.itb.hits 61775993 # DTB hits
+system.cpu.checker.itb.inst_accesses 61484784 # ITB inst accesses
+system.cpu.checker.itb.hits 61480313 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61780464 # DTB accesses
-system.cpu.checker.numCycles 78235922 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61484784 # DTB accesses
+system.cpu.checker.numCycles 77883110 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51295505 # DTB read hits
-system.cpu.dtb.read_misses 73548 # DTB read misses
-system.cpu.dtb.write_hits 11769416 # DTB write hits
-system.cpu.dtb.write_misses 17308 # DTB write misses
+system.cpu.dtb.read_hits 51212683 # DTB read hits
+system.cpu.dtb.read_misses 73387 # DTB read misses
+system.cpu.dtb.write_hits 11701466 # DTB write hits
+system.cpu.dtb.write_misses 17011 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7698 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 7759 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51369053 # DTB read accesses
-system.cpu.dtb.write_accesses 11786724 # DTB write accesses
+system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51286070 # DTB read accesses
+system.cpu.dtb.write_accesses 11718477 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63064921 # DTB hits
-system.cpu.dtb.misses 90856 # DTB misses
-system.cpu.dtb.accesses 63155777 # DTB accesses
-system.cpu.itb.inst_hits 11599470 # ITB inst hits
-system.cpu.itb.inst_misses 11387 # ITB inst misses
+system.cpu.dtb.hits 62914149 # DTB hits
+system.cpu.dtb.misses 90398 # DTB misses
+system.cpu.dtb.accesses 63004547 # DTB accesses
+system.cpu.itb.inst_hits 11530598 # ITB inst hits
+system.cpu.itb.inst_misses 11503 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5136 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5166 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11610857 # ITB inst accesses
-system.cpu.itb.hits 11599470 # DTB hits
-system.cpu.itb.misses 11387 # DTB misses
-system.cpu.itb.accesses 11610857 # DTB accesses
-system.cpu.numCycles 470965317 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11542101 # ITB inst accesses
+system.cpu.itb.hits 11530598 # DTB hits
+system.cpu.itb.misses 11503 # DTB misses
+system.cpu.itb.accesses 11542101 # DTB accesses
+system.cpu.numCycles 469830472 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued
-system.cpu.iq.rate 0.262043 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued
+system.cpu.iq.rate 0.261848 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 221628 # number of nop insts executed
-system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11537560 # Number of branches executed
-system.cpu.iew.exec_stores 12281337 # Number of stores executed
-system.cpu.iew.exec_rate 0.257635 # Inst execution rate
-system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47183541 # num instructions producing a value
-system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value
+system.cpu.iew.exec_nop 221038 # number of nop insts executed
+system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11477980 # Number of branches executed
+system.cpu.iew.exec_stores 12213052 # Number of stores executed
+system.cpu.iew.exec_rate 0.257448 # Inst execution rate
+system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47051195 # num instructions producing a value
+system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60747621 # Number of instructions committed
-system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60456701 # Number of instructions committed
+system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27514551 # Number of memory references committed
-system.cpu.commit.loads 15716032 # Number of loads committed
-system.cpu.commit.membars 413105 # Number of memory barriers committed
-system.cpu.commit.branches 10023101 # Number of branches committed
+system.cpu.commit.refs 27385892 # Number of memory references committed
+system.cpu.commit.loads 15654083 # Number of loads committed
+system.cpu.commit.membars 403583 # Number of memory barriers committed
+system.cpu.commit.branches 9961154 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69134175 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995982 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68853054 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991222 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 239713879 # The number of ROB reads
-system.cpu.rob.rob_writes 197204165 # The number of ROB writes
-system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60597240 # Number of Instructions Simulated
-system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated
-system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 549724993 # number of integer regfile reads
-system.cpu.int_regfile_writes 88045460 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8276 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2926 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912900 # number of misc regfile writes
-system.cpu.icache.replacements 981280 # number of replacements
-system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use
-system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 10533801 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10533801 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10533801 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10533801 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10533801 # number of overall hits
-system.cpu.icache.overall_hits::total 10533801 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1061888 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1061888 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1061888 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1061888 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1061888 # number of overall misses
-system.cpu.icache.overall_misses::total 1061888 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13967491489 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13967491489 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13967491489 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 13967491489 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 13967491489 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 13967491489 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11595689 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11595689 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11595689 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11595689 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11595689 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11595689 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091576 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 5396 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 1220 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 17.808581 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 610 # average number of cycles each access was blocked
+system.cpu.rob.rob_reads 238273902 # The number of ROB reads
+system.cpu.rob.rob_writes 196332947 # The number of ROB writes
+system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60306320 # Number of Instructions Simulated
+system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated
+system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 547824488 # number of integer regfile reads
+system.cpu.int_regfile_writes 87698032 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8340 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2902 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads
+system.cpu.misc_regfile_writes 831851 # number of misc regfile writes
+system.cpu.icache.replacements 979772 # number of replacements
+system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use
+system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits
+system.cpu.icache.overall_hits::total 10466836 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses
+system.cpu.icache.overall_misses::total 1059904 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 80057 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 80057 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 80057 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 80057 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 80057 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981831 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 981831 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 981831 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 981831 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 981831 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 981831 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11353310491 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11353310491 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11353310491 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11353310491 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11353310491 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11353310491 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 980321 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 980321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 980321 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 980321 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 980321 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11335281493 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11335281493 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11335281493 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11335281493 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11335281493 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11335281493 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084672 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.084672 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.084672 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.406015 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.406015 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085048 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.085048 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.085048 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.826353 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.826353 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 64370 # number of replacements
-system.cpu.l2cache.tagsinuse 51358.666800 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1910788 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 129761 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 14.725441 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2488452468500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 36927.008868 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 28.274765 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 8177.411143 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6225.971675 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.563461 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000431 # Average percentage of cache occupancy
+system.cpu.l2cache.replacements 64384 # number of replacements
+system.cpu.l2cache.tagsinuse 51365.557849 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1909698 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 129778 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 14.715114 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2488155004000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 36926.744718 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 36.464010 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003926 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 8168.761699 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6233.583496 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.563457 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000556 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.124777 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.095001 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.783671 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 78622 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10599 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 968211 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 387222 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1444654 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112968 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112968 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 78622 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 10599 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 968211 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 500190 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1557622 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 78622 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 10599 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 968211 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 500190 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1557622 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 12367 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 10717 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 12367 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143903 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 12367 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143903 # number of overall misses
-system.cpu.l2cache.overall_misses::total 156313 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2982500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 653684500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590050498 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1246835498 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 431500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6675201498 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6675201498 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2982500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 653684500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7265251996 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 7922036996 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2982500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 653684500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7265251996 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 7922036996 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 78663 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10601 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 980578 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 397939 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1467781 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.occ_percent::cpu.inst 0.124645 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.095117 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.783776 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 78725 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10899 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 966625 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 387064 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1443313 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607596 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607596 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 78725 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10899 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 966625 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 499971 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1556220 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 78725 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10899 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 966625 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 499971 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1556220 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12362 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133204 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133204 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 12362 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143927 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156343 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 12362 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143927 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156343 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3708000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 187000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 653051500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 588973999 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1245920499 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 478500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6665784498 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6665784498 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3708000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 187000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 653051500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7254758497 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 7911704997 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3708000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 187000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 653051500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7254758497 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 7911704997 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 78776 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10902 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 978987 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 397787 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1466452 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607596 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607596 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 246154 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 246154 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 78663 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 10601 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 980578 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 644093 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1713935 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 78663 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 10601 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 980578 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 644093 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1713935 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000521 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026931 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.015756 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986158 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986158 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541068 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.541068 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000521 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.223420 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.091201 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000521 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.223420 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.091201 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72743.902439 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52857.160184 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55057.431931 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 53912.548017 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 147.723382 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 147.723382 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50119.393164 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50119.393164 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 50680.602356 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 50680.602356 # average overall miss latency
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246111 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246111 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 78776 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10902 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 978987 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 643898 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1712563 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 78776 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10902 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 978987 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 643898 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1712563 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000647 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000275 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012627 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026957 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.015779 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986833 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986833 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541235 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541235 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000647 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000275 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012627 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223525 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.091292 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000647 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000275 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012627 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223525 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.091292 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72705.882353 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62333.333333 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52827.333765 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54926.233237 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 53845.045119 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.701676 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.701676 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50041.924402 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50041.924402 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72705.882353 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52827.333765 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50405.820291 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 50604.792009 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72705.882353 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52827.333765 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50405.820291 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 50604.792009 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 59111 # number of writebacks
-system.cpu.l2cache.writebacks::total 59111 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12355 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 23054 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12355 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143842 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 156240 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12355 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143842 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 156240 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2461077 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 497040130 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 451732824 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 951327033 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5024401862 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5024401862 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2461077 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 497040130 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5476134686 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 5975728895 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2461077 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 497040130 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5476134686 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 5975728895 # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks 59120 # number of writebacks
+system.cpu.l2cache.writebacks::total 59120 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12349 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10661 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133204 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133204 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12349 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143865 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156268 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12349 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143865 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3058596 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149004 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 496430614 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 450664827 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 950303041 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 40004 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 40004 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5014619823 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5014619823 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3058596 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149004 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 496430614 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5465284650 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 5964922864 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3058596 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149004 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 496430614 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5465284650 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 5964922864 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167008598530 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167012943685 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18318853408 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18318853408 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167009478530 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167013823685 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18374986550 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18374986550 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185327451938 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185331797093 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026778 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015707 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986158 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986158 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541068 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541068 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.091159 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.091159 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40229.876973 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42392.344595 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41265.161490 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185384465080 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185388810235 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026801 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015728 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986833 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986833 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541235 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541235 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49668 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40200.065916 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42272.284682 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41202.872052 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37724.699758 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37724.699758 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.165453 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.165453 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 643581 # number of replacements
-system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 643386 # number of replacements
+system.cpu.dcache.tagsinuse 511.994223 # Cycle average of tags in use
+system.cpu.dcache.total_refs 21524162 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 643898 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33.427906 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 511.994223 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21105442 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21105442 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21105442 # number of overall hits
-system.cpu.dcache.overall_hits::total 21105442 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 731834 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 731834 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2961255 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2961255 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13603 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13603 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3693089 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3693089 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3693089 # number of overall misses
-system.cpu.dcache.overall_misses::total 3693089 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9564740000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9564740000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 104026861731 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 104026861731 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180604500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 180604500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 244000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 244000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 113591601731 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 113591601731 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 113591601731 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 113591601731 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 296044 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285756 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285756 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24798531 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24798531 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24798531 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24798531 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050305 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050305 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288884 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.288884 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35129.315689 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35129.315689 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13276.813938 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13276.813938 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15250 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15250 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30757.883639 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30757.883639 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32046 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 14482 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.377752 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 57.697211 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data 13769851 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13769851 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7260574 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7260574 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 243031 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 243031 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21030425 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21030425 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21030425 # number of overall hits
+system.cpu.dcache.overall_hits::total 21030425 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 731035 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 731035 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2961528 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2961528 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13553 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13553 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3692563 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3692563 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3692563 # number of overall misses
+system.cpu.dcache.overall_misses::total 3692563 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9558145500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9558145500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 103975545233 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 103975545233 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180615500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 180615500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 229500 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 229500 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 113533690733 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 113533690733 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 113533690733 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 113533690733 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14500886 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14500886 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10222102 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10222102 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256584 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 256584 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247612 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247612 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24722988 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24722988 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24722988 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24722988 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050413 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050413 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289718 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052821 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052821 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks
-system.cpu.dcache.writebacks::total 607832 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345983 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 345983 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks
+system.cpu.dcache.writebacks::total 607596 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.603185 # Number of seconds simulated
-sim_ticks 2603185215000 # Number of ticks simulated
-final_tick 2603185215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.092969 # Number of seconds simulated
+sim_ticks 1092968826500 # Number of ticks simulated
+final_tick 1092968826500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 24146 # Simulator instruction rate (inst/s)
-host_op_rate 31077 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 996702828 # Simulator tick rate (ticks/s)
-host_mem_usage 410224 # Number of bytes of host memory used
-host_seconds 2611.80 # Real time elapsed on the host
-sim_insts 63063952 # Number of instructions simulated
-sim_ops 81166306 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 396288 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4383412 # Number of bytes read from this memory
+host_inst_rate 64747 # Simulator instruction rate (inst/s)
+host_op_rate 83356 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1148881552 # Simulator tick rate (ticks/s)
+host_mem_usage 415112 # Number of bytes of host memory used
+host_seconds 951.33 # Real time elapsed on the host
+sim_insts 61595972 # Number of instructions simulated
+sim_ops 79298956 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 59 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 351 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 410 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 59 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 351 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 410 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 59 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 351 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 410 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 408768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4356148 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5252400 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131570212 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 396288 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 821824 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4280832 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 407360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5254000 # Number of bytes read from this memory
+system.physmem.bytes_read::total 59186980 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 408768 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 407360 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 816128 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4265536 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7309968 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6192 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68563 # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7292880 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6387 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68137 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 82095 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15302347 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66888 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6365 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 82120 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6257887 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66649 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 824172 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46523977 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 152232 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1683865 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 163467 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2017682 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50542010 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 152232 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 163467 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 315699 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1644459 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 1157096 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2808086 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1644459 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46523977 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 152232 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1690395 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 163467 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3174778 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53350096 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15302347 # Total number of read requests seen
-system.physmem.writeReqs 824172 # Total number of write requests seen
-system.physmem.cpureqs 284728 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 979350208 # Total number of bytes read from memory
-system.physmem.bytesWritten 52747008 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 131570212 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7309968 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 346 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 14078 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 956479 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 956691 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 956370 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 956557 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 956475 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 956110 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 955970 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 956102 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 956952 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 956364 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 956322 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 956651 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 956317 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 956502 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 956203 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 955936 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 51032 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50766 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50996 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51588 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51566 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 52101 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51797 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51588 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51821 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51672 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51523 # Track writes on a per bank basis
+system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 823485 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 44611322 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 117 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 373998 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3985610 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 995 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 372710 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4807090 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54152487 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 373998 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 372710 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 746707 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3902706 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 15554 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2754282 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6672542 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3902706 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 44611322 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 117 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 373998 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 4001164 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 995 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 372710 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 7561372 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 60825028 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6257887 # Total number of read requests seen
+system.physmem.writeReqs 823485 # Total number of write requests seen
+system.physmem.cpureqs 281561 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 400504768 # Total number of bytes read from memory
+system.physmem.bytesWritten 52703040 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 59186980 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7292880 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 99 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 12576 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 391078 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 391463 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 391295 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 391282 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 391106 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 390838 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 390638 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 390722 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 391599 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 391075 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 391119 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 391349 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 391010 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 391200 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 391075 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 390939 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50710 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 51048 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50959 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50974 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51767 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 51577 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 51386 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51435 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51989 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51698 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51575 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51742 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51637 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51658 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51582 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1182222 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2603183939000 # Total gap between requests
+system.physmem.numWrRetry 1176096 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1092967540000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
-system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
+system.physmem.readPktSize::3 6094848 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 163426 # Categorize read packet sizes
+system.physmem.readPktSize::6 162934 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1939506 # categorize write packet sizes
+system.physmem.writePktSize::2 1932932 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 66888 # categorize write packet sizes
+system.physmem.writePktSize::6 66649 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 14078 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 12576 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1062295 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 996413 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 951405 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 986255 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2765519 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2772335 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5446641 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 44668 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 31245 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 30881 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 30868 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 58473 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 38578 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 65793 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 17450 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 3001 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 140 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 33 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 496879 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 431716 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 387410 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 401103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1104120 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1111115 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2162095 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 27972 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 13923 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 13366 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 13210 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 24040 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 20771 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 31247 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 16482 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2056 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 191 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 73 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3151 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3270 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3380 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3476 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3611 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3812 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4018 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4199 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4366 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32683 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32564 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32454 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32358 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32022 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 31816 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31635 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31468 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3123 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3366 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3475 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3601 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3806 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3971 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4155 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4342 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35804 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35804 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35804 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35804 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35804 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35804 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35804 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32541 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32438 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32329 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32203 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31998 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31649 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31462 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 332610890470 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 410507230470 # Sum of mem lat for all requests
-system.physmem.totBusLat 61208004000 # Total cycles spent in databus access
-system.physmem.totBankLat 16688336000 # Total cycles spent in bank access
-system.physmem.avgQLat 21736.43 # Average queueing delay per request
-system.physmem.avgBankLat 1090.60 # Average bank access latency per request
+system.physmem.totQLat 164150101325 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 197462743325 # Sum of mem lat for all requests
+system.physmem.totBusLat 25031152000 # Total cycles spent in databus access
+system.physmem.totBankLat 8281490000 # Total cycles spent in bank access
+system.physmem.avgQLat 26231.33 # Average queueing delay per request
+system.physmem.avgBankLat 1323.39 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26827.03 # Average memory access latency
-system.physmem.avgRdBW 376.21 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31554.72 # Average memory access latency
+system.physmem.avgRdBW 366.44 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 48.22 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 54.15 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.67 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.48 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.16 # Average read queue length over time
-system.physmem.avgWrQLen 12.97 # Average write queue length over time
-system.physmem.readRowHits 15255805 # Number of row buffer hits during reads
-system.physmem.writeRowHits 789541 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes
-system.physmem.avgGap 161422.56 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 73139 # number of replacements
-system.l2c.tagsinuse 53098.784053 # Cycle average of tags in use
-system.l2c.total_refs 1903330 # Total number of references to valid blocks.
-system.l2c.sampled_refs 138315 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.760836 # Average number of references to valid blocks.
+system.physmem.busUtil 2.59 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.18 # Average read queue length over time
+system.physmem.avgWrQLen 9.65 # Average write queue length over time
+system.physmem.readRowHits 6229568 # Number of row buffer hits during reads
+system.physmem.writeRowHits 789194 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.55 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 95.84 # Row buffer hit rate for writes
+system.physmem.avgGap 154344.04 # Average gap between requests
+system.l2c.replacements 72641 # number of replacements
+system.l2c.tagsinuse 53795.283774 # Cycle average of tags in use
+system.l2c.total_refs 1870380 # Total number of references to valid blocks.
+system.l2c.sampled_refs 137779 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.575218 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 37803.409303 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 5.317240 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.004373 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4191.158517 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2951.048787 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 13.024682 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 4037.185847 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 4097.635305 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.576834 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000081 # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 39404.658188 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 3.902854 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker 0.000810 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4010.788267 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 2816.355225 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 10.914137 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 3736.677098 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 3811.987195 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.601267 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.063952 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.045029 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000199 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.061603 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.062525 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.810223 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 33629 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 4816 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 393434 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 165508 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 53340 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 6018 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 607751 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 201341 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1465837 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 582635 # number of Writeback hits
-system.l2c.Writeback_hits::total 582635 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 1118 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 732 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1850 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 371 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 47631 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 59120 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 106751 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 33629 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 4816 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 393434 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 213139 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 53340 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 6018 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 607751 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 260461 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1572588 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 33629 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 4816 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 393434 # number of overall hits
-system.l2c.overall_hits::cpu0.data 213139 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 53340 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 6018 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 607751 # number of overall hits
-system.l2c.overall_hits::cpu1.data 260461 # number of overall hits
-system.l2c.overall_hits::total 1572588 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 6072 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6358 # number of ReadReq misses
+system.l2c.occ_percent::cpu0.inst 0.061200 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.042974 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker 0.000167 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.057017 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.058166 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.820851 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 31008 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 4497 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 386125 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 166511 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 49385 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 5433 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 590760 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 198089 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1431808 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 581288 # number of Writeback hits
+system.l2c.Writeback_hits::total 581288 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 1275 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 889 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 2164 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 334 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 48752 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 58366 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 107118 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 31008 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 4497 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 386125 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 215263 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 49385 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 5433 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 590760 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 256455 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1538926 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 31008 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 4497 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 386125 # number of overall hits
+system.l2c.overall_hits::cpu0.data 215263 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 49385 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 5433 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 590760 # number of overall hits
+system.l2c.overall_hits::cpu1.data 256455 # number of overall hits
+system.l2c.overall_hits::total 1538926 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 6267 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6396 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 6613 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 6308 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 25383 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 5670 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 4365 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 10035 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 766 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 584 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1350 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 63604 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 77038 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140642 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 6072 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 69962 # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu1.inst 6329 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 6335 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 25357 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 5149 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 3784 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 8933 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 643 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1051 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 63102 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 76972 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140074 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 6267 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 69498 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 6613 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 83346 # number of demand (read+write) misses
-system.l2c.demand_misses::total 166025 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 6072 # number of overall misses
-system.l2c.overall_misses::cpu0.data 69962 # number of overall misses
+system.l2c.demand_misses::cpu1.inst 6329 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 83307 # number of demand (read+write) misses
+system.l2c.demand_misses::total 165431 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 6267 # number of overall misses
+system.l2c.overall_misses::cpu0.data 69498 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 6613 # number of overall misses
-system.l2c.overall_misses::cpu1.data 83346 # number of overall misses
-system.l2c.overall_misses::total 166025 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 932000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker 187000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 315446500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 349611000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1169000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 361021000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 360243500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1388610000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 8984984 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 11919000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 20903984 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 502500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3000500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 3503000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 3132047991 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 4232582992 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7364630983 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 932000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker 187000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 315446500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 3481658991 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 1169000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 361021000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 4592826492 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 8753240983 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 932000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker 187000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 315446500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 3481658991 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 1169000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 361021000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 4592826492 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 8753240983 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 33641 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 4819 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 399506 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 171866 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 53357 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 6018 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 614364 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 207649 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1491220 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 582635 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 582635 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 6788 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 5097 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 11885 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 978 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 743 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1721 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 111235 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 136158 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 247393 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 33641 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 4819 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 399506 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 283101 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 53357 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 6018 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 614364 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 343807 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1738613 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 33641 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 4819 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 399506 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 283101 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 53357 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 6018 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 614364 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 343807 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1738613 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000357 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000623 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015199 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.036994 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000319 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.010764 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.030378 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.017022 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.835298 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.856386 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.844342 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783231 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.786003 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.784428 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.571798 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.565799 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.568496 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000357 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000623 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015199 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.247127 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000319 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.010764 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.242421 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.095493 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000357 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000623 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015199 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.247127 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000319 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.010764 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.242421 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.095493 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77666.666667 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 62333.333333 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51951.004611 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 54987.574709 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68764.705882 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54592.620596 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 57108.988586 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 54706.299492 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1584.653263 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2730.584192 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 2083.107524 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 656.005222 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5137.842466 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 2594.814815 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49242.940554 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54941.496301 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52364.378941 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77666.666667 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 62333.333333 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 51951.004611 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 49765.000872 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68764.705882 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 54592.620596 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 55105.541862 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52722.427243 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77666.666667 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 62333.333333 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 51951.004611 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 49765.000872 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68764.705882 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 54592.620596 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 55105.541862 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52722.427243 # average overall miss latency
+system.l2c.overall_misses::cpu1.inst 6329 # number of overall misses
+system.l2c.overall_misses::cpu1.data 83307 # number of overall misses
+system.l2c.overall_misses::total 165431 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 717000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 326644000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 351867998 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1444500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 345049500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 365249000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1391089998 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 9054984 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 11616000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 20670984 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 661000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2846498 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 3507498 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 3082603488 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 4220265994 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7302869482 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 717000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 326644000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 3434471486 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 1444500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 345049500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 4585514994 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 8693959480 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 717000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 326644000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 3434471486 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 1444500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 345049500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 4585514994 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 8693959480 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 31019 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 4499 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 392392 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 172907 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 49402 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 5433 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 597089 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 204424 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1457165 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 581288 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 581288 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 6424 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 4673 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 11097 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 832 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 553 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1385 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 111854 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 135338 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 247192 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 31019 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 4499 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 392392 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 284761 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 49402 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 5433 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 597089 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 339762 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1704357 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 31019 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 4499 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 392392 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 284761 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 49402 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 5433 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 597089 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 339762 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1704357 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000355 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000445 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015971 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.036991 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000344 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.010600 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.030990 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.017402 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801526 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.809758 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.804992 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772837 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.737794 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.758845 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.564146 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.568739 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.566661 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000355 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000445 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015971 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.244057 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000344 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.010600 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.245192 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.097064 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000355 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000445 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015971 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.244057 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000344 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.010600 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.245192 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.097064 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65181.818182 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52121.270145 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 55013.758286 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84970.588235 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54518.802338 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 57655.722178 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 54860.196317 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1758.590794 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3069.767442 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 2314.002463 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1027.993779 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6976.710784 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 3337.295909 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 48851.121803 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54828.586941 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52135.795951 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65181.818182 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52121.270145 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 49418.278022 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84970.588235 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 54518.802338 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 55043.573697 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52553.387696 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65181.818182 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52121.270145 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 49418.278022 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84970.588235 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 54518.802338 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 55043.573697 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52553.387696 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 66888 # number of writebacks
-system.l2c.writebacks::total 66888 # number of writebacks
+system.l2c.writebacks::writebacks 66649 # number of writebacks
+system.l2c.writebacks::total 66649 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 12 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 6068 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 6320 # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 6263 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 6358 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 6606 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 6284 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 25310 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 5670 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 4365 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 10035 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 766 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 584 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 1350 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 63604 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 77038 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 140642 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 12 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 6068 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 69924 # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 6322 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 6312 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 25285 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 5149 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 3784 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 8933 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 643 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 408 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 1051 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 63102 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 76972 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 140074 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 6263 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 69460 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 6606 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 83322 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 165952 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 12 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 6068 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 69924 # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 6322 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 83284 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 165359 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 6263 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 69460 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 6606 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 83322 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 165952 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 779021 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 149004 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 238620719 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 267423854 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 952034 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 277227882 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 279338276 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1064490790 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57153439 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44270770 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 101424209 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7709241 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5848580 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 13557821 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2345272692 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3275122771 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5620395463 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 779021 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 149004 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 238620719 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 2612696546 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 952034 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 277227882 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 3554461047 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 6684886253 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 779021 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 149004 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 238620719 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 2612696546 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 952034 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 277227882 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 3554461047 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 6684886253 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu1.inst 6322 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 83284 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 165359 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 578020 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93002 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 247369568 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 268980439 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1227032 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 264820900 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 284075297 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1067144258 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51815000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38464202 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 90279202 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6474121 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4094402 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 10568523 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2301961811 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3263562835 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5565524646 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 578020 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 247369568 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 2570942250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1227032 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 264820900 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 3547638132 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 6632668904 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 578020 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 247369568 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 2570942250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1227032 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 264820900 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 3547638132 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 6632668904 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4558163 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330828558 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1893563 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154946270000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167283550284 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062643238 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17370101500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 18432744738 # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12397759064 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1815064 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154673182999 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167077315290 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 998522739 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17312425061 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 18310947800 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4558163 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13393471796 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1893563 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172316371500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 185716295022 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036773 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030263 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.016973 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.835298 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.856386 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.844342 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783231 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786003 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784428 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.571798 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565799 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.568496 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.242351 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.095451 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.242351 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.095451 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42313.900949 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 44452.303628 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 42058.111023 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10079.971605 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10142.215349 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.046238 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.283290 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.691781 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.830370 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36873.037733 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42513.081479 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 39962.425613 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13396281803 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1815064 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171985608060 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 185388263090 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036771 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030877 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.017352 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801526 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809758 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.804992 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772837 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.737794 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.758845 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.564146 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.568739 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.566661 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.243924 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.245125 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.097021 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.243924 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.245125 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.097021 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42305.825574 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45005.592047 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 42204.637453 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10063.119052 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10164.958245 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10106.257920 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.617418 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.299020 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10055.683159 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36480.013486 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42399.350868 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 39732.745877 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37013.277426 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42596.874934 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40110.722150 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37013.277426 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42596.874934 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40110.722150 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9024363 # DTB read hits
-system.cpu0.dtb.read_misses 35062 # DTB read misses
-system.cpu0.dtb.write_hits 5257895 # DTB write hits
-system.cpu0.dtb.write_misses 6477 # DTB write misses
+system.cpu0.dtb.read_hits 8918270 # DTB read hits
+system.cpu0.dtb.read_misses 33761 # DTB read misses
+system.cpu0.dtb.write_hits 5143475 # DTB write hits
+system.cpu0.dtb.write_misses 6030 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2160 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 2137 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1055 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 365 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9059425 # DTB read accesses
-system.cpu0.dtb.write_accesses 5264372 # DTB write accesses
+system.cpu0.dtb.perms_faults 538 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 8952031 # DTB read accesses
+system.cpu0.dtb.write_accesses 5149505 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14282258 # DTB hits
-system.cpu0.dtb.misses 41539 # DTB misses
-system.cpu0.dtb.accesses 14323797 # DTB accesses
-system.cpu0.itb.inst_hits 4307156 # ITB inst hits
-system.cpu0.itb.inst_misses 5205 # ITB inst misses
+system.cpu0.dtb.hits 14061745 # DTB hits
+system.cpu0.dtb.misses 39791 # DTB misses
+system.cpu0.dtb.accesses 14101536 # DTB accesses
+system.cpu0.itb.inst_hits 4226389 # ITB inst hits
+system.cpu0.itb.inst_misses 5148 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1360 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1370 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4312361 # ITB inst accesses
-system.cpu0.itb.hits 4307156 # DTB hits
-system.cpu0.itb.misses 5205 # DTB misses
-system.cpu0.itb.accesses 4312361 # DTB accesses
-system.cpu0.numCycles 69075583 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4231537 # ITB inst accesses
+system.cpu0.itb.hits 4226389 # DTB hits
+system.cpu0.itb.misses 5148 # DTB misses
+system.cpu0.itb.accesses 4231537 # DTB accesses
+system.cpu0.numCycles 67785734 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 6134621 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 4681383 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 299233 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 3810859 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 2992358 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 6012491 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 4585363 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 296577 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 3765620 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 2919015 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 688987 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 28743 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 12013253 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 32740564 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6134621 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3681345 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7677557 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1482239 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 64559 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 21828282 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 5891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 53864 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 90312 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 236 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4305560 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 159104 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2370 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 42798314 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.987162 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.368020 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 674578 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 28863 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 11763968 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32049970 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6012491 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3593593 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7526717 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1460555 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 62547 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 20715231 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 4834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 54522 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 85492 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4224665 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 156872 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2292 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 41263116 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.003783 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.384047 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 35128127 82.08% 82.08% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 610328 1.43% 83.50% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 795353 1.86% 85.36% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 689183 1.61% 86.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 781372 1.83% 88.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 569733 1.33% 90.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 711695 1.66% 91.79% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 364225 0.85% 92.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3148298 7.36% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 33743827 81.78% 81.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 566856 1.37% 83.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 818944 1.98% 85.14% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 676218 1.64% 86.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 773991 1.88% 88.65% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 560705 1.36% 90.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 670652 1.63% 91.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 352961 0.86% 92.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3098962 7.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 42798314 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.088810 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.473982 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12517044 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 21792466 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6901256 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 586970 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1000578 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 954803 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64851 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 40861344 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 213562 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1000578 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 13092600 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5813788 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13806762 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6861684 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2222902 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 39740402 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2257 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 444272 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1240471 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 77 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 40148585 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 179562690 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 179528337 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34353 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 31678708 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8469876 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 458191 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 414927 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5465728 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7827563 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5820560 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1149873 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1213359 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 37598856 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 946637 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37967135 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 82667 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6387129 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13438267 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 258027 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 42798314 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.887118 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.498670 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 41263116 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.088698 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.472813 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12272697 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 20662299 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6831890 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 510283 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 985947 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 936613 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 64715 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40060631 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 213244 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 985947 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12836550 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5831447 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 12738222 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6726939 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2144011 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 38954643 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 2110 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 419770 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1235917 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39310777 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 175935751 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 175901847 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 33904 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 30931608 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8379168 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 411632 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 370766 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5325827 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7663556 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5690026 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1120184 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1252239 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 36870649 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 896350 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37273811 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 81085 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6313763 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13211798 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 257333 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 41263116 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.903320 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.511259 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 27228481 63.62% 63.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 6024200 14.08% 77.70% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3238541 7.57% 85.26% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2496476 5.83% 91.10% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2116280 4.94% 96.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 952748 2.23% 98.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 498209 1.16% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 188721 0.44% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 54658 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 26116346 63.29% 63.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5727985 13.88% 77.17% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3164328 7.67% 84.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2471717 5.99% 90.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2127646 5.16% 95.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 929575 2.25% 98.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 487199 1.18% 99.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 186194 0.45% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 52126 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 42798314 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 41263116 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 25719 2.40% 2.40% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 458 0.04% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 838558 78.31% 80.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 206136 19.25% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 25847 2.42% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 453 0.04% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 842941 78.82% 81.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 200262 18.72% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22801553 60.06% 60.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 48143 0.13% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9487186 24.99% 85.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5577397 14.69% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 52409 0.14% 0.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22347449 59.95% 60.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 46908 0.13% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9376305 25.16% 85.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5450017 14.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37967135 # Type of FU issued
-system.cpu0.iq.rate 0.549646 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1070871 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028205 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 119919123 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 44940813 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 35094596 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8245 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4688 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3877 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38981568 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4289 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 319568 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37273811 # Type of FU issued
+system.cpu0.iq.rate 0.549877 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1069503 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028693 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 116992528 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 44088817 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 34369527 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8360 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3860 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38286519 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 307254 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1406645 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2495 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13426 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 546497 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1385688 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2397 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13227 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 538655 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2149373 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5419 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2192760 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5477 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1000578 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4177293 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 102909 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 38663154 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 84882 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7827563 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5820560 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 615194 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 41110 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3269 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13426 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 151880 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 119782 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 271662 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 37584827 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9341263 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 382308 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 985947 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4198442 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 101973 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 37885007 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 86572 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7663556 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5690026 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 571892 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 40888 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13227 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 150955 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 118096 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 269051 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 36896358 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9233299 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 377453 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 117661 # number of nop insts executed
-system.cpu0.iew.exec_refs 14871823 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4965899 # Number of branches executed
-system.cpu0.iew.exec_stores 5530560 # Number of stores executed
-system.cpu0.iew.exec_rate 0.544112 # Inst execution rate
-system.cpu0.iew.wb_sent 37390069 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 35098473 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18662098 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35837598 # num instructions consuming a value
+system.cpu0.iew.exec_nop 118008 # number of nop insts executed
+system.cpu0.iew.exec_refs 14636338 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4860481 # Number of branches executed
+system.cpu0.iew.exec_stores 5403039 # Number of stores executed
+system.cpu0.iew.exec_rate 0.544309 # Inst execution rate
+system.cpu0.iew.wb_sent 36702505 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34373387 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18311880 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35235348 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.508117 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.520741 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.507089 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.519702 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6206788 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 688610 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 235451 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 41797736 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.765444 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.723461 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6136748 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 639017 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 232971 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 40277169 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.776860 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.743491 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 29752237 71.18% 71.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5970878 14.29% 85.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1965315 4.70% 90.17% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 999760 2.39% 92.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 803961 1.92% 94.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 518760 1.24% 95.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 395530 0.95% 96.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 220150 0.53% 97.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1171145 2.80% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 28628964 71.08% 71.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5718437 14.20% 85.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1895078 4.71% 89.98% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 977858 2.43% 92.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 774389 1.92% 94.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 507385 1.26% 95.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 386799 0.96% 96.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 213802 0.53% 97.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1174457 2.92% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 41797736 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 24265529 # Number of instructions committed
-system.cpu0.commit.committedOps 31993822 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 40277169 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 23678178 # Number of instructions committed
+system.cpu0.commit.committedOps 31289712 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11694981 # Number of memory references committed
-system.cpu0.commit.loads 6420918 # Number of loads committed
-system.cpu0.commit.membars 234476 # Number of memory barriers committed
-system.cpu0.commit.branches 4347395 # Number of branches committed
+system.cpu0.commit.refs 11429239 # Number of memory references committed
+system.cpu0.commit.loads 6277868 # Number of loads committed
+system.cpu0.commit.membars 229666 # Number of memory barriers committed
+system.cpu0.commit.branches 4244753 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 28261624 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 500034 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1171145 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 27646281 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 489273 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1174457 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 77942939 # The number of ROB reads
-system.cpu0.rob.rob_writes 77403720 # The number of ROB writes
-system.cpu0.timesIdled 364282 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26277269 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5137251054 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 24184787 # Number of Instructions Simulated
-system.cpu0.committedOps 31913080 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 24184787 # Number of Instructions Simulated
-system.cpu0.cpi 2.856158 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.856158 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.350121 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.350121 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 175453235 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34873256 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3235 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 908 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 13424511 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 527689 # number of misc regfile writes
-system.cpu0.icache.replacements 399628 # number of replacements
-system.cpu0.icache.tagsinuse 511.593033 # Cycle average of tags in use
-system.cpu0.icache.total_refs 3873847 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 400140 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 9.681229 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 6818802000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.593033 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.999205 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.999205 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3873847 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3873847 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3873847 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3873847 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3873847 # number of overall hits
-system.cpu0.icache.overall_hits::total 3873847 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 431582 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 431582 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 431582 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 431582 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 431582 # number of overall misses
-system.cpu0.icache.overall_misses::total 431582 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5855735994 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5855735994 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5855735994 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5855735994 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5855735994 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5855735994 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 4305429 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 4305429 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 4305429 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 4305429 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 4305429 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 4305429 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100241 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.100241 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100241 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.100241 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100241 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.100241 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13568.072797 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13568.072797 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13568.072797 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13568.072797 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13568.072797 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13568.072797 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2448 # number of cycles access was blocked
+system.cpu0.rob.rob_reads 75678018 # The number of ROB reads
+system.cpu0.rob.rob_writes 75840987 # The number of ROB writes
+system.cpu0.timesIdled 360810 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 26522618 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2118110205 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 23597436 # Number of Instructions Simulated
+system.cpu0.committedOps 31208970 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 23597436 # Number of Instructions Simulated
+system.cpu0.cpi 2.872589 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.872589 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.348118 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.348118 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 172012852 # number of integer regfile reads
+system.cpu0.int_regfile_writes 34120799 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 892 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 13056447 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 451188 # number of misc regfile writes
+system.cpu0.icache.replacements 392549 # number of replacements
+system.cpu0.icache.tagsinuse 511.079018 # Cycle average of tags in use
+system.cpu0.icache.total_refs 3800627 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 393061 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 9.669306 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 6496390000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 511.079018 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.998201 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.998201 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 3800627 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 3800627 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 3800627 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 3800627 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 3800627 # number of overall hits
+system.cpu0.icache.overall_hits::total 3800627 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 423907 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 423907 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 423907 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 423907 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 423907 # number of overall misses
+system.cpu0.icache.overall_misses::total 423907 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5778558992 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5778558992 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5778558992 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5778558992 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5778558992 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5778558992 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 4224534 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 4224534 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 4224534 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 4224534 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 4224534 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 4224534 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100344 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.100344 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100344 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.100344 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100344 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.100344 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13631.666833 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13631.666833 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13631.666833 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13631.666833 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 3110 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 142 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.239437 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.326797 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31419 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 31419 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 31419 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 31419 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 31419 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 31419 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400163 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 400163 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 400163 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 400163 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 400163 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 400163 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4791432494 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4791432494 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4791432494 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4791432494 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4791432494 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4791432494 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30826 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 30826 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 30826 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 30826 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 30826 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 30826 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393081 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 393081 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 393081 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 393081 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 393081 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 393081 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4722265492 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4722265492 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4722265492 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4722265492 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4722265492 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4722265492 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092944 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.092944 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.092944 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11973.701951 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11973.701951 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11973.701951 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093047 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.093047 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.093047 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12013.466670 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 274722 # number of replacements
-system.cpu0.dcache.tagsinuse 476.919366 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 9525271 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 275234 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 34.607901 # Average number of references to valid blocks.
+system.cpu0.dcache.replacements 276186 # number of replacements
+system.cpu0.dcache.tagsinuse 460.207954 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 9271152 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 276698 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 33.506393 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 476.919366 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.931483 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.931483 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 5895102 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 5895102 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3238989 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3238989 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174455 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 174455 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171581 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 171581 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 9134091 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 9134091 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 9134091 # number of overall hits
-system.cpu0.dcache.overall_hits::total 9134091 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 390587 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 390587 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1579573 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1579573 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8896 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 8896 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7728 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7728 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1970160 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1970160 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1970160 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1970160 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5389048500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5389048500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60454939374 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 60454939374 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88150000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 88150000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50211500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 50211500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 65843987874 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 65843987874 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 65843987874 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 65843987874 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 6285689 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 6285689 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818562 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 4818562 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183351 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 183351 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179309 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 179309 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 11104251 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 11104251 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 11104251 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 11104251 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062139 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.062139 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327810 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.327810 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048519 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048519 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043099 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043099 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177424 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.177424 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177424 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.177424 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.306362 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.306362 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38272.963246 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38272.963246 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9908.947842 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9908.947842 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6497.347308 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6497.347308 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33420.629733 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33420.629733 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 8059 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 2986 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 556 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.494604 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 37.325000 # average number of cycles each access was blocked
+system.cpu0.dcache.occ_blocks::cpu0.data 460.207954 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.898844 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.898844 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 5791916 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 5791916 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3159128 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3159128 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139197 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 139197 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137104 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 137104 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 8951044 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 8951044 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 8951044 # number of overall hits
+system.cpu0.dcache.overall_hits::total 8951044 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 391497 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 391497 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1585211 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1585211 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8805 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 8805 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7503 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7503 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1976708 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1976708 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 1976708 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1976708 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5419802000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 5419802000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59847292371 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 59847292371 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88405500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 88405500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46738000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 46738000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 65267094371 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 65267094371 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 65267094371 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 65267094371 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 6183413 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 6183413 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744339 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4744339 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144607 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 144607 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 10927752 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 10927752 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 10927752 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 10927752 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063314 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.063314 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334127 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.334127 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059492 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059492 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051885 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051885 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180889 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.180889 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180889 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.180889 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13843.789352 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13843.789352 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37753.518220 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 37753.518220 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10040.374787 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10040.374787 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6229.241637 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6229.241637 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33018.075695 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33018.075695 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 8715 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 3535 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 594 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.671717 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 42.590361 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 255180 # number of writebacks
-system.cpu0.dcache.writebacks::total 255180 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202008 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 202008 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1448555 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1448555 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650563 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1650563 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650563 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1650563 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188579 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 188579 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131018 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 131018 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8412 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8412 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7726 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7726 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 319597 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 319597 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 319597 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 319597 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2343972000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2343972000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029495991 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029495991 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66259000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66259000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34759500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34759500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6373467991 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 6373467991 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6373467991 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 6373467991 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432446000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432446000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199878877 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199878877 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14632324877 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14632324877 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030001 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030001 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045879 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045879 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043088 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043088 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.028781 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.028781 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12429.655476 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12429.655476 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30755.285465 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30755.285465 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7876.723728 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7876.723728 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4499.029252 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4499.029252 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 256562 # number of writebacks
+system.cpu0.dcache.writebacks::total 256562 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202833 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 202833 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454685 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1454685 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 458 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 458 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657518 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1657518 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657518 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1657518 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188664 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 188664 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130526 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 130526 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8347 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8347 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7503 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7503 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 319190 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 319190 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 319190 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 319190 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2355812500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2355812500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3979098490 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3979098490 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66495500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66495500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31732000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31732000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6334910990 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6334910990 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6334910990 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6334910990 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504511500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504511500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128583377 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128583377 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14633094877 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14633094877 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030511 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030511 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027512 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027512 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056398 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056398 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051885 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051885 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12486.815185 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12486.815185 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30485.102508 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30485.102508 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7966.395112 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7966.395112 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4229.241637 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4229.241637 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 43034108 # DTB read hits
-system.cpu1.dtb.read_misses 42641 # DTB read misses
-system.cpu1.dtb.write_hits 7001737 # DTB write hits
-system.cpu1.dtb.write_misses 11814 # DTB write misses
+system.cpu1.dtb.read_hits 42721233 # DTB read hits
+system.cpu1.dtb.read_misses 41267 # DTB read misses
+system.cpu1.dtb.write_hits 6827437 # DTB write hits
+system.cpu1.dtb.write_misses 11457 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2370 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2838 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2630 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 43076749 # DTB read accesses
-system.cpu1.dtb.write_accesses 7013551 # DTB write accesses
+system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 42762500 # DTB read accesses
+system.cpu1.dtb.write_accesses 6838894 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 50035845 # DTB hits
-system.cpu1.dtb.misses 54455 # DTB misses
-system.cpu1.dtb.accesses 50090300 # DTB accesses
-system.cpu1.itb.inst_hits 7783284 # ITB inst hits
-system.cpu1.itb.inst_misses 5669 # ITB inst misses
+system.cpu1.dtb.hits 49548670 # DTB hits
+system.cpu1.dtb.misses 52724 # DTB misses
+system.cpu1.dtb.accesses 49601394 # DTB accesses
+system.cpu1.itb.inst_hits 7583980 # ITB inst hits
+system.cpu1.itb.inst_misses 5601 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1584 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1561 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1542 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1591 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7788953 # ITB inst accesses
-system.cpu1.itb.hits 7783284 # DTB hits
-system.cpu1.itb.misses 5669 # DTB misses
-system.cpu1.itb.accesses 7788953 # DTB accesses
-system.cpu1.numCycles 409060969 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7589581 # ITB inst accesses
+system.cpu1.itb.hits 7583980 # DTB hits
+system.cpu1.itb.misses 5601 # DTB misses
+system.cpu1.itb.accesses 7589581 # DTB accesses
+system.cpu1.numCycles 406854445 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 9019142 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 7341577 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 421290 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 5896961 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 5059614 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 8781590 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 7165099 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 410272 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 5784510 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 4949628 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 812166 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 44802 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 19538569 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 61710735 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9019142 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 5871780 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 13457716 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3440559 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 72159 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 78167878 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 5662 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 49809 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 140998 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 7781352 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 538014 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3102 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 113786982 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.664391 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.995438 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 773605 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 42847 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 18987687 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 60514486 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 8781590 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5723233 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 13164545 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3370379 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 67214 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 77426772 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 4687 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 46358 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 129737 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 707 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 7581976 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 531329 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3060 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 112134243 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.659620 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.988948 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 100336589 88.18% 88.18% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 821334 0.72% 88.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 966420 0.85% 89.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1725152 1.52% 91.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1418529 1.25% 92.51% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 601242 0.53% 93.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1958088 1.72% 94.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 436465 0.38% 95.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5523163 4.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 98977030 88.27% 88.27% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 796888 0.71% 88.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 939707 0.84% 89.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1694875 1.51% 91.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1403619 1.25% 92.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 573280 0.51% 93.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1928107 1.72% 94.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 410374 0.37% 95.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5410363 4.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 113786982 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022048 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.150860 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 20926147 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 77797918 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12266013 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 542191 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2254713 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1149115 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 100993 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 71511004 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 338807 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2254713 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22129407 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 32117603 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 41299485 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11510444 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4475330 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 67658360 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 19594 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 697706 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3178110 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 32539 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 70993653 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 310596355 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 310537273 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 59082 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 50200074 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 20793579 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 474201 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 414075 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8134070 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 12921007 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8155176 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1083797 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1589261 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 62166896 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1195329 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 89153414 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 99788 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 13746763 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 36760953 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 275268 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 113786982 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.783512 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.519359 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 112134243 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.021584 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.148737 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 20329334 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 77067438 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 11999240 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 528326 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2209905 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1105816 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 98089 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 69983071 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 327113 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2209905 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 21512186 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 32033439 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 40715711 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11249430 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4413572 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 66189803 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 19593 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 681290 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3157378 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 32035 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 69538015 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 303909752 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 303850528 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59224 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 49060717 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 20477298 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 445152 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 388313 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 7961235 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 12608499 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 7947542 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1037744 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1535939 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 60784720 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1155099 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 87803920 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 97322 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 13491429 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 36062520 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 274254 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 112134243 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.783025 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.519999 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 83183185 73.10% 73.10% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8664055 7.61% 80.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4355929 3.83% 84.55% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3746204 3.29% 87.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10471181 9.20% 97.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1956933 1.72% 98.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1074012 0.94% 99.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 258436 0.23% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 77047 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 82080142 73.20% 73.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8453890 7.54% 80.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4228870 3.77% 84.51% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3673146 3.28% 87.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10396618 9.27% 97.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1923791 1.72% 98.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1051838 0.94% 99.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 251187 0.22% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 74761 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 113786982 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 112134243 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 29283 0.37% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 991 0.01% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7571422 95.88% 96.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 294824 3.73% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 29715 0.38% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7547628 96.04% 96.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 280810 3.57% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37493479 42.06% 42.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 61246 0.07% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43910750 49.25% 91.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7372221 8.27% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 36673483 41.77% 42.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59172 0.07% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1514 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 43579800 49.63% 91.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7175925 8.17% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 89153414 # Type of FU issued
-system.cpu1.iq.rate 0.217947 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7896520 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.088572 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 300129512 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 77117892 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 54483079 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14896 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8093 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96728092 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7845 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 354516 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 87803920 # Type of FU issued
+system.cpu1.iq.rate 0.215812 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7859149 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.089508 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 295735701 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 75439999 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 53226631 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 15376 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8066 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6868 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 95340871 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 8201 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 343143 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2925065 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 4096 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17562 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1131401 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2852269 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3976 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17384 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1106708 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31964883 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 695794 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31919671 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 693087 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2254713 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24187633 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 367329 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 63466208 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 114663 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 12921007 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8155176 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 887376 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 69283 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3741 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17562 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 208254 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 160111 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 368365 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 87428231 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43415449 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1725183 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2209905 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24121244 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 365124 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 62044608 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 111941 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 12608499 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 7947542 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 865588 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 68372 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3578 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17384 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 203207 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 155936 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 359143 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 86098386 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43091016 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1705534 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 103983 # number of nop insts executed
-system.cpu1.iew.exec_refs 50722611 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 7090027 # Number of branches executed
-system.cpu1.iew.exec_stores 7307162 # Number of stores executed
-system.cpu1.iew.exec_rate 0.213729 # Inst execution rate
-system.cpu1.iew.wb_sent 86641966 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 54489882 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 30361493 # num instructions producing a value
-system.cpu1.iew.wb_consumers 54263873 # num instructions consuming a value
+system.cpu1.iew.exec_nop 104789 # number of nop insts executed
+system.cpu1.iew.exec_refs 50204478 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 6908033 # Number of branches executed
+system.cpu1.iew.exec_stores 7113462 # Number of stores executed
+system.cpu1.iew.exec_rate 0.211620 # Inst execution rate
+system.cpu1.iew.wb_sent 85323128 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 53233499 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 29734399 # num instructions producing a value
+system.cpu1.iew.wb_consumers 53052149 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.133207 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.559516 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.130842 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.560475 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 13678793 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 920061 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 321962 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 111532269 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.442230 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.412276 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 13410332 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 880845 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 313641 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 109924338 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.438116 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.408415 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 94330377 84.58% 84.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8440609 7.57% 92.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2214130 1.99% 94.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1297536 1.16% 95.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1275593 1.14% 96.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 591609 0.53% 96.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 995873 0.89% 97.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 566603 0.51% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1819939 1.63% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 93165965 84.75% 84.75% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8233685 7.49% 92.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2134554 1.94% 94.19% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1255111 1.14% 95.33% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1238932 1.13% 96.46% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 576271 0.52% 96.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 972518 0.88% 97.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 559108 0.51% 98.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1788194 1.63% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 111532269 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38948804 # Number of instructions committed
-system.cpu1.commit.committedOps 49322865 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 109924338 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38068175 # Number of instructions committed
+system.cpu1.commit.committedOps 48159625 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 17019717 # Number of memory references committed
-system.cpu1.commit.loads 9995942 # Number of loads committed
-system.cpu1.commit.membars 202353 # Number of memory barriers committed
-system.cpu1.commit.branches 6138218 # Number of branches committed
-system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 43713249 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 556359 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1819939 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 16597064 # Number of memory references committed
+system.cpu1.commit.loads 9756230 # Number of loads committed
+system.cpu1.commit.membars 190160 # Number of memory barriers committed
+system.cpu1.commit.branches 5968166 # Number of branches committed
+system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 42694155 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 534687 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1788194 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 171599349 # The number of ROB reads
-system.cpu1.rob.rob_writes 128350222 # The number of ROB writes
-system.cpu1.timesIdled 1423694 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 295273987 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4796667155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 38879165 # Number of Instructions Simulated
-system.cpu1.committedOps 49253226 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 38879165 # Number of Instructions Simulated
-system.cpu1.cpi 10.521341 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.521341 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.095045 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.095045 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 391632222 # number of integer regfile reads
-system.cpu1.int_regfile_writes 56613239 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4857 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2306 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 19006571 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 429961 # number of misc regfile writes
-system.cpu1.icache.replacements 614526 # number of replacements
-system.cpu1.icache.tagsinuse 498.795598 # Cycle average of tags in use
-system.cpu1.icache.total_refs 7119619 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 615038 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 11.575901 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 74541182500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 498.795598 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.974210 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.974210 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 7119619 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 7119619 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 7119619 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 7119619 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 7119619 # number of overall hits
-system.cpu1.icache.overall_hits::total 7119619 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 661683 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 661683 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 661683 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 661683 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 661683 # number of overall misses
-system.cpu1.icache.overall_misses::total 661683 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8857903496 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 8857903496 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 8857903496 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 8857903496 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 8857903496 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 8857903496 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 7781302 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 7781302 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 7781302 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 7781302 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 7781302 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 7781302 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085035 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.085035 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085035 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.085035 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085035 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.085035 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13386.929233 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13386.929233 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13386.929233 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13386.929233 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 2804 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 188 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.914894 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.rob.rob_reads 168661953 # The number of ROB reads
+system.cpu1.rob.rob_writes 125442140 # The number of ROB writes
+system.cpu1.timesIdled 1407356 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 294720202 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 1778443945 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 37998536 # Number of Instructions Simulated
+system.cpu1.committedOps 48089986 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 37998536 # Number of Instructions Simulated
+system.cpu1.cpi 10.707108 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 10.707108 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.093396 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.093396 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 385381686 # number of integer regfile reads
+system.cpu1.int_regfile_writes 55406618 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 18496665 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 405533 # number of misc regfile writes
+system.cpu1.icache.replacements 597187 # number of replacements
+system.cpu1.icache.tagsinuse 480.515152 # Cycle average of tags in use
+system.cpu1.icache.total_refs 6939274 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 597699 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 11.609981 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 74121232000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 480.515152 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.938506 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.938506 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 6939274 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 6939274 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 6939274 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 6939274 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 6939274 # number of overall hits
+system.cpu1.icache.overall_hits::total 6939274 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 642651 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 642651 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 642651 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 642651 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 642651 # number of overall misses
+system.cpu1.icache.overall_misses::total 642651 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8610286993 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 8610286993 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 8610286993 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 8610286993 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 8610286993 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 8610286993 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 7581925 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 7581925 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 7581925 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 7581925 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 7581925 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 7581925 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084761 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.084761 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084761 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.084761 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084761 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.084761 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13398.076083 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13398.076083 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13398.076083 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13398.076083 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13398.076083 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13398.076083 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 2076 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 753 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.069767 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets 753 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46618 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 46618 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 46618 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 46618 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 46618 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 46618 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615065 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 615065 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 615065 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 615065 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 615065 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 615065 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7253593996 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 7253593996 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7253593996 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 7253593996 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7253593996 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 7253593996 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2902500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2902500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2902500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 2902500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079044 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.079044 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.079044 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11793.215345 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44927 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 44927 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 44927 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 44927 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 44927 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 44927 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597724 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 597724 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 597724 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 597724 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 597724 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 597724 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7047898994 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 7047898994 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7047898994 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 7047898994 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7047898994 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 7047898994 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078835 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.078835 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.078835 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11791.226375 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 363115 # number of replacements
-system.cpu1.dcache.tagsinuse 487.216470 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 13089737 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 363478 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 36.012460 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 70648399000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 487.216470 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.951595 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.951595 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 8556277 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 8556277 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4290501 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4290501 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104307 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 104307 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100808 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 100808 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 12846778 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 12846778 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 12846778 # number of overall hits
-system.cpu1.dcache.overall_hits::total 12846778 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 401782 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 401782 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1563319 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1563319 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14178 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 14178 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10904 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 10904 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 1965101 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 1965101 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 1965101 # number of overall misses
-system.cpu1.dcache.overall_misses::total 1965101 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6025006500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 6025006500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64041163497 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 64041163497 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131124500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 131124500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58523500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 58523500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 70066169997 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 70066169997 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 70066169997 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 70066169997 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 8958059 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 8958059 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 5853820 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 5853820 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 118485 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 118485 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111712 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 111712 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 14811879 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 14811879 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 14811879 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 14811879 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044851 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.044851 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267060 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.267060 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119661 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119661 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097608 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097608 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132671 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.132671 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132671 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.132671 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14995.710360 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14995.710360 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40964.872491 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 40964.872491 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.448300 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.448300 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5367.158841 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5367.158841 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35655.251306 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 35655.251306 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35655.251306 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 35655.251306 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 28539 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 15177 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 3269 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.730193 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 91.427711 # average number of cycles each access was blocked
+system.cpu1.dcache.replacements 360661 # number of replacements
+system.cpu1.dcache.tagsinuse 473.725553 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 12688668 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 361027 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 35.146036 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 70279173000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 473.725553 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.925245 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.925245 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 8315910 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 8315910 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 4141838 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 4141838 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97575 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 97575 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94901 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 94901 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 12457748 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 12457748 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 12457748 # number of overall hits
+system.cpu1.dcache.overall_hits::total 12457748 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 397655 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 397655 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1555408 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1555408 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 13937 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10609 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10609 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 1953063 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 1953063 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 1953063 # number of overall misses
+system.cpu1.dcache.overall_misses::total 1953063 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5962620500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 5962620500 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 63820949998 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 63820949998 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128371500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 128371500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53750500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 53750500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 69783570498 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 69783570498 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 69783570498 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 69783570498 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 8713565 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 8713565 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 5697246 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 5697246 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111512 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 111512 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105510 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 105510 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 14410811 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 14410811 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 14410811 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 14410811 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045636 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.045636 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273011 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.273011 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124982 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124982 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100550 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100550 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135528 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.135528 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135528 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.135528 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14994.456250 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14994.456250 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41031.645715 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 41031.645715 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9210.841645 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9210.841645 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5066.500141 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5066.500141 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 35730.322318 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 35730.322318 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 26431 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 15171 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 158 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.193118 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 96.018987 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 327455 # number of writebacks
-system.cpu1.dcache.writebacks::total 327455 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170587 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 170587 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400204 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 1400204 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1432 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1432 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570791 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1570791 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570791 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1570791 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231195 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 231195 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163115 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 163115 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10902 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10902 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 394310 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 394310 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 394310 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 394310 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2860496500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2860496500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5258978708 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5258978708 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89750500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89750500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36721500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36721500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8119475208 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 8119475208 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8119475208 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 8119475208 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298302500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298302500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27190030960 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27190030960 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196488333460 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196488333460 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025809 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025809 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027865 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027865 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107575 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107575 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097590 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097590 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026621 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026621 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12372.657281 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12372.657281 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32240.926389 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32240.926389 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7041.463989 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7041.463989 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3368.326912 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3368.326912 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 324726 # number of writebacks
+system.cpu1.dcache.writebacks::total 324726 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169327 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 169327 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393847 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1393847 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1563174 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1563174 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1563174 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1563174 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228328 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 228328 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161561 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 161561 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12488 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12488 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10607 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10607 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 389889 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 389889 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 389889 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 389889 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2825835000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2825835000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5223945209 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5223945209 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87441500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87441500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32536500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32536500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8049780209 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 8049780209 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8049780209 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 8049780209 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168995979000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168995979000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27123329043 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27123329043 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196119308043 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196119308043 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026204 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026204 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028358 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028358 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111988 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111988 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100531 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100531 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.027055 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.027055 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.208787 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12376.208787 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32334.197046 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32334.197046 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7002.041960 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7002.041960 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3067.455454 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3067.455454 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1162989936366 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1162989936366 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 497798121418 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 497798121418 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 497798121418 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 497798121418 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 43794 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 41715 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 53929 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.523518 # Number of seconds simulated
-sim_ticks 2523517846500 # Number of ticks simulated
-final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.523205 # Number of seconds simulated
+sim_ticks 2523204701000 # Number of ticks simulated
+final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 24932 # Simulator instruction rate (inst/s)
-host_op_rate 32070 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1038273503 # Simulator tick rate (ticks/s)
-host_mem_usage 403456 # Number of bytes of host memory used
-host_seconds 2430.49 # Real time elapsed on the host
-sim_insts 60597240 # Number of instructions simulated
-sim_ops 77945362 # Number of ops (including micro ops) simulated
+host_inst_rate 64094 # Simulator instruction rate (inst/s)
+host_op_rate 82471 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2681679652 # Simulator tick rate (ticks/s)
+host_mem_usage 409992 # Number of bytes of host memory used
+host_seconds 940.90 # Real time elapsed on the host
+sim_insts 60306320 # Number of instructions simulated
+sim_ops 77597310 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096842 # Total number of read requests seen
-system.physmem.writeReqs 813129 # Total number of write requests seen
-system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966197888 # Total number of bytes read from memory
-system.physmem.bytesWritten 52040256 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis
+system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096856 # Total number of read requests seen
+system.physmem.writeReqs 813138 # Total number of write requests seen
+system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966198784 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040832 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2523516727500 # Total gap between requests
+system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2523203522000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154598 # Categorize read packet sizes
+system.physmem.readPktSize::6 154612 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1937150 # categorize write packet sizes
+system.physmem.writePktSize::2 1943854 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59111 # categorize write packet sizes
+system.physmem.writePktSize::6 59120 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests
-system.physmem.totBusLat 60385948000 # Total cycles spent in databus access
-system.physmem.totBankLat 16343502000 # Total cycles spent in bank access
-system.physmem.avgQLat 21736.41 # Average queueing delay per request
-system.physmem.avgBankLat 1082.60 # Average bank access latency per request
+system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests
+system.physmem.totBusLat 60386192000 # Total cycles spent in databus access
+system.physmem.totBankLat 16356620000 # Total cycles spent in bank access
+system.physmem.avgQLat 21743.10 # Average queueing delay per request
+system.physmem.avgBankLat 1083.47 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26819.01 # Average memory access latency
-system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26826.57 # Average memory access latency
+system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.52 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.16 # Average read queue length over time
-system.physmem.avgWrQLen 11.85 # Average write queue length over time
-system.physmem.readRowHits 15052691 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784814 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 10.68 # Average write queue length over time
+system.physmem.readRowHits 15052450 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784654 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes
-system.physmem.avgGap 158612.28 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes
+system.physmem.avgGap 158592.36 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51295505 # DTB read hits
-system.cpu.dtb.read_misses 73548 # DTB read misses
-system.cpu.dtb.write_hits 11769416 # DTB write hits
-system.cpu.dtb.write_misses 17308 # DTB write misses
+system.cpu.dtb.read_hits 51212683 # DTB read hits
+system.cpu.dtb.read_misses 73387 # DTB read misses
+system.cpu.dtb.write_hits 11701466 # DTB write hits
+system.cpu.dtb.write_misses 17011 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4227 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51369053 # DTB read accesses
-system.cpu.dtb.write_accesses 11786724 # DTB write accesses
+system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51286070 # DTB read accesses
+system.cpu.dtb.write_accesses 11718477 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63064921 # DTB hits
-system.cpu.dtb.misses 90856 # DTB misses
-system.cpu.dtb.accesses 63155777 # DTB accesses
-system.cpu.itb.inst_hits 11599470 # ITB inst hits
-system.cpu.itb.inst_misses 11387 # ITB inst misses
+system.cpu.dtb.hits 62914149 # DTB hits
+system.cpu.dtb.misses 90398 # DTB misses
+system.cpu.dtb.accesses 63004547 # DTB accesses
+system.cpu.itb.inst_hits 11530598 # ITB inst hits
+system.cpu.itb.inst_misses 11503 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2571 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2585 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11610857 # ITB inst accesses
-system.cpu.itb.hits 11599470 # DTB hits
-system.cpu.itb.misses 11387 # DTB misses
-system.cpu.itb.accesses 11610857 # DTB accesses
-system.cpu.numCycles 470965317 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11542101 # ITB inst accesses
+system.cpu.itb.hits 11530598 # DTB hits
+system.cpu.itb.misses 11503 # DTB misses
+system.cpu.itb.accesses 11542101 # DTB accesses
+system.cpu.numCycles 469830472 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued
-system.cpu.iq.rate 0.262043 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued
+system.cpu.iq.rate 0.261848 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 221628 # number of nop insts executed
-system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11537560 # Number of branches executed
-system.cpu.iew.exec_stores 12281337 # Number of stores executed
-system.cpu.iew.exec_rate 0.257635 # Inst execution rate
-system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47183541 # num instructions producing a value
-system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value
+system.cpu.iew.exec_nop 221038 # number of nop insts executed
+system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11477980 # Number of branches executed
+system.cpu.iew.exec_stores 12213052 # Number of stores executed
+system.cpu.iew.exec_rate 0.257448 # Inst execution rate
+system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47051195 # num instructions producing a value
+system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60747621 # Number of instructions committed
-system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60456701 # Number of instructions committed
+system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27514551 # Number of memory references committed
-system.cpu.commit.loads 15716032 # Number of loads committed
-system.cpu.commit.membars 413105 # Number of memory barriers committed
-system.cpu.commit.branches 10023101 # Number of branches committed
+system.cpu.commit.refs 27385892 # Number of memory references committed
+system.cpu.commit.loads 15654083 # Number of loads committed
+system.cpu.commit.membars 403583 # Number of memory barriers committed
+system.cpu.commit.branches 9961154 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69134175 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995982 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68853054 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991222 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 239713879 # The number of ROB reads
-system.cpu.rob.rob_writes 197204165 # The number of ROB writes
-system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60597240 # Number of Instructions Simulated
-system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated
-system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 549724990 # number of integer regfile reads
-system.cpu.int_regfile_writes 88045459 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8276 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2926 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912900 # number of misc regfile writes
-system.cpu.icache.replacements 981280 # number of replacements
-system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use
-system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 10533801 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10533801 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10533801 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10533801 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10533801 # number of overall hits
-system.cpu.icache.overall_hits::total 10533801 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1061888 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1061888 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1061888 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1061888 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1061888 # number of overall misses
-system.cpu.icache.overall_misses::total 1061888 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13967491489 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13967491489 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13967491489 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 13967491489 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 13967491489 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 13967491489 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11595689 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11595689 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11595689 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11595689 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11595689 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11595689 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091576 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 5396 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 1220 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 17.808581 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 610 # average number of cycles each access was blocked
+system.cpu.rob.rob_reads 238273902 # The number of ROB reads
+system.cpu.rob.rob_writes 196332947 # The number of ROB writes
+system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60306320 # Number of Instructions Simulated
+system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated
+system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 547824485 # number of integer regfile reads
+system.cpu.int_regfile_writes 87698031 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8340 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2902 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads
+system.cpu.misc_regfile_writes 831851 # number of misc regfile writes
+system.cpu.icache.replacements 979772 # number of replacements
+system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use
+system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits
+system.cpu.icache.overall_hits::total 10466836 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses
+system.cpu.icache.overall_misses::total 1059904 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 80057 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 80057 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 80057 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 80057 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 80057 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981831 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 981831 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 981831 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 981831 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 981831 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 981831 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11353310491 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11353310491 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11353310491 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11353310491 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11353310491 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11353310491 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 980321 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 980321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 980321 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 980321 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 980321 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11335281493 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11335281493 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11335281493 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11335281493 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11335281493 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11335281493 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084672 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.084672 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.084672 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.406015 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.406015 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085048 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.085048 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.085048 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.826353 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.826353 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 64370 # number of replacements
-system.cpu.l2cache.tagsinuse 51358.666800 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1910788 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 129761 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 14.725441 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2488452468500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 36927.008868 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 28.274765 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 8177.411143 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6225.971675 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.563461 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000431 # Average percentage of cache occupancy
+system.cpu.l2cache.replacements 64384 # number of replacements
+system.cpu.l2cache.tagsinuse 51365.557849 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1909698 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 129778 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 14.715114 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2488155004000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 36926.744718 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 36.464010 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003926 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 8168.761699 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6233.583496 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.563457 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000556 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.124777 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.095001 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.783671 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 78622 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10599 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 968211 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 387222 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1444654 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112968 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112968 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 78622 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 10599 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 968211 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 500190 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1557622 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 78622 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 10599 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 968211 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 500190 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1557622 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 12367 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 10717 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 12367 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143903 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 12367 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143903 # number of overall misses
-system.cpu.l2cache.overall_misses::total 156313 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2982500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 653684500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590050498 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1246835498 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 431500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6675201498 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6675201498 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2982500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 653684500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7265251996 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 7922036996 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2982500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 653684500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7265251996 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 7922036996 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 78663 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10601 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 980578 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 397939 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1467781 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.occ_percent::cpu.inst 0.124645 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.095117 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.783776 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 78725 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10899 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 966625 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 387064 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1443313 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607596 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607596 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 78725 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10899 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 966625 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 499971 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1556220 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 78725 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10899 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 966625 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 499971 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1556220 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12362 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133204 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133204 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 12362 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143927 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156343 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 12362 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143927 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156343 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3708000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 187000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 653051500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 588973999 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1245920499 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 478500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6665784498 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6665784498 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3708000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 187000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 653051500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7254758497 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 7911704997 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3708000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 187000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 653051500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7254758497 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 7911704997 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 78776 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10902 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 978987 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 397787 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1466452 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607596 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607596 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 246154 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 246154 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 78663 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 10601 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 980578 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 644093 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1713935 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 78663 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 10601 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 980578 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 644093 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1713935 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000521 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026931 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.015756 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986158 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986158 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541068 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.541068 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000521 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.223420 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.091201 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000521 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.223420 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.091201 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72743.902439 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52857.160184 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55057.431931 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 53912.548017 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 147.723382 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 147.723382 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50119.393164 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50119.393164 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 50680.602356 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 50680.602356 # average overall miss latency
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246111 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246111 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 78776 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10902 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 978987 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 643898 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1712563 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 78776 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10902 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 978987 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 643898 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1712563 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000647 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000275 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012627 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026957 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.015779 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986833 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986833 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541235 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541235 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000647 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000275 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012627 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223525 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.091292 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000647 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000275 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012627 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223525 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.091292 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72705.882353 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62333.333333 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52827.333765 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54926.233237 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 53845.045119 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.701676 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.701676 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50041.924402 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50041.924402 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72705.882353 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52827.333765 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50405.820291 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 50604.792009 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72705.882353 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52827.333765 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50405.820291 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 50604.792009 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 59111 # number of writebacks
-system.cpu.l2cache.writebacks::total 59111 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12355 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 23054 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12355 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143842 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 156240 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12355 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143842 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 156240 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2461077 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 497040130 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 451732824 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 951327033 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5024401862 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5024401862 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2461077 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 497040130 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5476134686 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 5975728895 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2461077 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 497040130 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5476134686 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 5975728895 # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks 59120 # number of writebacks
+system.cpu.l2cache.writebacks::total 59120 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12349 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10661 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133204 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133204 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12349 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143865 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156268 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12349 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143865 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3058596 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149004 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 496430614 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 450664827 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 950303041 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 40004 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 40004 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5014619823 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5014619823 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3058596 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149004 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 496430614 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5465284650 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 5964922864 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3058596 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149004 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 496430614 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5465284650 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 5964922864 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167008598530 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167012943685 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18318853408 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18318853408 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167009478530 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167013823685 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18374986550 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18374986550 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185327451938 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185331797093 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026778 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015707 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986158 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986158 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541068 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541068 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.091159 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.091159 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40229.876973 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42392.344595 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41265.161490 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185384465080 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185388810235 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026801 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015728 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986833 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986833 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541235 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541235 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49668 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40200.065916 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42272.284682 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41202.872052 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37724.699758 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37724.699758 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.165453 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.165453 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 643581 # number of replacements
-system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 643386 # number of replacements
+system.cpu.dcache.tagsinuse 511.994223 # Cycle average of tags in use
+system.cpu.dcache.total_refs 21524162 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 643898 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33.427906 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 511.994223 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21105442 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21105442 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21105442 # number of overall hits
-system.cpu.dcache.overall_hits::total 21105442 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 731834 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 731834 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2961255 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2961255 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13603 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13603 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3693089 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3693089 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3693089 # number of overall misses
-system.cpu.dcache.overall_misses::total 3693089 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9564740000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9564740000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 104026861731 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 104026861731 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180604500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 180604500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 244000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 244000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 113591601731 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 113591601731 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 113591601731 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 113591601731 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 296044 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285756 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285756 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24798531 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24798531 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24798531 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24798531 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050305 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050305 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288884 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.288884 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35129.315689 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35129.315689 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13276.813938 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13276.813938 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15250 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15250 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30757.883639 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30757.883639 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32046 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 14482 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.377752 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 57.697211 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data 13769851 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13769851 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7260574 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7260574 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 243031 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 243031 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21030425 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21030425 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21030425 # number of overall hits
+system.cpu.dcache.overall_hits::total 21030425 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 731035 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 731035 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2961528 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2961528 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13553 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13553 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3692563 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3692563 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3692563 # number of overall misses
+system.cpu.dcache.overall_misses::total 3692563 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9558145500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9558145500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 103975545233 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 103975545233 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180615500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 180615500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 229500 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 229500 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 113533690733 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 113533690733 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 113533690733 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 113533690733 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14500886 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14500886 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10222102 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10222102 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256584 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 256584 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247612 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247612 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24722988 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24722988 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24722988 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24722988 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050413 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050413 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289718 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052821 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052821 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks
-system.cpu.dcache.writebacks::total 607832 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345983 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 345983 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks
+system.cpu.dcache.writebacks::total 607596 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.401421 # Number of seconds simulated
-sim_ticks 2401421439000 # Number of ticks simulated
-final_tick 2401421439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.401290 # Number of seconds simulated
+sim_ticks 2401290348000 # Number of ticks simulated
+final_tick 2401290348000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75201 # Simulator instruction rate (inst/s)
-host_op_rate 96555 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2986582566 # Simulator tick rate (ticks/s)
-host_mem_usage 393856 # Number of bytes of host memory used
-host_seconds 804.07 # Real time elapsed on the host
-sim_insts 60466509 # Number of instructions simulated
-sim_ops 77636591 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 196762 # Simulator instruction rate (inst/s)
+host_op_rate 252717 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7831753482 # Simulator tick rate (ticks/s)
+host_mem_usage 401668 # Number of bytes of host memory used
+host_seconds 306.61 # Real time elapsed on the host
+sim_insts 60329082 # Number of instructions simulated
+sim_ops 77485321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 478816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 7027600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 486624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 7022480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 73664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 716876 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 1216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 218496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1332556 # Number of bytes read from this memory
-system.physmem.bytes_read::total 124668680 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 478816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 73664 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 218496 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 770976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3748032 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1052216 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 199484 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data 1764144 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6763876 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 77504 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 723200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 203648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1332732 # Number of bytes read from this memory
+system.physmem.bytes_read::total 124666476 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 486624 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 77504 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 203648 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 767776 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3747584 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1052224 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data 1764136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6763400 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 13684 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 109840 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 13806 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 109760 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1151 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 11204 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 19 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 3414 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 20824 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 14512526 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58563 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 263054 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 49871 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data 441036 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812524 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47812962 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 1211 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 11300 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 3182 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 20838 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 14512500 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 58556 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 263056 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data 441034 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 812510 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47815572 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 199389 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2926433 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 202651 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2924461 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 30675 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 298522 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 506 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 90986 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 554903 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51914536 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 199389 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 30675 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 90986 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 321050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1560756 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 438164 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 83069 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data 734625 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2816613 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1560756 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47812962 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 32276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 301171 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 400 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 84808 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 555007 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51916452 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 202651 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 32276 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 84808 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 319735 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1560654 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 438191 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 83062 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data 734662 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2816569 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1560654 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47815572 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 199389 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3364597 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 202651 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3362652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 30675 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 381591 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 506 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 90986 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1289528 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54731150 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 12619527 # Total number of read requests seen
-system.physmem.writeReqs 508095 # Total number of write requests seen
-system.physmem.cpureqs 56153 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 807649728 # Total number of bytes read from memory
-system.physmem.bytesWritten 32518080 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 103006296 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 3063660 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2356 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 788374 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 788516 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 788173 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 788282 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 788267 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 788268 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 788411 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 789077 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 789904 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 789864 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 789609 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 789636 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 788668 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 788108 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 788208 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 788160 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 30462 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 31339 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 31367 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 31519 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 31434 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 31463 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 31715 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 32144 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 32667 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 32642 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 32415 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 32370 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 31797 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 31479 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 31921 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 31361 # Track writes on a per bank basis
+system.physmem.bw_total::cpu1.inst 32276 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 384233 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 400 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 84808 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1289668 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54733021 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 12619459 # Total number of read requests seen
+system.physmem.writeReqs 508288 # Total number of write requests seen
+system.physmem.cpureqs 56279 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 807645376 # Total number of bytes read from memory
+system.physmem.bytesWritten 32530432 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 103001404 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 3076552 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 788367 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 788540 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 788340 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 788430 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 788204 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 788361 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 788387 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 789073 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 789810 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 789739 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 789543 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 789483 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 788664 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 788174 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 788221 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 788123 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 30454 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 30491 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 30890 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 31526 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 31443 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 31484 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 31752 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 32161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 32686 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 32676 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 32416 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 32334 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 31816 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 31518 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 32440 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 32201 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 317403 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2400386249000 # Total gap between requests
+system.physmem.numWrRetry 316906 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2400255112000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 6 # Categorize read packet sizes
+system.physmem.readPktSize::2 15 # Categorize read packet sizes
system.physmem.readPktSize::3 12582912 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 36609 # Categorize read packet sizes
+system.physmem.readPktSize::6 36532 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 808310 # categorize write packet sizes
+system.physmem.writePktSize::2 807804 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 17188 # categorize write packet sizes
+system.physmem.writePktSize::6 17390 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 2356 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 2357 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 817282 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 792530 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 787018 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 816081 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2309777 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2310026 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 4565188 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 24972 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 24597 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 24594 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 24587 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 47867 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 24582 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 47847 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1291 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 817349 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 792132 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 786840 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 815906 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2309875 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2310166 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 4565473 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 24979 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 24626 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 24603 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 24600 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 47884 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 24589 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 47866 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1286 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1284 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3518 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3620 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3760 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3937 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4056 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4161 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4250 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4415 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 22096 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 22090 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 22088 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 22084 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 22079 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 22076 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 22070 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 22068 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 22064 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 22061 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 22055 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 22051 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 22047 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 22044 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 18625 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 18585 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 18515 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 18188 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 18065 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17957 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17859 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17690 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3535 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3581 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3654 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3796 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3987 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4204 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4296 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4452 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 22104 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 22101 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 22095 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 22093 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 22091 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 22082 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 22076 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 22075 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 22071 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 22068 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 22063 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 22058 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 22054 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 22052 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 18615 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 18566 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 18491 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 18346 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 18150 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 18019 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17918 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17662 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 234691241923 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 297448055923 # Sum of mem lat for all requests
-system.physmem.totBusLat 50478100000 # Total cycles spent in databus access
-system.physmem.totBankLat 12278714000 # Total cycles spent in bank access
-system.physmem.avgQLat 18597.47 # Average queueing delay per request
-system.physmem.avgBankLat 972.99 # Average bank access latency per request
+system.physmem.totQLat 234677385926 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 297433333926 # Sum of mem lat for all requests
+system.physmem.totBusLat 50477836000 # Total cycles spent in databus access
+system.physmem.totBankLat 12278112000 # Total cycles spent in bank access
+system.physmem.avgQLat 18596.47 # Average queueing delay per request
+system.physmem.avgBankLat 972.95 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 23570.46 # Average memory access latency
-system.physmem.avgRdBW 336.32 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 13.54 # Average achieved write bandwidth in MB/s
+system.physmem.avgMemAccLat 23569.42 # Average memory access latency
+system.physmem.avgRdBW 336.34 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 13.55 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 42.89 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.28 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.19 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.12 # Average read queue length over time
-system.physmem.avgWrQLen 0.40 # Average write queue length over time
-system.physmem.readRowHits 12589945 # Number of row buffer hits during reads
-system.physmem.writeRowHits 499132 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 0.39 # Average write queue length over time
+system.physmem.readRowHits 12589970 # Number of row buffer hits during reads
+system.physmem.writeRowHits 499207 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.77 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.24 # Row buffer hit rate for writes
-system.physmem.avgGap 182850.04 # Average gap between requests
-system.l2c.replacements 63371 # number of replacements
-system.l2c.tagsinuse 50440.930838 # Cycle average of tags in use
-system.l2c.total_refs 1764263 # Total number of references to valid blocks.
-system.l2c.sampled_refs 128761 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.701843 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2374519462500 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36775.045658 # Average occupied blocks per requestor
+system.physmem.writeRowHitRate 98.21 # Row buffer hit rate for writes
+system.physmem.avgGap 182838.31 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 63336 # number of replacements
+system.l2c.tagsinuse 50450.717856 # Cycle average of tags in use
+system.l2c.total_refs 1763394 # Total number of references to valid blocks.
+system.l2c.sampled_refs 128728 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.698605 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 2374386486500 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 36835.436413 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4782.596749 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 3401.388842 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 0.993264 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 624.225892 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 1084.430901 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.dtb.walker 16.710319 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.itb.walker 0.970933 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst 2110.368967 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data 1644.199171 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.561143 # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu0.inst 4889.589414 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 3789.162794 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 693.988921 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 773.305444 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.dtb.walker 12.782672 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst 1890.141167 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data 1565.317572 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.562064 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.072977 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.051901 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.074609 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.057818 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.009525 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.016547 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.dtb.walker 0.000255 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst 0.032202 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.data 0.025088 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.769668 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 8850 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 3418 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 467065 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 185990 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 2576 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 1139 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 127160 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 58153 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 32653 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 4529 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 285923 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 129158 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1306614 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 597611 # number of Writeback hits
-system.l2c.Writeback_hits::total 597611 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
+system.l2c.occ_percent::cpu1.inst 0.010589 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.011800 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.dtb.walker 0.000195 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst 0.028841 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data 0.023885 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.769817 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 8682 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 3261 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 465917 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 189493 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 2536 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 1094 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 125655 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 58631 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker 31888 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker 4603 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 288441 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 125210 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1305411 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 597807 # number of Writeback hits
+system.l2c.Writeback_hits::total 597807 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data 6 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 62389 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 18579 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 32685 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 113653 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 8850 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 3418 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 467065 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 248379 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 2576 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 1139 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 127160 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 76732 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker 32653 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker 4529 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 285923 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 161843 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1420267 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 8850 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 3418 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 467065 # number of overall hits
-system.l2c.overall_hits::cpu0.data 248379 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 2576 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 1139 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 127160 # number of overall hits
-system.l2c.overall_hits::cpu1.data 76732 # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker 32653 # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker 4529 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 285923 # number of overall hits
-system.l2c.overall_hits::cpu2.data 161843 # number of overall hits
-system.l2c.overall_hits::total 1420267 # number of overall hits
+system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 35 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu2.data 5 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 62176 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 18861 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 32633 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 113670 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 8682 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 3261 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 465917 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 251669 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 2536 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 1094 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 125655 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 77492 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker 31888 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker 4603 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 288441 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 157843 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1419081 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 8682 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 3261 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 465917 # number of overall hits
+system.l2c.overall_hits::cpu0.data 251669 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 2536 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 1094 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 125655 # number of overall hits
+system.l2c.overall_hits::cpu1.data 77492 # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker 31888 # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker 4603 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 288441 # number of overall hits
+system.l2c.overall_hits::cpu2.data 157843 # number of overall hits
+system.l2c.overall_hits::total 1419081 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 7068 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 5964 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 7190 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6394 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1151 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 1562 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker 19 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 3416 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 2619 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 21805 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 1429 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 489 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 987 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 104629 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 9911 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 18825 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 133365 # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.inst 1211 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 1217 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker 15 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 3184 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 2540 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 21755 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 1426 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 500 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 978 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 104120 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 10355 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 18899 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 133374 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 7068 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 110593 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 7190 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 110514 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1151 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 11473 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker 19 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 3416 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 21444 # number of demand (read+write) misses
-system.l2c.demand_misses::total 155170 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 1211 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 11572 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker 15 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 3184 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 21439 # number of demand (read+write) misses
+system.l2c.demand_misses::total 155129 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 7068 # number of overall misses
-system.l2c.overall_misses::cpu0.data 110593 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 7190 # number of overall misses
+system.l2c.overall_misses::cpu0.data 110514 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 1151 # number of overall misses
-system.l2c.overall_misses::cpu1.data 11473 # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker 19 # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 3416 # number of overall misses
-system.l2c.overall_misses::cpu2.data 21444 # number of overall misses
-system.l2c.overall_misses::total 155170 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 1211 # number of overall misses
+system.l2c.overall_misses::cpu1.data 11572 # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker 15 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 3184 # number of overall misses
+system.l2c.overall_misses::cpu2.data 21439 # number of overall misses
+system.l2c.overall_misses::total 155129 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 59181000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 81935500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1348500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker 137000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 197768500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 150939499 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 491378999 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 91500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 137000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 228500 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 442251500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 1015620500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 1457872000 # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 63123000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 67640500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1041500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 185369000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 147930500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 465173500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 69000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data 92000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 161000 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 459040000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 1013895000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 1472935000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 59181000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 524187000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker 1348500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker 137000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 197768500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 1166559999 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 1949250999 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 63123000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 526680500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker 1041500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 185369000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 1161825500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 1938108500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 59181000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 524187000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker 1348500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker 137000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 197768500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 1166559999 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 1949250999 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 8851 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 3420 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 474133 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 191954 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 2577 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 1139 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 128311 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 59715 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker 32672 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker 4531 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 289339 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 131777 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1328419 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 597611 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 597611 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 1442 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 493 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 1001 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data 6 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 167018 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 28490 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 51510 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 247018 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 8851 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 3420 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 474133 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 358972 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 2577 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 1139 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 128311 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 88205 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker 32672 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker 4531 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 289339 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 183287 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1575437 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 8851 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 3420 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 474133 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 358972 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 2577 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 1139 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 128311 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 88205 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker 32672 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker 4531 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 289339 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 183287 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1575437 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000585 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.014907 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.031070 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.008970 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.026158 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000441 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.011806 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.019874 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990985 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991886 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.986014 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.989441 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.626453 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.347876 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.365463 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.539900 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000585 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.014907 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.308083 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.008970 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.130072 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker 0.000441 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.011806 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.116997 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.098493 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000585 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.014907 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.308083 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.008970 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.130072 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker 0.000441 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.011806 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.116997 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.098493 # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu1.inst 63123000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 526680500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker 1041500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 185369000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 1161825500 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 1938108500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 8683 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 3263 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 473107 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 195887 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 2537 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 1094 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 126866 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 59848 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker 31903 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker 4603 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 291625 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 127750 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1327166 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 597807 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 597807 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 1440 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 504 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 995 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu2.data 7 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 166296 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 29216 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 51532 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 247044 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 8683 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 3263 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 473107 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 362183 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 2537 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 1094 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 126866 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 89064 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker 31903 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker 4603 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 291625 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 179282 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1574210 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 8683 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 3263 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 473107 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 362183 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 2537 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 1094 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 126866 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 89064 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker 31903 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker 4603 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 291625 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 179282 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1574210 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000613 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015197 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.032641 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.009546 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.020335 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000470 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.010918 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.019883 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.016392 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990278 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992063 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.982915 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.988091 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.285714 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.626112 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.354429 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.366743 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.539880 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000613 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015197 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.305133 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.009546 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.129929 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000470 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.010918 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.119583 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.098544 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000613 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015197 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.305133 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.009546 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.129929 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000470 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.010918 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.119583 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.098544 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51417.028671 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52455.505762 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 68500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 57894.759953 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 57632.492936 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 22535.152442 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 187.116564 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 138.804458 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 78.657487 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44622.288366 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53950.624170 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 10931.443782 # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52124.690339 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 55579.704191 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 69433.333333 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 58218.907035 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 58240.354331 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 21382.371869 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 138 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 94.069530 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 55.440771 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44330.275229 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53648.076618 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 11043.644189 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 51417.028671 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 45688.747494 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 57894.759953 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 54400.298405 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 12562.035181 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52124.690339 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 45513.351193 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 69433.333333 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 58218.907035 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 54192.149820 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 12493.527967 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 51417.028671 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 45688.747494 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 57894.759953 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 54400.298405 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 12562.035181 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52124.690339 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 45513.351193 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 69433.333333 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 58218.907035 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 54192.149820 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 12493.527967 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 58563 # number of writebacks
-system.l2c.writebacks::total 58563 # number of writebacks
+system.l2c.writebacks::writebacks 58556 # number of writebacks
+system.l2c.writebacks::total 58556 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.data 15 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.data 11 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data 15 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data 11 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data 15 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data 11 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 1151 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 1562 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 19 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 3414 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 2604 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 8753 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 489 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 987 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 1476 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 9911 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 18825 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 28736 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 1211 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 1217 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 15 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst 3182 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data 2529 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 8155 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 500 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 978 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 1478 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 2 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 10355 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 18899 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 29254 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 1151 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 11473 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 19 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 3414 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 21429 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 37489 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 1211 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 11572 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker 15 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 3182 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 21428 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 37409 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 1151 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 11473 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 19 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 3414 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 21429 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 37489 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 1211 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 11572 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker 15 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 3182 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 21428 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 37409 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56002 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 44565780 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 61910606 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1106535 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 112004 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 154485385 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 117079807 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 379316119 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4947956 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9870987 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 14818943 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 315063958 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 780713218 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 1095777176 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 47755394 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 52091914 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 849528 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 145023955 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 115293698 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 361070491 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5052469 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9788977 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 14841446 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 20002 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 326338340 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 777736991 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 1104075331 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 44565780 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 376974564 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1106535 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 112004 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 154485385 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 897793025 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 1475093295 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 47755394 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 378430254 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 849528 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 145023955 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 893030689 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 1465145822 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56002 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 44565780 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 376974564 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1106535 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 112004 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 154485385 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 897793025 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 1475093295 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25233133000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26572368004 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 51805501004 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 640106868 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 7144945536 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 7785052404 # number of WriteReq MSHR uncacheable cycles
-system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76004 # number of LoadLockedReq MSHR uncacheable cycles
-system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76004 # number of LoadLockedReq MSHR uncacheable cycles
-system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
-system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25873239868 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 33717313540 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 59590553408 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026158 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.019761 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.006589 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991886 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986014 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.502725 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347876 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365463 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.116332 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.130072 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.116915 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.023796 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.130072 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.116915 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.023796 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu1.inst 47755394 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 378430254 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 849528 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 145023955 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 893030689 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 1465145822 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25275455000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26580183526 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 51855638526 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 651827364 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 7180784034 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 7832611398 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25927282364 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 33760967560 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 59688249924 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009546 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020335 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000470 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010911 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.019796 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.006145 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992063 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.982915 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.502892 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.354429 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366743 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.118416 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009546 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.129929 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000470 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010911 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.119521 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.023764 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009546 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.129929 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000470 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010911 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.119521 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.023764 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39635.471191 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 44961.523425 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 43335.555695 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10118.519427 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10039.934282 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 31789.320755 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41472.149695 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 38132.557628 # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39434.677126 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42803.544782 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56635.200000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 45576.352923 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 45588.650850 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 44275.964562 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.938000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10009.178937 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10041.573748 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 31515.049734 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41152.282713 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 37741.003999 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 32857.540661 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41896.169910 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 39347.363093 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39434.677126 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 32702.234186 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56635.200000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45576.352923 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41675.876843 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 39165.597102 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 32857.540661 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41896.169910 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 39347.363093 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39434.677126 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 32702.234186 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56635.200000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45576.352923 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41675.876843 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 39165.597102 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
-system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
-system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
-system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7902224 # DTB read hits
-system.cpu0.dtb.read_misses 6242 # DTB read misses
-system.cpu0.dtb.write_hits 6537817 # DTB write hits
-system.cpu0.dtb.write_misses 1923 # DTB write misses
+system.cpu0.dtb.read_hits 7853690 # DTB read hits
+system.cpu0.dtb.read_misses 6243 # DTB read misses
+system.cpu0.dtb.write_hits 6487171 # DTB write hits
+system.cpu0.dtb.write_misses 1921 # DTB write misses
system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 5670 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7908466 # DTB read accesses
-system.cpu0.dtb.write_accesses 6539740 # DTB write accesses
+system.cpu0.dtb.read_accesses 7859933 # DTB read accesses
+system.cpu0.dtb.write_accesses 6489092 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14440041 # DTB hits
-system.cpu0.dtb.misses 8165 # DTB misses
-system.cpu0.dtb.accesses 14448206 # DTB accesses
-system.cpu0.itb.inst_hits 31853127 # ITB inst hits
+system.cpu0.dtb.hits 14340861 # DTB hits
+system.cpu0.dtb.misses 8164 # DTB misses
+system.cpu0.dtb.accesses 14349025 # DTB accesses
+system.cpu0.itb.inst_hits 31512097 # ITB inst hits
system.cpu0.itb.inst_misses 3518 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 31856645 # ITB inst accesses
-system.cpu0.itb.hits 31853127 # DTB hits
+system.cpu0.itb.inst_accesses 31515615 # ITB inst accesses
+system.cpu0.itb.hits 31512097 # DTB hits
system.cpu0.itb.misses 3518 # DTB misses
-system.cpu0.itb.accesses 31856645 # DTB accesses
-system.cpu0.numCycles 112931028 # number of cpu cycles simulated
+system.cpu0.itb.accesses 31515615 # DTB accesses
+system.cpu0.numCycles 112564012 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 31362077 # Number of instructions committed
-system.cpu0.committedOps 41448320 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 36567470 # Number of integer alu accesses
+system.cpu0.committedInsts 31022111 # Number of instructions committed
+system.cpu0.committedOps 41078367 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 36251649 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5105 # Number of float alu accesses
-system.cpu0.num_func_calls 1216492 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4268853 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 36567470 # number of integer instructions
+system.cpu0.num_func_calls 1198861 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4217068 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 36251649 # number of integer instructions
system.cpu0.num_fp_insts 5105 # number of float instructions
-system.cpu0.num_int_register_reads 186633277 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 38778240 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 184966774 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 38342244 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3615 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written
-system.cpu0.num_mem_refs 15097186 # number of memory refs
-system.cpu0.num_load_insts 8269911 # Number of load instructions
-system.cpu0.num_store_insts 6827275 # Number of store instructions
-system.cpu0.num_idle_cycles 13401980962.617596 # Number of idle cycles
-system.cpu0.num_busy_cycles -13289049934.617596 # Number of busy cycles
-system.cpu0.not_idle_fraction -117.674037 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 118.674037 # Percentage of idle cycles
+system.cpu0.num_mem_refs 15003639 # number of memory refs
+system.cpu0.num_load_insts 8220534 # Number of load instructions
+system.cpu0.num_store_insts 6783105 # Number of store instructions
+system.cpu0.num_idle_cycles 13359160341.338484 # Number of idle cycles
+system.cpu0.num_busy_cycles -13246596329.338484 # Number of busy cycles
+system.cpu0.not_idle_fraction -117.680563 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 118.680563 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 84468 # number of quiesce instructions executed
-system.cpu0.icache.replacements 892780 # number of replacements
-system.cpu0.icache.tagsinuse 511.591234 # Cycle average of tags in use
-system.cpu0.icache.total_refs 43441886 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 893292 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 48.631227 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 8001805000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 491.376976 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 7.109245 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu2.inst 13.105014 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.959721 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu1.inst 0.013885 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu2.inst 0.025596 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.999202 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 31380980 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 8436238 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 3624668 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 43441886 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 31380980 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 8436238 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 3624668 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 43441886 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 31380980 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 8436238 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 3624668 # number of overall hits
-system.cpu0.icache.overall_hits::total 43441886 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 474853 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 128587 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 314740 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 918180 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 474853 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 128587 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 314740 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 918180 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 474853 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 128587 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 314740 # number of overall misses
-system.cpu0.icache.overall_misses::total 918180 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1722310000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4209726988 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5932036988 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 1722310000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 4209726988 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5932036988 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 1722310000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 4209726988 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5932036988 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 31855833 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 8564825 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 3939408 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 44360066 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 31855833 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 8564825 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 3939408 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 44360066 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 31855833 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 8564825 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 3939408 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 44360066 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014906 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015013 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.079895 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.020698 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014906 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015013 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.079895 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.020698 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014906 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015013 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.079895 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.020698 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13394.122267 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13375.252551 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 6460.647137 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13394.122267 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13375.252551 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 6460.647137 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13394.122267 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13375.252551 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 6460.647137 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 3469 # number of cycles access was blocked
+system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed
+system.cpu0.icache.replacements 892592 # number of replacements
+system.cpu0.icache.tagsinuse 511.602515 # Cycle average of tags in use
+system.cpu0.icache.total_refs 43093947 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 893104 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 48.251880 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 8108198000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 496.911233 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst 7.172611 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu2.inst 7.518672 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.970530 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst 0.014009 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu2.inst 0.014685 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 31040977 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 8399762 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 3653208 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 43093947 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 31040977 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 8399762 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 3653208 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 43093947 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 31040977 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 8399762 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 3653208 # number of overall hits
+system.cpu0.icache.overall_hits::total 43093947 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 473826 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 127142 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 316554 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 917522 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 473826 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 127142 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 316554 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 917522 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 473826 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 127142 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 316554 # number of overall misses
+system.cpu0.icache.overall_misses::total 917522 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1706895500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4221661989 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5928557489 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 1706895500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 4221661989 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5928557489 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 1706895500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 4221661989 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5928557489 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 31514803 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 8526904 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 3969762 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 44011469 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 31514803 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 8526904 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 3969762 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 44011469 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 31514803 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 8526904 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 3969762 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 44011469 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015035 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014911 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.079741 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.020847 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015035 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014911 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.079741 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.020847 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015035 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014911 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.079741 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.020847 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13425.111293 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13336.309094 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 6461.488105 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13425.111293 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13336.309094 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 6461.488105 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13425.111293 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13336.309094 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 6461.488105 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 3186 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.394191 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.694581 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24876 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 24876 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 24876 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 24876 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 24876 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 24876 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128587 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 289864 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 418451 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 128587 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 289864 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 418451 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 128587 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 289864 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 418451 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1465136000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3427061488 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4892197488 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1465136000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3427061488 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4892197488 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1465136000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3427061488 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4892197488 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009433 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.009433 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.009433 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11691.207544 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11691.207544 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11691.207544 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24400 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 24400 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst 24400 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 24400 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst 24400 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 24400 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 127142 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 292154 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 419296 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 127142 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 292154 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 419296 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 127142 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 292154 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 419296 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1452611500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3441945989 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4894557489 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1452611500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3441945989 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4894557489 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1452611500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3441945989 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4894557489 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014911 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.073595 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009527 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014911 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.073595 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.009527 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014911 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.073595 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.009527 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11425.111293 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11781.272853 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11673.274939 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11425.111293 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11781.272853 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11673.274939 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11425.111293 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11781.272853 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11673.274939 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 629952 # number of replacements
+system.cpu0.dcache.replacements 630017 # number of replacements
system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 23322161 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 630464 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 36.992058 # Average number of references to valid blocks.
+system.cpu0.dcache.total_refs 23260459 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 630529 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 36.890387 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 497.280136 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu1.data 8.191597 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu2.data 6.525382 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.971250 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu1.data 0.015999 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu2.data 0.012745 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::cpu0.data 497.365080 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data 8.139667 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu2.data 6.492369 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.971416 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data 0.015898 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu2.data 0.012680 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 6763167 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 1877822 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 4718068 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 13359057 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 5963557 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 1365617 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 2102817 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 9431991 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135570 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 32797 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 91307 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 259674 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142092 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34425 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data 91924 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 268441 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 12726724 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 3243439 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 6820885 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 22791048 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 12726724 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 3243439 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 6820885 # number of overall hits
-system.cpu0.dcache.overall_hits::total 22791048 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 185432 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 58086 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 273913 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 517431 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 168460 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 28983 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 595876 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 793319 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6522 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1629 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3810 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 11961 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data 6 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 353892 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 87069 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 869789 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1310750 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 353892 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 87069 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 869789 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1310750 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 824588500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3876286000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 4700874500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 726126000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19133055918 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 19859181918 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 21335000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 51226000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 72561000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 78000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 78000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 1550714500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 23009341918 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 24560056418 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 1550714500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 23009341918 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 24560056418 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 6948599 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 1935908 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 4991981 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 13876488 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 6132017 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 1394600 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 2698693 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 10225310 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142092 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34426 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 95117 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 271635 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142092 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34425 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 91930 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 268447 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 13080616 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 3330508 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 7690674 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 24101798 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 13080616 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 3330508 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 7690674 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 24101798 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026686 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030005 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.054871 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.037288 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027472 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020782 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220802 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.077584 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045900 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047319 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.040056 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.044033 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000065 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000022 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027055 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026143 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.113097 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.054384 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027055 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026143 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.113097 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.054384 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14195.993871 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14151.522564 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 9085.026796 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25053.514129 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32109.123237 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25033.034527 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.992020 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13445.144357 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6066.466015 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17810.179283 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26453.935285 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 18737.407147 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17810.179283 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26453.935285 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18737.407147 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 6963 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 952 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 771 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.031128 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 20.695652 # average number of cycles each access was blocked
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6715363 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 1862593 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 4768116 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 13346072 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 5918280 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 1362335 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 2145174 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 9425789 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131141 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 32944 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 74119 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 238204 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137686 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34552 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data 75151 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 247389 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 12633643 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 3224928 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 6913290 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 22771861 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 12633643 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 3224928 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 6913290 # number of overall hits
+system.cpu0.dcache.overall_hits::total 22771861 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 189342 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 58240 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 256014 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 503596 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 167736 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 29720 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 593106 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 790562 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6545 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1608 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3821 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 11974 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 357078 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 87960 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 849120 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1294158 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 357078 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 87960 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 849120 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1294158 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 815877500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3620904500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 4436782000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 748178500 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18896011913 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 19644190413 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 21031500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 51388500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 72420000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 115000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 115000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 1564056000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 22516916413 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 24080972413 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 1564056000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 22516916413 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 24080972413 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 6904705 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 1920833 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 5024130 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 13849668 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 6086016 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 1392055 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 2738280 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 10216351 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137686 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34552 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77940 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 250178 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137686 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34552 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 75158 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 247396 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 12990721 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 3312888 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 7762410 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 24066019 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 12990721 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 3312888 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 7762410 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 24066019 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027422 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030320 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.050957 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.036362 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027561 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021350 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.216598 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.077382 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047536 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046539 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.049025 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047862 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000093 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000028 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027487 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026551 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.109389 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.053775 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027487 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026551 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.109389 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.053775 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14008.885646 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14143.384737 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 8810.201034 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25174.242934 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31859.417900 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 24848.386860 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13079.291045 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13448.966239 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6048.104226 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16428.571429 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16428.571429 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17781.446112 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26517.943769 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 18607.443923 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17781.446112 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26517.943769 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18607.443923 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 6254 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 1492 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 649 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 40 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.636364 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 37.300000 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 597611 # number of writebacks
-system.cpu0.dcache.writebacks::total 597611 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145491 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 145491 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 543392 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 543392 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 428 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 428 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 688883 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 688883 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 688883 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 688883 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58086 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 128422 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 186508 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28983 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52484 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 81467 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1629 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3382 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5011 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 6 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 87069 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 180906 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 267975 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 87069 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 180906 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 267975 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 708416500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1664999000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2373415500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 668160000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1456004992 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2124164992 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 18077000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39418000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57495000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 66000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1376576500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3121003992 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 4497580492 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1376576500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3121003992 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 4497580492 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27568021500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29009742000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56577763500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1272962000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 12893978360 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14166940360 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles
-system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840983500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41903720360 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70744703860 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030005 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.025726 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013441 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020782 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019448 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007967 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047319 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.035556 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018448 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000065 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000022 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026143 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023523 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.011118 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026143 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.023523 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.011118 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12195.993871 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12965.060504 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.542604 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23053.514129 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27741.883088 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26073.931678 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11096.992020 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11655.233590 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11473.757733 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15810.179283 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17252.075619 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16783.582394 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15810.179283 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17252.075619 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16783.582394 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 597807 # number of writebacks
+system.cpu0.dcache.writebacks::total 597807 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 131637 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 131637 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 540605 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 540605 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 422 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 422 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 672242 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 672242 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 672242 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 672242 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58240 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 124377 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 182617 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29720 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52501 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 82221 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1608 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3399 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5007 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 87960 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 176878 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 264838 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 87960 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 176878 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 264838 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 699397500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1604351000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2303748500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 688738500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1452391492 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2141129992 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 17815500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39577500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57393000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 101000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 101000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1388136000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3056742492 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 4444878492 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1388136000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3056742492 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 4444878492 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27612956500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29018137000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56631093500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1285303000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 12932223922 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14217526922 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28898259500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41950360922 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70848620422 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030320 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.024756 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013186 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021350 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019173 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008048 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046539 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043610 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020014 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026551 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.022786 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.011005 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026551 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.022786 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.011005 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12008.885646 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12899.097100 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12615.191904 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23174.242934 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27664.072913 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26041.157271 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11079.291045 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11643.865843 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11462.552427 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14428.571429 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14428.571429 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15781.446112 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17281.643234 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16783.386417 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15781.446112 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17281.643234 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16783.386417 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 2149941 # DTB read hits
-system.cpu1.dtb.read_misses 2094 # DTB read misses
-system.cpu1.dtb.write_hits 1479770 # DTB write hits
+system.cpu1.dtb.read_hits 2135190 # DTB read hits
+system.cpu1.dtb.read_misses 2107 # DTB read misses
+system.cpu1.dtb.write_hits 1477401 # DTB write hits
system.cpu1.dtb.write_misses 382 # DTB write misses
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1681 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1694 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 46 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 2152035 # DTB read accesses
-system.cpu1.dtb.write_accesses 1480152 # DTB write accesses
+system.cpu1.dtb.read_accesses 2137297 # DTB read accesses
+system.cpu1.dtb.write_accesses 1477783 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 3629711 # DTB hits
-system.cpu1.dtb.misses 2476 # DTB misses
-system.cpu1.dtb.accesses 3632187 # DTB accesses
-system.cpu1.itb.inst_hits 8564825 # ITB inst hits
+system.cpu1.dtb.hits 3612591 # DTB hits
+system.cpu1.dtb.misses 2489 # DTB misses
+system.cpu1.dtb.accesses 3615080 # DTB accesses
+system.cpu1.itb.inst_hits 8526904 # ITB inst hits
system.cpu1.itb.inst_misses 1128 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8565953 # ITB inst accesses
-system.cpu1.itb.hits 8564825 # DTB hits
+system.cpu1.itb.inst_accesses 8528032 # ITB inst accesses
+system.cpu1.itb.hits 8526904 # DTB hits
system.cpu1.itb.misses 1128 # DTB misses
-system.cpu1.itb.accesses 8565953 # DTB accesses
-system.cpu1.numCycles 573618226 # number of cpu cycles simulated
+system.cpu1.itb.accesses 8528032 # DTB accesses
+system.cpu1.numCycles 573624739 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 8360582 # Number of instructions committed
-system.cpu1.committedOps 10552123 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 9474069 # Number of integer alu accesses
+system.cpu1.committedInsts 8322298 # Number of instructions committed
+system.cpu1.committedOps 10507258 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 9429869 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses
-system.cpu1.num_func_calls 304948 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1122653 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 9474069 # number of integer instructions
+system.cpu1.num_func_calls 301953 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1117858 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 9429869 # number of integer instructions
system.cpu1.num_fp_insts 2062 # number of float instructions
-system.cpu1.num_int_register_reads 54388368 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 10296894 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 54131389 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 10251114 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written
-system.cpu1.num_mem_refs 3801129 # number of memory refs
-system.cpu1.num_load_insts 2242444 # Number of load instructions
-system.cpu1.num_store_insts 1558685 # Number of store instructions
-system.cpu1.num_idle_cycles -28470862.464355 # Number of idle cycles
-system.cpu1.num_busy_cycles 602089088.464355 # Number of busy cycles
-system.cpu1.not_idle_fraction 1.049634 # Percentage of non-idle cycles
-system.cpu1.idle_fraction -0.049634 # Percentage of idle cycles
+system.cpu1.num_mem_refs 3780360 # number of memory refs
+system.cpu1.num_load_insts 2226594 # Number of load instructions
+system.cpu1.num_store_insts 1553766 # Number of store instructions
+system.cpu1.num_idle_cycles -28509606.904042 # Number of idle cycles
+system.cpu1.num_busy_cycles 602134345.904042 # Number of busy cycles
+system.cpu1.not_idle_fraction 1.049701 # Percentage of non-idle cycles
+system.cpu1.idle_fraction -0.049701 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 11072336 # DTB read hits
-system.cpu2.dtb.read_misses 27162 # DTB read misses
-system.cpu2.dtb.write_hits 3379244 # DTB write hits
-system.cpu2.dtb.write_misses 7485 # DTB write misses
+system.cpu2.dtb.read_hits 11094758 # DTB read hits
+system.cpu2.dtb.read_misses 26972 # DTB read misses
+system.cpu2.dtb.write_hits 3400244 # DTB write hits
+system.cpu2.dtb.write_misses 7099 # DTB write misses
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 3059 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 210 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 3080 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 792 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 201 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 417 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 11099498 # DTB read accesses
-system.cpu2.dtb.write_accesses 3386729 # DTB write accesses
+system.cpu2.dtb.perms_faults 424 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 11121730 # DTB read accesses
+system.cpu2.dtb.write_accesses 3407343 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 14451580 # DTB hits
-system.cpu2.dtb.misses 34647 # DTB misses
-system.cpu2.dtb.accesses 14486227 # DTB accesses
-system.cpu2.itb.inst_hits 3940913 # ITB inst hits
-system.cpu2.itb.inst_misses 4663 # ITB inst misses
+system.cpu2.dtb.hits 14495002 # DTB hits
+system.cpu2.dtb.misses 34071 # DTB misses
+system.cpu2.dtb.accesses 14529073 # DTB accesses
+system.cpu2.itb.inst_hits 3971406 # ITB inst hits
+system.cpu2.itb.inst_misses 4850 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 1673 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 1791 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1033 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 3945576 # ITB inst accesses
-system.cpu2.itb.hits 3940913 # DTB hits
-system.cpu2.itb.misses 4663 # DTB misses
-system.cpu2.itb.accesses 3945576 # DTB accesses
-system.cpu2.numCycles 88228970 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 3976256 # ITB inst accesses
+system.cpu2.itb.hits 3971406 # DTB hits
+system.cpu2.itb.misses 4850 # DTB misses
+system.cpu2.itb.accesses 3976256 # DTB accesses
+system.cpu2.numCycles 88220053 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 4678533 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 3809806 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 231267 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 3069092 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 2498136 # Number of BTB hits
+system.cpu2.BPredUnit.lookups 4714679 # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted 3830081 # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect 228509 # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups 3129435 # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits 2502665 # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 412114 # Number of times the RAS was used to get a target.
-system.cpu2.BPredUnit.RASInCorrect 22380 # Number of incorrect RAS predictions.
-system.cpu2.fetch.icacheStallCycles 9360105 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 31976282 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 4678533 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 2910250 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 6786917 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1728503 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 53808 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles 19342330 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 913 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 36859 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 59251 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 389 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3939412 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 244088 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2174 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 36830548 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.047719 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.434253 # Number of instructions fetched each cycle (Total)
+system.cpu2.BPredUnit.usedRAS 416919 # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.RASInCorrect 22256 # Number of incorrect RAS predictions.
+system.cpu2.fetch.icacheStallCycles 9444272 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 32171210 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 4714679 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 2919584 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 6810047 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1714054 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 54378 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 19370743 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 384 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 766 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 36586 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 56559 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 314 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3969766 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 243007 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 2358 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 36954315 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.048838 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.435241 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 30048718 81.59% 81.59% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 408687 1.11% 82.70% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 492187 1.34% 84.03% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 812698 2.21% 86.24% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 611463 1.66% 87.90% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 330922 0.90% 88.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1062958 2.89% 91.68% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 224607 0.61% 92.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 2838308 7.71% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 30149445 81.59% 81.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 388045 1.05% 82.64% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 515673 1.40% 84.03% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 809442 2.19% 86.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 613859 1.66% 87.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 342479 0.93% 88.81% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1057115 2.86% 91.67% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 225211 0.61% 92.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 2853046 7.72% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 36830548 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.053027 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.362424 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 9885763 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 19327017 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 6180149 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 300885 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1135792 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 597498 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 54848 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 36565818 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 186819 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 1135792 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 10385247 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 6621320 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 11277395 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 5962558 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1447335 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 34838937 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2719 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 250879 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 912957 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents 22201 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 37227895 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 159446068 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 159418988 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 27080 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 26794485 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 10433409 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 254044 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 230219 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3142941 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6628278 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3915406 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 518992 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 767543 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 32164019 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 534132 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 35030885 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 59969 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 6868407 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 17749072 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 150741 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 36830548 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.951137 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.612264 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 36954315 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.053442 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.364670 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 9982984 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 19336478 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 6240183 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 267118 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1126648 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 608561 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 54769 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 36760882 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 185685 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 1126648 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 10483708 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 6549966 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 11350548 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 5986699 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1455863 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 35043442 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2820 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 275900 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 915207 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents 16681 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 37480121 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 160397903 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 160370485 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 27418 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 27101892 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 10378228 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 234776 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 210973 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3167835 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6643625 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3930476 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 536055 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 848060 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 32398169 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 511180 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 35261741 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 57711 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 6815727 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 17611211 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 150093 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 36954315 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.954198 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.610437 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 24216483 65.75% 65.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3835065 10.41% 76.16% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 2287291 6.21% 82.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 1980355 5.38% 87.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 2800040 7.60% 95.35% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1007857 2.74% 98.09% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 517219 1.40% 99.49% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 152490 0.41% 99.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 33748 0.09% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 24234818 65.58% 65.58% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3845219 10.41% 75.99% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 2339985 6.33% 82.32% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 2011458 5.44% 87.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 2820235 7.63% 95.39% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1010729 2.74% 98.13% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 509292 1.38% 99.51% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 148791 0.40% 99.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 33788 0.09% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 36830548 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 36954315 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 17662 1.14% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 1415792 91.50% 92.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 113850 7.36% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 16803 1.09% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 1412351 91.83% 92.92% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 108917 7.08% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 60995 0.17% 0.17% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 19871242 56.72% 56.90% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 29695 0.08% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.98% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 11515486 32.87% 89.86% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3553080 10.14% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 60938 0.17% 0.17% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 20064817 56.90% 57.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 28831 0.08% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 373 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.16% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 11537749 32.72% 89.88% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3569015 10.12% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 35030885 # Type of FU issued
-system.cpu2.iq.rate 0.397045 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 1547304 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.044170 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 108527324 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 39572230 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 28399462 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 6790 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 3711 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 36513628 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 3566 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 191014 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 35261741 # Type of FU issued
+system.cpu2.iq.rate 0.399702 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 1538071 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.043619 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 109100819 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 39730950 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 28646602 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 6706 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 3736 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 3123 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 36735375 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 3499 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 200241 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1467031 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 2011 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 9738 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 545094 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1445664 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1895 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 9919 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 541092 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5365251 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 332989 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5363616 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 332725 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1135792 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 4899150 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 89921 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32779082 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 64376 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6628278 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3915406 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 386018 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 31359 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 9738 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 111294 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 92702 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 203996 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 34250844 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 11286425 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 780041 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 1126648 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 4836519 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 87210 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32990358 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 63317 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6643625 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3930476 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 365793 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 29718 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2499 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 9919 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 109460 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 91793 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 201253 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 34488012 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 11310897 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 773729 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 80931 # number of nop insts executed
-system.cpu2.iew.exec_refs 14805022 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 3673391 # Number of branches executed
-system.cpu2.iew.exec_stores 3518597 # Number of stores executed
-system.cpu2.iew.exec_rate 0.388204 # Inst execution rate
-system.cpu2.iew.wb_sent 33866957 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 28402589 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 16335424 # num instructions producing a value
-system.cpu2.iew.wb_consumers 29431571 # num instructions consuming a value
+system.cpu2.iew.exec_nop 81009 # number of nop insts executed
+system.cpu2.iew.exec_refs 14846360 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 3721674 # Number of branches executed
+system.cpu2.iew.exec_stores 3535463 # Number of stores executed
+system.cpu2.iew.exec_rate 0.390932 # Inst execution rate
+system.cpu2.iew.wb_sent 34107524 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 28649725 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 16504855 # num instructions producing a value
+system.cpu2.iew.wb_consumers 29777909 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.321919 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.555031 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.324753 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.554265 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 6831747 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 383391 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 177223 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 35694573 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.719725 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.780912 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 6780603 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 361087 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 174485 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 35827443 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.724416 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.779563 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 26969912 75.56% 75.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4228252 11.85% 87.40% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1198360 3.36% 90.76% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 616402 1.73% 92.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 527161 1.48% 93.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 311066 0.87% 94.84% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 434912 1.22% 96.05% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 325428 0.91% 96.97% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1083080 3.03% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 26972703 75.29% 75.29% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4272213 11.92% 87.21% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1247843 3.48% 90.69% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 631329 1.76% 92.45% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 544091 1.52% 93.97% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 320362 0.89% 94.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 435465 1.22% 96.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 326356 0.91% 96.99% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1077081 3.01% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 35694573 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 20797962 # Number of instructions committed
-system.cpu2.commit.committedOps 25690260 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 35827443 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 21038967 # Number of instructions committed
+system.cpu2.commit.committedOps 25953990 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8531559 # Number of memory references committed
-system.cpu2.commit.loads 5161247 # Number of loads committed
-system.cpu2.commit.membars 98356 # Number of memory barriers committed
-system.cpu2.commit.branches 3158165 # Number of branches committed
+system.cpu2.commit.refs 8587345 # Number of memory references committed
+system.cpu2.commit.loads 5197961 # Number of loads committed
+system.cpu2.commit.membars 96306 # Number of memory barriers committed
+system.cpu2.commit.branches 3207336 # Number of branches committed
system.cpu2.commit.fp_insts 3087 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 22900752 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 287889 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 1083080 # number cycles where commit BW limit reached
+system.cpu2.commit.int_insts 23136134 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 296648 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 1077081 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 66589270 # The number of ROB reads
-system.cpu2.rob.rob_writes 66235051 # The number of ROB writes
-system.cpu2.timesIdled 359715 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 51398422 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 3569788363 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 20743850 # Number of Instructions Simulated
-system.cpu2.committedOps 25636148 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 20743850 # Number of Instructions Simulated
-system.cpu2.cpi 4.253259 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 4.253259 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.235114 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.235114 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 159046643 # number of integer regfile reads
-system.cpu2.int_regfile_writes 30194860 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 22317 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 20822 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 9419199 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 278833 # number of misc regfile writes
+system.cpu2.rob.rob_reads 66956650 # The number of ROB reads
+system.cpu2.rob.rob_writes 66650908 # The number of ROB writes
+system.cpu2.timesIdled 359376 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 51265738 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 3569532047 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 20984673 # Number of Instructions Simulated
+system.cpu2.committedOps 25899696 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 20984673 # Number of Instructions Simulated
+system.cpu2.cpi 4.204023 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 4.204023 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.237867 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.237867 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 160070437 # number of integer regfile reads
+system.cpu2.int_regfile_writes 30477342 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 22294 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 20824 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 9434068 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 244358 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925539770424 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 925539770424 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925539770424 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 925539770424 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925532055074 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 925532055074 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925532055074 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 925532055074 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.540587 # Number of seconds simulated
-sim_ticks 2540587123500 # Number of ticks simulated
-final_tick 2540587123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.540276 # Number of seconds simulated
+sim_ticks 2540275734000 # Number of ticks simulated
+final_tick 2540275734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28859 # Simulator instruction rate (inst/s)
-host_op_rate 37121 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1209803028 # Simulator tick rate (ticks/s)
-host_mem_usage 406188 # Number of bytes of host memory used
-host_seconds 2100.00 # Real time elapsed on the host
-sim_insts 60603607 # Number of instructions simulated
-sim_ops 77954043 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 63914 # Simulator instruction rate (inst/s)
+host_op_rate 82240 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2691970222 # Simulator tick rate (ticks/s)
+host_mem_usage 413060 # Number of bytes of host memory used
+host_seconds 943.65 # Real time elapsed on the host
+sim_insts 60312498 # Number of instructions simulated
+sim_ops 77605759 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 521152 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4740560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 279808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4349656 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131004456 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 521152 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 279808 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 800960 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1619508 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1396592 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6799204 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 405568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 3860688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 1472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 395008 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5229152 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131004144 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 405568 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 395008 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783168 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1412956 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1603284 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799408 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 8143 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 74105 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4372 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 67969 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293448 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 404877 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 349148 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47670291 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 806 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst 6337 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 60357 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 23 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6172 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 81713 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15293445 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59112 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 353239 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 400821 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 813172 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47676135 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 605 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 205131 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1865931 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 110135 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1712067 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51564638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 205131 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 110135 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 315266 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1489067 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 637454 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 549712 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2676233 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1489067 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47670291 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 806 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 159655 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1519791 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 579 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 155498 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2058498 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51570836 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 159655 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 155498 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315153 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1489275 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 556222 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 631146 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2676642 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1489275 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47676135 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 205131 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2503385 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 110135 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2261780 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54240872 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15293448 # Total number of read requests seen
-system.physmem.writeReqs 813136 # Total number of write requests seen
-system.physmem.cpureqs 218391 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 978780672 # Total number of bytes read from memory
-system.physmem.bytesWritten 52040704 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 131004456 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6799204 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 955907 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 956222 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 955717 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 955757 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 955661 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 955544 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 955404 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 955585 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 956056 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 955920 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 955992 # Track reads on a per bank basis
+system.physmem.bw_total::cpu0.inst 159655 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2076012 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 579 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 155498 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2689643 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54247478 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15293445 # Total number of read requests seen
+system.physmem.writeReqs 813172 # Total number of write requests seen
+system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 978780480 # Total number of bytes read from memory
+system.physmem.bytesWritten 52043008 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 131004144 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799408 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 955910 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 956214 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 955714 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 955761 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 955656 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 955538 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 955410 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 955590 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 956063 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 955922 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 955987 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 955944 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 956032 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 955927 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 956056 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 955714 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50106 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50364 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 49972 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50827 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50676 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50834 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51120 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51083 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51170 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51298 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::12 956042 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 955918 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 956046 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 955719 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50108 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50359 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50035 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50823 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50679 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50829 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51147 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51119 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51116 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51361 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51167 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51295 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51031 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 677160 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2540585876000 # Total gap between requests
+system.physmem.numWrRetry 693675 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2540274436500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 42 # Categorize read packet sizes
+system.physmem.readPktSize::2 44 # Categorize read packet sizes
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154590 # Categorize read packet sizes
+system.physmem.readPktSize::6 154585 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1431185 # categorize write packet sizes
+system.physmem.writePktSize::2 1447735 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59111 # categorize write packet sizes
+system.physmem.writePktSize::6 59112 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1056941 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 992282 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 949580 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 983982 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2774748 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2777750 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5475537 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 36612 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 30094 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 29956 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 29864 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 57737 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 31653 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 59391 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 5382 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1868 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1057043 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 992576 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 949780 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 984222 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2774561 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2777593 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5475568 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 36103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 30071 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 29941 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 29875 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 57717 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 31668 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 59387 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 5361 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1880 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 24 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3640 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3716 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3825 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4020 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4294 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4489 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4657 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4830 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5057 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35378 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35366 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35318 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35309 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3638 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3819 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4264 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4466 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4603 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4761 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35360 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35343 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35332 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35325 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35283 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35222 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 31866 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 31776 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 31654 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 31445 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 31156 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 30947 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 30761 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 30573 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 30334 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35257 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35249 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35241 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35220 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 31872 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 31784 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 31663 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 31466 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 31190 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 30972 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 30814 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 30644 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 30396 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 295225090687 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 372543516687 # Sum of mem lat for all requests
-system.physmem.totBusLat 61173752000 # Total cycles spent in databus access
-system.physmem.totBankLat 16144674000 # Total cycles spent in bank access
-system.physmem.avgQLat 19304.04 # Average queueing delay per request
-system.physmem.avgBankLat 1055.66 # Average bank access latency per request
+system.physmem.totQLat 295222941913 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 372544627913 # Sum of mem lat for all requests
+system.physmem.totBusLat 61173736000 # Total cycles spent in databus access
+system.physmem.totBankLat 16147950000 # Total cycles spent in bank access
+system.physmem.avgQLat 19303.90 # Average queueing delay per request
+system.physmem.avgBankLat 1055.87 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24359.70 # Average memory access latency
-system.physmem.avgRdBW 385.26 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.56 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 24359.78 # Average memory access latency
+system.physmem.avgRdBW 385.30 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.49 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.57 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.54 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 1.12 # Average write queue length over time
-system.physmem.readRowHits 15250784 # Number of row buffer hits during reads
-system.physmem.writeRowHits 786076 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 1.11 # Average write queue length over time
+system.physmem.readRowHits 15250779 # Number of row buffer hits during reads
+system.physmem.writeRowHits 786181 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.72 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.67 # Row buffer hit rate for writes
-system.physmem.avgGap 157735.86 # Average gap between requests
-system.l2c.replacements 64360 # number of replacements
-system.l2c.tagsinuse 51403.610979 # Cycle average of tags in use
-system.l2c.total_refs 1940230 # Total number of references to valid blocks.
-system.l2c.sampled_refs 129752 # Sample count of references to valid blocks.
-system.l2c.avg_refs 14.953373 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2504468947000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36917.340991 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 20.674010 # Average occupied blocks per requestor
+system.physmem.writeRowHitRate 96.68 # Row buffer hit rate for writes
+system.physmem.avgGap 157716.20 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 64355 # number of replacements
+system.l2c.tagsinuse 51419.267755 # Cycle average of tags in use
+system.l2c.total_refs 1938049 # Total number of references to valid blocks.
+system.l2c.sampled_refs 129745 # Sample count of references to valid blocks.
+system.l2c.avg_refs 14.937369 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 2504164034000 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 36931.020579 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 16.606352 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000348 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5181.760660 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 3292.636698 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 8.768373 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 3037.851423 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 2944.578476 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.563314 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000315 # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu0.inst 4513.419817 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 3324.401102 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 19.072216 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.itb.walker 0.003905 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 3703.882826 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 2910.860610 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.563523 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker 0.000253 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.079067 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.050242 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.046354 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.044931 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.784357 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 52210 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 7522 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 501648 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 201746 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 46118 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 6836 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 471830 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 185683 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1473593 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 608099 # number of Writeback hits
-system.l2c.Writeback_hits::total 608099 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 20 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits
+system.l2c.occ_percent::cpu0.inst 0.068869 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.050726 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker 0.000291 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.056517 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.044416 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.784596 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 45285 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 6882 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 457711 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 190308 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 52226 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 7603 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 514110 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 196973 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1471098 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 608285 # number of Writeback hits
+system.l2c.Writeback_hits::total 608285 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 19 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 36 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 57007 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 55991 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 112998 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 52210 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 7522 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 501648 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 258753 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 46118 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 6836 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 471830 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 241674 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1586591 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 52210 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 7522 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 501648 # number of overall hits
-system.l2c.overall_hits::cpu0.data 258753 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 46118 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 6836 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 471830 # number of overall hits
-system.l2c.overall_hits::cpu1.data 241674 # number of overall hits
-system.l2c.overall_hits::total 1586591 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 32 # number of ReadReq misses
+system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 56083 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 56920 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 113003 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 45285 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 6882 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 457711 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 246391 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 52226 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 7603 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 514110 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 253893 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1584101 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 45285 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 6882 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 457711 # number of overall hits
+system.l2c.overall_hits::cpu0.data 246391 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 52226 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 7603 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 514110 # number of overall hits
+system.l2c.overall_hits::cpu1.data 253893 # number of overall hits
+system.l2c.overall_hits::total 1584101 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 24 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 8033 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6226 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 4376 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 4487 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 23165 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 1562 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 1342 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses
+system.l2c.ReadReq_misses::cpu0.inst 6225 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6013 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 23 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 6180 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 4688 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 23156 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 1337 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 1563 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2900 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 68853 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 64314 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 133167 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 32 # number of demand (read+write) misses
+system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 55166 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 78004 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 133170 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 24 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 8033 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 75079 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 4376 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 68801 # number of demand (read+write) misses
-system.l2c.demand_misses::total 156332 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 32 # number of overall misses
+system.l2c.demand_misses::cpu0.inst 6225 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 61179 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 23 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 6180 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 82692 # number of demand (read+write) misses
+system.l2c.demand_misses::total 156326 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 24 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 8033 # number of overall misses
-system.l2c.overall_misses::cpu0.data 75079 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 4376 # number of overall misses
-system.l2c.overall_misses::cpu1.data 68801 # number of overall misses
-system.l2c.overall_misses::total 156332 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2269000 # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu0.inst 6225 # number of overall misses
+system.l2c.overall_misses::cpu0.data 61179 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 23 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 6180 # number of overall misses
+system.l2c.overall_misses::cpu1.data 82692 # number of overall misses
+system.l2c.overall_misses::total 156326 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1794000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 420354500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 331291999 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 618500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 233702500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 250819000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1239173499 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 181000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 252500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 433500 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 3783281998 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 2967459500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 6750741498 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 2269000 # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 325918500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 325021000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1538000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 327300000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 258970498 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1240728498 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 181500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 204500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 386000 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 2786064998 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 3948204500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 6734269498 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 1794000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 420354500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 4114573997 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 618500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 233702500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 3218278500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 7989914997 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 2269000 # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 325918500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 3111085998 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 1538000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 327300000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 4207174998 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 7974997996 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 1794000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 420354500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 4114573997 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 618500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 233702500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 3218278500 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 7989914997 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 52242 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 7524 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 509681 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 207972 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 46127 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 6836 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 476206 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 190170 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1496758 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 608099 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 608099 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 1582 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 1362 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu0.inst 325918500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 3111085998 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 1538000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 327300000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 4207174998 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 7974997996 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 45309 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 6884 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 463936 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 196321 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 52249 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 7604 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 520290 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 201661 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1494254 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 608285 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 608285 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 1354 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 1582 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 7 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 125860 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 120305 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246165 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 52242 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 7524 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 509681 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 333832 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 46127 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 6836 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 476206 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 310475 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1742923 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 52242 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 7524 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 509681 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 333832 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 46127 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 6836 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 476206 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 310475 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1742923 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000266 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015761 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.029937 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000195 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.009189 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.023595 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.015477 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987358 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.985316 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.986413 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_accesses::cpu0.data 111249 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 134924 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 246173 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 45309 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 6884 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 463936 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 307570 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 52249 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 7604 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 520290 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 336585 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1740427 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 45309 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 6884 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 463936 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 307570 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 52249 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 7604 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 520290 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 336585 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1740427 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000530 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000291 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.013418 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.030628 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000440 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000132 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.011878 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.023247 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.015497 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987445 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.987990 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.987738 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.142857 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.076923 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.547060 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.534591 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.540966 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000266 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015761 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.224901 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000195 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.009189 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.221599 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.089695 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000266 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015761 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.224901 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000195 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.009189 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.221599 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.089695 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70906.250000 # average ReadReq miss latency
+system.l2c.SCUpgradeReq_miss_rate::total 0.153846 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.495879 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.578133 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.540961 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000530 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000291 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.013418 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.198911 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000440 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.000132 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.011878 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.245679 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.089820 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000530 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000291 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.013418 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.198911 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000440 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.000132 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.011878 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.245679 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.089820 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52328.457612 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 53211.050273 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68722.222222 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53405.507313 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 55899.041676 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 53493.351997 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 115.877081 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 188.152012 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 149.276860 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54947.235386 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46140.179432 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 50693.801753 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 70906.250000 # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52356.385542 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 54053.051721 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 66869.565217 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52961.165049 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 55241.147184 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 53581.296338 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 135.751683 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 130.838132 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 133.103448 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 50503.299097 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 50615.410748 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 50568.968221 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52328.457612 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 54803.260526 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68722.222222 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 53405.507313 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 46776.623886 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 51108.634170 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 70906.250000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52356.385542 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 50852.187810 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 66869.565217 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52961.165049 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 50877.654404 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 51015.173394 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52328.457612 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 54803.260526 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68722.222222 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 53405.507313 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 46776.623886 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 51108.634170 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52356.385542 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 50852.187810 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 66869.565217 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52961.165049 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 50877.654404 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 51015.173394 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 59111 # number of writebacks
-system.l2c.writebacks::total 59111 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 32 # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks 59112 # number of writebacks
+system.l2c.writebacks::total 59112 # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 24 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 8025 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 6187 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 4372 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 4463 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 23090 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 1562 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 1342 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 2904 # number of UpgradeReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 6219 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 5976 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 23 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 6172 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 4665 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 23082 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 1337 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 1563 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 2900 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 68853 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 64314 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 133167 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 32 # number of demand (read+write) MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 55166 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 78004 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 133170 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 24 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 8025 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 75040 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 4372 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 68777 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 156257 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 32 # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 6219 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 61142 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 23 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 6172 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 82669 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 156252 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 24 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 8025 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 75040 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 4372 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 68777 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 156257 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1865559 # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu0.inst 6219 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 61142 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 23 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 6172 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 82669 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 156252 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1489045 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93002 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 318411185 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 250751004 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 504018 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 178311078 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 193087266 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 943023112 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15680528 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13422342 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 29102870 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 247133124 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 247332621 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1246542 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56002 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 248969104 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 198696108 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 945015548 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13371337 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15702513 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 29073850 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 10001 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2929616476 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2170341063 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5099957539 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1865559 # number of demand (read+write) MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2100759191 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2982654930 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5083414121 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1489045 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 318411185 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 3180367480 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 504018 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 178311078 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 2363428329 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 6042980651 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1865559 # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 247133124 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 2348091812 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1246542 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56002 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 248969104 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 3181351038 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 6028429669 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1489045 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 318411185 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 3180367480 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 504018 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 178311078 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 2363428329 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 6042980651 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 247133124 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 2348091812 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1246542 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56002 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 248969104 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 3181351038 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 6028429669 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4312653 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83955529530 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83016717004 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 166976559187 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8488186790 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 5709859144 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 14198045934 # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83367317530 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83605453007 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166977083190 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 6167057731 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8185447208 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 14352504939 # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76004 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76004 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4312653 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92443716320 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 88726576148 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 181174605121 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000266 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015745 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.029749 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000195 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009181 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023468 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.015427 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987358 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.985316 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.986413 # mshr miss rate for UpgradeReq accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 89534375261 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91790900215 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 181329588129 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.030440 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023133 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.015447 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987445 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987990 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.987738 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.142857 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.076923 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.547060 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534591 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.540966 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000266 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015745 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.224784 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000195 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009181 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.221522 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.089652 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000266 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015745 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.224784 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000195 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009181 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.221522 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.089652 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750 # average ReadReq mshr miss latency
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.495879 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578133 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.540961 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.198791 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.245611 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.089778 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.198791 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.245611 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.089778 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39677.406231 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40528.689834 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40784.784538 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43264.007618 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40841.191511 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.750320 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.745156 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.649449 # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41387.654116 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42592.949196 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40941.666580 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10046.393474 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.465517 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42548.857363 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.012734 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 38297.457621 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 38080.687217 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 38237.204887 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 38172.367057 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39677.406231 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42382.295842 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40784.784538 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34363.643791 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 38673.343601 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39677.406231 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42382.295842 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40784.784538 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34363.643791 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 38673.343601 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 26104138 # DTB read hits
-system.cpu0.dtb.read_misses 45655 # DTB read misses
-system.cpu0.dtb.write_hits 6173225 # DTB write hits
-system.cpu0.dtb.write_misses 11582 # DTB write misses
-system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 25321176 # DTB read hits
+system.cpu0.dtb.read_misses 39544 # DTB read misses
+system.cpu0.dtb.write_hits 5538222 # DTB write hits
+system.cpu0.dtb.write_misses 9025 # DTB write misses
+system.cpu0.dtb.flush_tlb 256 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 737 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 8687 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1569 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 7899 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1433 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 666 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 26149793 # DTB read accesses
-system.cpu0.dtb.write_accesses 6184807 # DTB write accesses
+system.cpu0.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 25360720 # DTB read accesses
+system.cpu0.dtb.write_accesses 5547247 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 32277363 # DTB hits
-system.cpu0.dtb.misses 57237 # DTB misses
-system.cpu0.dtb.accesses 32334600 # DTB accesses
-system.cpu0.itb.inst_hits 6054056 # ITB inst hits
-system.cpu0.itb.inst_misses 7505 # ITB inst misses
+system.cpu0.dtb.hits 30859398 # DTB hits
+system.cpu0.dtb.misses 48569 # DTB misses
+system.cpu0.dtb.accesses 30907967 # DTB accesses
+system.cpu0.itb.inst_hits 5399990 # ITB inst hits
+system.cpu0.itb.inst_misses 6797 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 256 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 737 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2789 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2645 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1640 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1504 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 6061561 # ITB inst accesses
-system.cpu0.itb.hits 6054056 # DTB hits
-system.cpu0.itb.misses 7505 # DTB misses
-system.cpu0.itb.accesses 6061561 # DTB accesses
-system.cpu0.numCycles 240389950 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 5406787 # ITB inst accesses
+system.cpu0.itb.hits 5399990 # DTB hits
+system.cpu0.itb.misses 6797 # DTB misses
+system.cpu0.itb.accesses 5406787 # DTB accesses
+system.cpu0.numCycles 232916834 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 7650447 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 6071769 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 390619 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 4963412 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 4056247 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 6894641 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 5490275 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 340467 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 4496048 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 3641169 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 744385 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 39840 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 15652124 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 47554546 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7650447 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4800632 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10611377 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2494725 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 89565 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 50696365 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 1823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 1967 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 55574 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 106827 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6051824 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 344537 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3471 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 78943853 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.750152 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.105781 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 672237 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 35025 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 14144008 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 42774388 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6894641 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4313406 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 9542116 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2097502 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 81571 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 47928082 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 983 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 1918 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 48764 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 90424 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 5397887 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 280481 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3116 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 73293713 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.724548 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.073228 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 68340077 86.57% 86.57% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 702129 0.89% 87.46% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 881040 1.12% 88.57% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1224383 1.55% 90.12% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1120463 1.42% 91.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 584523 0.74% 92.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1319074 1.67% 93.95% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 413717 0.52% 94.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4358447 5.52% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 63759289 86.99% 86.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 642563 0.88% 87.87% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 816896 1.11% 88.98% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1076628 1.47% 90.45% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1030388 1.41% 91.86% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 525946 0.72% 92.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1160801 1.58% 94.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 367124 0.50% 94.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3914078 5.34% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 78943853 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.031825 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.197823 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 16656979 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 50446432 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9625401 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 575149 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1637749 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1050019 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 92865 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 56438894 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 312308 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1637749 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 17559275 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 19379590 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 27710296 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9215944 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3438937 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 54038405 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 14132 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 614041 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 2240889 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 19821 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 55994087 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 246350981 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 246302367 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 48614 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 41407239 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 14586848 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 463494 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 411765 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 6993142 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 10396030 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 7010506 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1100529 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1298753 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 50240617 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1080191 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 63997387 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 98424 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10068381 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 24718063 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 263130 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 78943853 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.810670 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.516651 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 73293713 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.029601 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.183647 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 15070134 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 47635747 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 8687716 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 522868 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1375117 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 927671 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 82962 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 50805033 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 279607 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1375117 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 15858431 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 18747322 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 25731690 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 8353206 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3225899 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 48905504 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 13838 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 630791 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 2093496 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 12811 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 50688794 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 222549147 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 222507399 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 41748 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 38461100 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 12227693 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 386484 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 344770 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 6389877 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 9452191 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6279292 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 988040 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1320602 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 45692134 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 977389 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 60037368 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 85152 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 8499333 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 20279389 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 254746 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 73293713 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.819134 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.521823 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 55721215 70.58% 70.58% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 7438559 9.42% 80.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3764189 4.77% 84.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3138828 3.98% 88.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6266578 7.94% 96.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1507037 1.91% 98.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 806867 1.02% 99.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 233373 0.30% 99.91% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 67207 0.09% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 51609317 70.41% 70.41% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 6835660 9.33% 79.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3457344 4.72% 84.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2997093 4.09% 88.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6031042 8.23% 96.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1346418 1.84% 98.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 738853 1.01% 99.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 217523 0.30% 99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 60463 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 78943853 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 73293713 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 28850 0.65% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 4 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4202057 94.56% 95.21% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 212765 4.79% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 26194 0.60% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 3 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4172771 94.90% 95.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 196420 0.31% 0.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 30502224 47.66% 47.97% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 49600 0.08% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 1274 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 26758229 41.81% 89.86% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6489612 10.14% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 194561 0.32% 0.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 28037950 46.70% 47.02% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 44753 0.07% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 838 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 25907736 43.15% 90.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5851514 9.75% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 63997387 # Type of FU issued
-system.cpu0.iq.rate 0.266223 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 4443676 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.069435 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 211525282 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 61397992 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 45248586 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12498 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6745 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5570 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 68238014 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6629 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 331719 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 60037368 # Type of FU issued
+system.cpu0.iq.rate 0.257763 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 4397050 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.073239 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 197888427 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 55177485 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 41654501 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 10625 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 5737 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 4733 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 64234192 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 5665 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 298497 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2183838 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 4014 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 16143 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 861796 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1811405 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3010 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 725021 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17073193 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 345280 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 17048224 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 266574 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1637749 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 14492701 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 245337 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 51437500 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 107423 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 10396030 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 7010506 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 766368 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 62240 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3660 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 16143 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 190401 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 151763 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 342164 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 62995358 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 26449087 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1002029 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1375117 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 14032156 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 223286 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 46775692 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 94480 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 9452191 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6279292 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 703336 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 50186 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 4000 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 14875 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 165277 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 131199 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 296476 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 59245437 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 25661722 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 791931 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 116692 # number of nop insts executed
-system.cpu0.iew.exec_refs 32879818 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 6078109 # Number of branches executed
-system.cpu0.iew.exec_stores 6430731 # Number of stores executed
-system.cpu0.iew.exec_rate 0.262055 # Inst execution rate
-system.cpu0.iew.wb_sent 62497341 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 45254156 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 24800882 # num instructions producing a value
-system.cpu0.iew.wb_consumers 45441474 # num instructions consuming a value
+system.cpu0.iew.exec_nop 106169 # number of nop insts executed
+system.cpu0.iew.exec_refs 31462090 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 5561458 # Number of branches executed
+system.cpu0.iew.exec_stores 5800368 # Number of stores executed
+system.cpu0.iew.exec_rate 0.254363 # Inst execution rate
+system.cpu0.iew.wb_sent 58848296 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 41659234 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 23213315 # num instructions producing a value
+system.cpu0.iew.wb_consumers 42468919 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.188253 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.545776 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.178859 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.546595 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 9944794 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 817061 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 299135 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 77306104 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.530438 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.512152 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 8329034 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 722643 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 258629 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 71918596 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.527800 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.514238 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 62653127 81.05% 81.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7139643 9.24% 90.28% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2117433 2.74% 93.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1152491 1.49% 94.51% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1052620 1.36% 95.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 581358 0.75% 96.62% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 718590 0.93% 97.55% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 381418 0.49% 98.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1509424 1.95% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 58433692 81.25% 81.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 6549576 9.11% 90.36% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1938281 2.70% 93.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1064527 1.48% 94.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 992329 1.38% 95.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 495986 0.69% 96.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 654165 0.91% 97.51% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 355670 0.49% 98.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1434370 1.99% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 77306104 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 32015395 # Number of instructions committed
-system.cpu0.commit.committedOps 41006110 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 71918596 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 29885048 # Number of instructions committed
+system.cpu0.commit.committedOps 37958605 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 14360902 # Number of memory references committed
-system.cpu0.commit.loads 8212192 # Number of loads committed
-system.cpu0.commit.membars 221881 # Number of memory barriers committed
-system.cpu0.commit.branches 5266033 # Number of branches committed
-system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 36294613 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 520344 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1509424 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 13195057 # Number of memory references committed
+system.cpu0.commit.loads 7640786 # Number of loads committed
+system.cpu0.commit.membars 194107 # Number of memory barriers committed
+system.cpu0.commit.branches 4848128 # Number of branches committed
+system.cpu0.commit.fp_insts 4699 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 33604858 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 476381 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1434370 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 125738503 # The number of ROB reads
-system.cpu0.rob.rob_writes 103590706 # The number of ROB writes
-system.cpu0.timesIdled 892654 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 161446097 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2255175331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 31936467 # Number of Instructions Simulated
-system.cpu0.committedOps 40927182 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 31936467 # Number of Instructions Simulated
-system.cpu0.cpi 7.527130 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 7.527130 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.132853 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.132853 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 285784738 # number of integer regfile reads
-system.cpu0.int_regfile_writes 46365180 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 22828 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 19904 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 16064067 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 471303 # number of misc regfile writes
-system.cpu0.icache.replacements 986601 # number of replacements
-system.cpu0.icache.tagsinuse 511.585602 # Cycle average of tags in use
-system.cpu0.icache.total_refs 10225858 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 987113 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 10.359359 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 6782112000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 321.917069 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 189.668533 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.628744 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu1.inst 0.370446 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.999191 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 5498991 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 4726867 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 10225858 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 5498991 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 4726867 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 10225858 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 5498991 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 4726867 # number of overall hits
-system.cpu0.icache.overall_hits::total 10225858 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 552708 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 515964 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1068672 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 552708 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 515964 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1068672 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 552708 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 515964 # number of overall misses
-system.cpu0.icache.overall_misses::total 1068672 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7467633494 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6811010992 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 14278644486 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 7467633494 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 6811010992 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 14278644486 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 7467633494 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 6811010992 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 14278644486 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 6051699 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 5242831 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 11294530 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 6051699 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 5242831 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 11294530 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 6051699 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 5242831 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 11294530 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.091331 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.098413 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.094619 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.091331 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.098413 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.094619 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.091331 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.098413 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.094619 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13510.992231 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13200.554674 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13361.110318 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13510.992231 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13200.554674 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13361.110318 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13510.992231 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13200.554674 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13361.110318 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 4485 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 398 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 340 # number of cycles access was blocked
+system.cpu0.rob.rob_reads 115883530 # The number of ROB reads
+system.cpu0.rob.rob_writes 93994803 # The number of ROB writes
+system.cpu0.timesIdled 855495 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 159623121 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2324012553 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 29813564 # Number of Instructions Simulated
+system.cpu0.committedOps 37887121 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 29813564 # Number of Instructions Simulated
+system.cpu0.cpi 7.812445 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 7.812445 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.128001 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.128001 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 268137987 # number of integer regfile reads
+system.cpu0.int_regfile_writes 42752144 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 22081 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 19566 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 14602892 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 394034 # number of misc regfile writes
+system.cpu0.icache.replacements 984960 # number of replacements
+system.cpu0.icache.tagsinuse 511.605628 # Cycle average of tags in use
+system.cpu0.icache.total_refs 10192469 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 985472 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 10.342728 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 6475146000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 192.391014 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst 319.214614 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.375764 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst 0.623466 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.999230 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 4895846 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 5296623 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 10192469 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 4895846 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 5296623 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 10192469 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 4895846 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 5296623 # number of overall hits
+system.cpu0.icache.overall_hits::total 10192469 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 501920 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 563999 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 1065919 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 501920 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 563999 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 1065919 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 501920 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 563999 # number of overall misses
+system.cpu0.icache.overall_misses::total 1065919 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6726188495 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7525770495 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 14251958990 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 6726188495 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 7525770495 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 14251958990 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 6726188495 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 7525770495 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 14251958990 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 5397766 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 5860622 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 11258388 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 5397766 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 5860622 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 11258388 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 5397766 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 5860622 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 11258388 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092987 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.096235 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.094678 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092987 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.096235 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.094678 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092987 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.096235 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.094678 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13400.917467 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13343.588366 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13370.583496 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13400.917467 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13343.588366 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13370.583496 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13400.917467 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13343.588366 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13370.583496 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 5202 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 775 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 345 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.191176 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 398 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.078261 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets 775 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42344 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39180 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 81524 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 42344 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst 39180 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 81524 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 42344 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst 39180 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 81524 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 510364 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 476784 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 987148 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 510364 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 476784 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 987148 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 510364 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 476784 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 987148 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6084165494 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5553411993 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 11637577487 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6084165494 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5553411993 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 11637577487 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6084165494 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5553411993 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 11637577487 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37396 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 43020 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 80416 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 37396 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst 43020 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 80416 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 37396 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst 43020 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 80416 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 464524 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 520979 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 985503 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 464524 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 520979 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 985503 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 464524 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 520979 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 985503 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5488905495 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 6129367496 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 11618272991 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5488905495 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 6129367496 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 11618272991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5488905495 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 6129367496 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 11618272991 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6767000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6767000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6767000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 6767000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084334 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.090940 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087401 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084334 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.090940 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.087401 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084334 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.090940 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.087401 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.227779 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11647.647557 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11789.090883 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.227779 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11647.647557 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11789.090883 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.227779 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11647.647557 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.090883 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087535 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.087535 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.087535 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11789.180744 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11789.180744 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.180744 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 643795 # number of replacements
-system.cpu0.dcache.tagsinuse 511.994133 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 21730635 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 644307 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 33.727144 # Average number of references to valid blocks.
+system.cpu0.dcache.replacements 643643 # number of replacements
+system.cpu0.dcache.tagsinuse 511.994132 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 21553843 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 644155 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 33.460647 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 36157000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 255.754263 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu1.data 256.239870 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.499520 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu1.data 0.500468 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::cpu0.data 257.044618 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data 254.949514 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.502040 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data 0.497948 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 7320998 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 6545083 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 13866081 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3839440 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 3452761 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 7292201 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 142548 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 140954 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 283502 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 144156 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 141612 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 285768 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 11160438 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 9997844 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 21158282 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 11160438 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 9997844 # number of overall hits
-system.cpu0.dcache.overall_hits::total 21158282 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 376773 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 369451 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 746224 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1505844 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 1453809 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2959653 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7530 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6140 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 13670 # number of LoadLockedReq misses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6668355 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 7127763 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 13796118 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3513738 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 3750110 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 7263848 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119013 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 124173 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 243186 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120748 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 126887 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 247635 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 10182093 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 10877873 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 21059966 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 10182093 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 10877873 # number of overall hits
+system.cpu0.dcache.overall_hits::total 21059966 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 398872 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 347013 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 745885 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1308679 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 1650694 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 2959373 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5990 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 7586 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 7 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1882617 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 1823260 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 3705877 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1882617 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 1823260 # number of overall misses
-system.cpu0.dcache.overall_misses::total 3705877 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5747755000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5402696500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 11150451500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 63541262289 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 51082353349 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 114623615638 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104538500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 81673500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 186212000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 78000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data 1707551 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 1997707 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 3705258 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 1707551 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 1997707 # number of overall misses
+system.cpu0.dcache.overall_misses::total 3705258 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5845680000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5302488500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 11148168500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46981626335 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 67357897820 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 114339524155 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81001000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 104468000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 185469000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 103000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 181000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 69289017289 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 56485049849 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 125774067138 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 69289017289 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 56485049849 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 125774067138 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 7697771 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 6914534 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 14612305 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 5345284 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 4906570 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 10251854 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 150078 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 147094 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 297172 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144162 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 141619 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 285781 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 13043055 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 11821104 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 24864159 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 13043055 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 11821104 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 24864159 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048946 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.053431 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.051068 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.281714 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.296298 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.288694 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.050174 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.041742 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046000 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000042 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000049 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.144339 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.154238 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.149045 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.144339 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.154238 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.149045 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15255.219987 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14623.580664 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14942.499169 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42196.444179 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35136.908183 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38728.734631 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13882.934927 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13301.872964 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13621.945867 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_miss_latency::total 193000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 52827306335 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 72660386320 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 125487692655 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 52827306335 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 72660386320 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 125487692655 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 7067227 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 7474776 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 14542003 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4822417 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 5400804 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 10223221 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125003 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131759 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 256762 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 120754 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 126894 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 247648 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 11889644 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 12875580 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 24765224 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 11889644 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 12875580 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 24765224 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056440 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.046425 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.051292 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.271374 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.305639 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.289476 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047919 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.057575 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052874 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000050 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000055 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143617 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.155155 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.149615 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143617 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.155155 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.149615 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14655.528591 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15280.374222 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14946.229647 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35900.038386 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40805.805207 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38636.401750 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13522.704508 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13771.157395 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13661.535062 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14714.285714 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13923.076923 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36804.627436 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30980.249580 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33939.083013 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36804.627436 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30980.249580 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33939.083013 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 35448 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 12573 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 3421 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 258 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.361882 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 48.732558 # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14846.153846 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30937.469121 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36371.893536 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33867.464197 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30937.469121 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36371.893536 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33867.464197 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 37449 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 14136 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 3410 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 266 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.982111 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 53.142857 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 608099 # number of writebacks
-system.cpu0.dcache.writebacks::total 608099 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 175511 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 184666 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 360177 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1378456 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1332180 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 2710636 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 766 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 717 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1483 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1553967 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data 1516846 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 3070813 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1553967 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data 1516846 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 3070813 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 201262 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184785 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 386047 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127388 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121629 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 249017 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6764 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5423 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks 608285 # number of writebacks
+system.cpu0.dcache.writebacks::total 608285 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 207823 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 152147 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 359970 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1196124 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1514247 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 2710371 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 670 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 732 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1402 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1403947 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 1666394 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 3070341 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1403947 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 1666394 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 3070341 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191049 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 194866 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 385915 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 112555 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 136447 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 249002 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5320 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6854 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12174 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 7 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 328650 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 306414 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 328650 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 306414 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2736355500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2446708500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5183064000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4640301429 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3791272989 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8431574418 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82236000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62703500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 144939500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 303604 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 331313 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 634917 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 303604 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 331313 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 634917 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2589299000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2593519000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5182818000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3585837983 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4828490940 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8414328923 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 62428500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81807000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 144235500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 89000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 155000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7376656929 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6237981489 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 13614638418 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7376656929 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6237981489 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 13614638418 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91682874000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90682822000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182365696000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13814824895 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 10281264593 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 24096089488 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6175136983 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7422009940 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 13597146923 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6175136983 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7422009940 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 13597146923 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91055617500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91310638500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182366256000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 10805151656 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13444453545 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 24249605201 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105497698895 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100964086593 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206461785488 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.026145 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026724 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026419 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023832 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024789 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024290 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045070 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.036868 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.041010 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000042 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000049 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025197 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025921 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.025541 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025197 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025921 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.025541 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13595.986823 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13240.839354 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13425.992172 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36426.519209 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31170.797992 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33859.432962 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12157.894737 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11562.511525 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11892.959711 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101860769156 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104755092045 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206615861201 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027033 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026070 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026538 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023340 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025264 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042559 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052019 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047414 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000055 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.025637 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.025637 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13553.062303 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13309.243275 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13429.947009 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31858.540118 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35387.300124 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33792.214211 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11734.680451 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11935.658010 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.831444 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923.076923 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22445.327640 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20358.017222 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21438.214759 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22445.327640 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20358.017222 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21438.214759 # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12846.153846 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22401.807173 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21415.629008 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22401.807173 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21415.629008 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25160982 # DTB read hits
-system.cpu1.dtb.read_misses 40128 # DTB read misses
-system.cpu1.dtb.write_hits 5622181 # DTB write hits
-system.cpu1.dtb.write_misses 9250 # DTB write misses
+system.cpu1.dtb.read_hits 25842433 # DTB read hits
+system.cpu1.dtb.read_misses 46174 # DTB read misses
+system.cpu1.dtb.write_hits 6180963 # DTB write hits
+system.cpu1.dtb.write_misses 11315 # DTB write misses
system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 702 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 7925 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1386 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 276 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 8574 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1449 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 627 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25201110 # DTB read accesses
-system.cpu1.dtb.write_accesses 5631431 # DTB write accesses
+system.cpu1.dtb.perms_faults 622 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 25888607 # DTB read accesses
+system.cpu1.dtb.write_accesses 6192278 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 30783163 # DTB hits
-system.cpu1.dtb.misses 49378 # DTB misses
-system.cpu1.dtb.accesses 30832541 # DTB accesses
-system.cpu1.itb.inst_hits 5244962 # ITB inst hits
-system.cpu1.itb.inst_misses 6670 # ITB inst misses
+system.cpu1.dtb.hits 32023396 # DTB hits
+system.cpu1.dtb.misses 57489 # DTB misses
+system.cpu1.dtb.accesses 32080885 # DTB accesses
+system.cpu1.itb.inst_hits 5862958 # ITB inst hits
+system.cpu1.itb.inst_misses 7630 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 702 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2650 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2762 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1456 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1655 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 5251632 # ITB inst accesses
-system.cpu1.itb.hits 5244962 # DTB hits
-system.cpu1.itb.misses 6670 # DTB misses
-system.cpu1.itb.accesses 5251632 # DTB accesses
-system.cpu1.numCycles 232013377 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 5870588 # ITB inst accesses
+system.cpu1.itb.hits 5862958 # DTB hits
+system.cpu1.itb.misses 7630 # DTB misses
+system.cpu1.itb.accesses 5870588 # DTB accesses
+system.cpu1.numCycles 238328292 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 6790425 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 5410391 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 343130 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 4365867 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 3552399 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 7461261 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 5924878 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 387688 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 4864845 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 3916001 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 675836 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 35150 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 14219364 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 41265528 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 6790425 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4228235 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 9330468 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2101425 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 82678 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 47674573 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 1053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 1954 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 48379 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 99398 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 108 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 5242833 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 267586 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2984 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 72923984 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.712246 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.058401 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 732677 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 39651 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 15658024 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 45723743 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 7461261 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4648678 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 10301295 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2449187 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 90048 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 49530341 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 1725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 2013 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 58322 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 105488 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 234 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5860623 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 343915 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3550 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 77436496 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.743507 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.098927 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 63601422 87.22% 87.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 651379 0.89% 88.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 811870 1.11% 89.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1013874 1.39% 90.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 943793 1.29% 91.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 538574 0.74% 92.65% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1195574 1.64% 94.29% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 358365 0.49% 94.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3809133 5.22% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 67142740 86.71% 86.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 670388 0.87% 87.57% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 904116 1.17% 88.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1146258 1.48% 90.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1035072 1.34% 91.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 585216 0.76% 92.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1324002 1.71% 94.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 382858 0.49% 94.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4245846 5.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 72923984 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.029267 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.177858 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 15065111 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 47459427 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 8508787 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 504767 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1383740 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 935366 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 84721 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 49702311 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 283407 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1383740 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 15832821 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 18424865 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 25966015 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 8176580 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3137893 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 47902393 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 7520 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 511770 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 2112759 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 14566 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 49459920 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 218567938 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 218526163 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 41775 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 37332689 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 12127230 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 420234 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 377586 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 6217035 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9300150 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6339076 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 983520 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1172387 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 44745095 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 970903 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 59171295 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 83947 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 8398889 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 19786111 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 243126 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 72923984 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.811411 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.516236 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 77436496 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.031307 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.191852 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 16603606 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 49335429 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 9407116 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 490405 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1597859 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1045633 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 93792 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 54840588 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 310696 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1597859 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 17482170 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 19064051 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 27065673 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 8938575 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 3286155 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 52466184 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 7798 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 497565 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 2245284 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 18515 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 54189093 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 239808372 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 239759506 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 48866 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 39935280 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 14253813 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 446450 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 393915 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 6702948 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 10122887 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6990261 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 974914 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1217289 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 48733638 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1005144 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 62551860 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 96432 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 9690546 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 24103101 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 245099 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 77436496 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.807783 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.518787 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 51567769 70.71% 70.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 6722785 9.22% 79.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3414540 4.68% 84.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2860255 3.92% 88.54% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6054704 8.30% 96.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1326273 1.82% 98.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 714361 0.98% 99.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 204058 0.28% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 59239 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 54919142 70.92% 70.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 7063904 9.12% 80.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3691282 4.77% 84.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 2953327 3.81% 88.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6235094 8.05% 96.68% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1492250 1.93% 98.60% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 791283 1.02% 99.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 225625 0.29% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 64589 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 72923984 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 77436496 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 24658 0.56% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 2 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4170684 95.00% 95.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 195004 4.44% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 27571 0.62% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 1 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4198494 94.58% 95.20% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 213042 4.80% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 167246 0.28% 0.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 27298169 46.13% 46.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 44245 0.07% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 839 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.49% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 25732684 43.49% 89.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 5928100 10.02% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 169105 0.27% 0.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 29343777 46.91% 47.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 48983 0.08% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1277 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 26498919 42.36% 89.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6489779 10.38% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 59171295 # Type of FU issued
-system.cpu1.iq.rate 0.255034 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4390348 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.074197 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 195779484 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 54123667 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 40860194 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 10578 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 5727 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 4726 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 63388772 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 5625 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 295886 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 62551860 # Type of FU issued
+system.cpu1.iq.rate 0.262461 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4439108 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.070967 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 207120715 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 59438377 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 43832825 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 12343 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 6735 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 5565 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 66815352 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 6511 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 325479 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 1794199 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 2827 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 15001 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 687985 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2107508 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3797 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 16351 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 811464 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 17035415 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 238532 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 17060218 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 341441 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1383740 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 13800740 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 226965 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 45822265 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 96960 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9300150 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6339076 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 695770 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 48787 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3997 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 15001 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 167673 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 132287 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 299960 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 58435443 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25502557 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 735852 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1597859 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 14264833 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 247482 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 49856426 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 107204 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 10122887 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6990261 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 704284 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 59901 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3604 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 16351 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 190247 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 149600 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 339847 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 61552998 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 26188496 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 998862 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 106267 # number of nop insts executed
-system.cpu1.iew.exec_refs 31379358 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 5453104 # Number of branches executed
-system.cpu1.iew.exec_stores 5876801 # Number of stores executed
-system.cpu1.iew.exec_rate 0.251862 # Inst execution rate
-system.cpu1.iew.wb_sent 58051293 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 40864920 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 22407090 # num instructions producing a value
-system.cpu1.iew.wb_consumers 41228321 # num instructions consuming a value
+system.cpu1.iew.exec_nop 117644 # number of nop insts executed
+system.cpu1.iew.exec_refs 32619530 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5900270 # Number of branches executed
+system.cpu1.iew.exec_stores 6431034 # Number of stores executed
+system.cpu1.iew.exec_rate 0.258270 # Inst execution rate
+system.cpu1.iew.wb_sent 61059596 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 43838390 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 23681235 # num instructions producing a value
+system.cpu1.iew.wb_consumers 43694541 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.176132 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.543488 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.183941 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.541972 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 8312194 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 727777 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 259619 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 71540244 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.518566 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.491714 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 9661212 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 760045 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 295282 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 75838637 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.524766 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.504226 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 58151016 81.28% 81.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 6627858 9.26% 90.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1880092 2.63% 93.18% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1040741 1.45% 94.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 983750 1.38% 96.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 494100 0.69% 96.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 697389 0.97% 97.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 324169 0.45% 98.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1341129 1.87% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 61579117 81.20% 81.20% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 7021291 9.26% 90.46% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2015124 2.66% 93.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1085811 1.43% 94.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1003078 1.32% 95.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 577963 0.76% 96.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 742657 0.98% 97.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 378274 0.50% 98.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1435322 1.89% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 71540244 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 28738593 # Number of instructions committed
-system.cpu1.commit.committedOps 37098314 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 75838637 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 30577831 # Number of instructions committed
+system.cpu1.commit.committedOps 39797535 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13157042 # Number of memory references committed
-system.cpu1.commit.loads 7505951 # Number of loads committed
-system.cpu1.commit.membars 191336 # Number of memory barriers committed
-system.cpu1.commit.branches 4758017 # Number of branches committed
-system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 32847444 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 475803 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1341129 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 14194176 # Number of memory references committed
+system.cpu1.commit.loads 8015379 # Number of loads committed
+system.cpu1.commit.membars 209589 # Number of memory barriers committed
+system.cpu1.commit.branches 5113967 # Number of branches committed
+system.cpu1.commit.fp_insts 5513 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 35255841 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 515004 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1435322 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 114702650 # The number of ROB reads
-system.cpu1.rob.rob_writes 92242025 # The number of ROB writes
-system.cpu1.timesIdled 868716 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 159089393 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2323530978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 28667140 # Number of Instructions Simulated
-system.cpu1.committedOps 37026861 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 28667140 # Number of Instructions Simulated
-system.cpu1.cpi 8.093356 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 8.093356 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.123558 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.123558 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 264545362 # number of integer regfile reads
-system.cpu1.int_regfile_writes 41743183 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 22037 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 19620 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 14602821 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 442325 # number of misc regfile writes
+system.cpu1.rob.rob_reads 122900984 # The number of ROB reads
+system.cpu1.rob.rob_writes 100566633 # The number of ROB writes
+system.cpu1.timesIdled 901138 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 160891796 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2255172449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 30498934 # Number of Instructions Simulated
+system.cpu1.committedOps 39718638 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 30498934 # Number of Instructions Simulated
+system.cpu1.cpi 7.814315 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 7.814315 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.127970 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.127970 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 279110946 # number of integer regfile reads
+system.cpu1.int_regfile_writes 44685160 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 22658 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 19886 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 15820673 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 438571 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125347676632 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1125347676632 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125347676632 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1125347676632 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1125362728944 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1125362728944 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 88038 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 83058 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 0.164568 # Number of seconds simulated
-sim_ticks 164568389500 # Number of ticks simulated
-final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.164543 # Number of seconds simulated
+sim_ticks 164543008000 # Number of ticks simulated
+final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61098 # Simulator instruction rate (inst/s)
-host_op_rate 64561 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17638362 # Simulator tick rate (ticks/s)
-host_mem_usage 233000 # Number of bytes of host memory used
-host_seconds 9330.14 # Real time elapsed on the host
-sim_insts 570052720 # Number of instructions simulated
-sim_ops 602360926 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1702080 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1749184 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 47104 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 47104 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory
-system.physmem.bytes_written::total 162368 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 736 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26595 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27331 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 286228 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 10342691 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10628919 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 286228 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 286228 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 986629 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 986629 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 986629 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 286228 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 10342691 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11615548 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27332 # Total number of read requests seen
-system.physmem.writeReqs 2537 # Total number of write requests seen
-system.physmem.cpureqs 29869 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1749184 # Total number of bytes read from memory
-system.physmem.bytesWritten 162368 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1749184 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize()
+host_inst_rate 153982 # Simulator instruction rate (inst/s)
+host_op_rate 162709 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44446364 # Simulator tick rate (ticks/s)
+host_mem_usage 244392 # Number of bytes of host memory used
+host_seconds 3702.06 # Real time elapsed on the host
+sim_insts 570051585 # Number of instructions simulated
+sim_ops 602359791 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1700992 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1747904 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 46912 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 46912 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 162560 # Number of bytes written to this memory
+system.physmem.bytes_written::total 162560 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 733 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26578 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27311 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 2540 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2540 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 285105 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 10337674 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10622779 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 285105 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 285105 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 987948 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 987948 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 987948 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 285105 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 10337674 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11610727 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27312 # Total number of read requests seen
+system.physmem.writeReqs 2540 # Total number of write requests seen
+system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1747904 # Total number of bytes read from memory
+system.physmem.bytesWritten 162560 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1747904 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 162560 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1696 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1706 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1737 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1704 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1733 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1675 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1745 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1734 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1739 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1674 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1718 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1743 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1723 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1723 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1673 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1741 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 160 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 160 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 164568372500 # Total gap between requests
+system.physmem.totGap 164542992000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27332 # Categorize read packet sizes
+system.physmem.readPktSize::6 27312 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 2537 # categorize write packet sizes
+system.physmem.writePktSize::6 2540 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 14894 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2844 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 8804 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 783 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 14941 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2772 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 8807 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 785 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 953339495 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1657961495 # Sum of mem lat for all requests
-system.physmem.totBusLat 109328000 # Total cycles spent in databus access
-system.physmem.totBankLat 595294000 # Total cycles spent in bank access
-system.physmem.avgQLat 34879.98 # Average queueing delay per request
-system.physmem.avgBankLat 21780.11 # Average bank access latency per request
+system.physmem.totQLat 954202972 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1658730972 # Sum of mem lat for all requests
+system.physmem.totBusLat 109248000 # Total cycles spent in databus access
+system.physmem.totBankLat 595280000 # Total cycles spent in bank access
+system.physmem.avgQLat 34937.13 # Average queueing delay per request
+system.physmem.avgBankLat 21795.55 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 60660.09 # Average memory access latency
-system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 60732.68 # Average memory access latency
+system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.07 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 6.05 # Average write queue length over time
-system.physmem.readRowHits 17765 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1091 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes
-system.physmem.avgGap 5509671.31 # Average gap between requests
+system.physmem.avgWrQLen 7.51 # Average write queue length over time
+system.physmem.readRowHits 17750 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1096 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes
+system.physmem.avgGap 5511958.73 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 329136780 # number of cpu cycles simulated
+system.cpu.numCycles 329086017 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 85146783 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 79928286 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2342158 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 47212748 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 46871026 # Number of BTB hits
+system.cpu.BPredUnit.lookups 85130885 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 79914937 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 2339051 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 47115734 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 46860934 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 68501012 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 119329476 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 67084221 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 755002 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 328178875 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1427305 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 879 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 48288239 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 129602885 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 13082707 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 119327277 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 198 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 67069040 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 754631 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 328130780 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.165288 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.193984 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 198558186 60.50% 60.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8890662 2.71% 75.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 9436402 2.88% 78.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4398507 1.34% 79.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 5788329 1.76% 81.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 198528126 60.50% 60.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 20911347 6.37% 66.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 4965496 1.51% 68.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 14342607 4.37% 72.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8889042 2.71% 75.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 9432606 2.87% 78.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4398382 1.34% 79.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 5787527 1.76% 81.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 60875647 18.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 328178875 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96199179 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4737184 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 1561 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 703240498 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 5895 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 10725676 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 114043085 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 694816428 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 328130780 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.258689 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.026017 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 92913811 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96211222 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 107901766 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20387668 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10716313 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4735353 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1507 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 703148359 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 5732 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 10716313 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 107108772 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14420824 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 39598 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 114018818 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 81826455 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 694730633 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 721301805 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3230529005 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3230528877 # Number of integer rename lookups
+system.cpu.rename.IQFullEvents 59350869 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 20332423 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 690 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 721206841 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3230143140 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3230143012 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 93882616 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 172202980 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 80458110 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 21583677 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 28704390 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 679987725 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3320 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 645601186 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1370428 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 328178875 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 93789468 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1631 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1577 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 170614097 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 172186244 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 80451329 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 21497797 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 28523197 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 679922328 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2842 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 645571900 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1371428 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 77382290 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 193030922 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 138 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 328130780 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.967423 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.726248 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 68164684 20.77% 20.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 28810425 8.78% 91.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 14904242 4.54% 95.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5586841 1.70% 97.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 6537919 1.99% 99.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 68155781 20.77% 20.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 85368264 26.02% 46.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 75828661 23.11% 69.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 40814489 12.44% 82.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 28806063 8.78% 91.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 14910916 4.54% 95.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 5593541 1.70% 97.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 6461751 1.97% 99.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2191314 0.67% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 328178875 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 328130780 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2691247 71.35% 77.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 863918 22.90% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 217275 5.77% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2690091 71.47% 77.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 856746 22.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 403371869 62.48% 62.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 403353378 62.48% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 165559477 25.64% 88.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 76663269 11.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 165552451 25.64% 88.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 76659500 11.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 645601186 # Type of FU issued
-system.cpu.iq.rate 1.961498 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1624523749 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 645571900 # Type of FU issued
+system.cpu.iq.rate 1.961712 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3764112 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.005831 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1624410084 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 757319559 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 637543970 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 649373276 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 649335992 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 30369655 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 30371258 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 23250160 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 123060 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12375 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10236870 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 23233651 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 124604 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 12357 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 10230316 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12923 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 32784 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 12884 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 32539 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 10725676 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 690728 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 32845 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 16029 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12375 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1358556 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1460812 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2819368 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 641523461 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 163490704 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4077725 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10716313 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 798788 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 92055 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 679928215 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 686727 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 172186244 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 80451329 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1514 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 33028 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 15856 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 12357 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1355593 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1460304 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2815897 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 641504035 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 163487420 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4067865 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3107 # number of nop insts executed
-system.cpu.iew.exec_refs 239380202 # number of memory reference insts executed
-system.cpu.iew.exec_branches 74672586 # Number of branches executed
-system.cpu.iew.exec_stores 75889498 # Number of stores executed
-system.cpu.iew.exec_rate 1.949109 # Inst execution rate
-system.cpu.iew.wb_sent 638973087 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 637563068 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 418509904 # num instructions producing a value
-system.cpu.iew.wb_consumers 649810327 # num instructions consuming a value
+system.cpu.iew.exec_nop 3045 # number of nop insts executed
+system.cpu.iew.exec_refs 239375677 # number of memory reference insts executed
+system.cpu.iew.exec_branches 74669000 # Number of branches executed
+system.cpu.iew.exec_stores 75888257 # Number of stores executed
+system.cpu.iew.exec_rate 1.949351 # Inst execution rate
+system.cpu.iew.wb_sent 638951120 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 637543986 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 418515101 # num instructions producing a value
+system.cpu.iew.wb_consumers 649819096 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.937076 # insts written-back per cycle
+system.cpu.iew.wb_rate 1.937317 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 77641136 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2340694 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 317453199 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.897480 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.237382 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 77576557 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 2337624 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 317414467 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.897708 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.237617 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 93244159 29.37% 29.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 104350587 32.87% 62.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 42987524 13.54% 75.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8793922 2.77% 78.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25958876 8.18% 86.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 12900336 4.06% 90.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 7627072 2.40% 93.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1171824 0.37% 93.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 20418899 6.43% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 93227454 29.37% 29.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 104339541 32.87% 62.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 42982023 13.54% 75.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 8785495 2.77% 78.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25936003 8.17% 86.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 12920810 4.07% 90.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7630828 2.40% 93.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1171764 0.37% 93.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 20420549 6.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 317453199 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 570052771 # Number of instructions committed
-system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 317414467 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 570051636 # Number of instructions committed
+system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 219174060 # Number of memory references committed
-system.cpu.commit.loads 148952820 # Number of loads committed
+system.cpu.commit.refs 219173606 # Number of memory references committed
+system.cpu.commit.loads 148952593 # Number of loads committed
system.cpu.commit.membars 1328 # Number of memory barriers committed
-system.cpu.commit.branches 70892751 # Number of branches committed
+system.cpu.commit.branches 70892524 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 533523539 # Number of committed integer instructions.
+system.cpu.commit.int_insts 533522631 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 20418899 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 20420549 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 977035801 # The number of ROB reads
-system.cpu.rob.rob_writes 1370761733 # The number of ROB writes
-system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 957905 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 570052720 # Number of Instructions Simulated
-system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated
-system.cpu.cpi 0.577380 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.577380 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.731963 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.731963 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3204362065 # number of integer regfile reads
-system.cpu.int_regfile_writes 663044095 # number of integer regfile writes
+system.cpu.rob.rob_reads 976929705 # The number of ROB reads
+system.cpu.rob.rob_writes 1370620821 # The number of ROB writes
+system.cpu.timesIdled 41180 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 955237 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 570051585 # Number of Instructions Simulated
+system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated
+system.cpu.cpi 0.577292 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.577292 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.732227 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.732227 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3204271897 # number of integer regfile reads
+system.cpu.int_regfile_writes 663022837 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 234776328 # number of misc regfile reads
-system.cpu.misc_regfile_writes 3110 # number of misc regfile writes
-system.cpu.icache.replacements 60 # number of replacements
-system.cpu.icache.tagsinuse 685.359263 # Cycle average of tags in use
-system.cpu.icache.total_refs 67083066 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 820 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 81808.617073 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 234769906 # number of misc regfile reads
+system.cpu.misc_regfile_writes 2656 # number of misc regfile writes
+system.cpu.icache.replacements 58 # number of replacements
+system.cpu.icache.tagsinuse 683.079303 # Cycle average of tags in use
+system.cpu.icache.total_refs 67067899 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 817 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 82090.451652 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 685.359263 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.334648 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.334648 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 67083066 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 67083066 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 67083066 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits
-system.cpu.icache.overall_hits::total 67083066 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1155 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1155 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1155 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1155 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1155 # number of overall misses
-system.cpu.icache.overall_misses::total 1155 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 51421999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 51421999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 51421999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 51421999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 51421999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 51421999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 67084221 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 67084221 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 67084221 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 67084221 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 67084221 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 67084221 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 683.079303 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.333535 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.333535 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 67067899 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 67067899 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 67067899 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 67067899 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 67067899 # number of overall hits
+system.cpu.icache.overall_hits::total 67067899 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses
+system.cpu.icache.overall_misses::total 1141 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 51270999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 51270999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 51270999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 51270999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 51270999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 51270999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 67069040 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 67069040 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 67069040 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 67069040 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 67069040 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 67069040 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44521.211255 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 44521.211255 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 44521.211255 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 44521.211255 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44935.143734 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 44935.143734 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 44935.143734 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 44935.143734 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 44.555556 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 335 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 335 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 335 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 335 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 335 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38656999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 38656999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38656999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 38656999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38656999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 38656999 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 322 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 322 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 322 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 322 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 322 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39128499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 39128499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39128499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 39128499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39128499 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 39128499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47142.681707 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47142.681707 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47775.945055 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47775.945055 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47775.945055 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 47775.945055 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47775.945055 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 47775.945055 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 2559 # number of replacements
-system.cpu.l2cache.tagsinuse 22365.188888 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 2562 # number of replacements
+system.cpu.l2cache.tagsinuse 22345.080888 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 517383 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 24154 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 21.420179 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20763.498620 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 646.825199 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 954.865069 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.633652 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.019740 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.029140 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.682531 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 81 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 192805 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 192886 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 421636 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 421636 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 225369 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 225369 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 81 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 418174 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 418255 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 81 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 418174 # number of overall hits
-system.cpu.l2cache.overall_hits::total 418255 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 739 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 4814 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 5553 # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::writebacks 20760.293948 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 643.441909 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 941.345031 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.633554 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.019636 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.028728 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.681918 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 83 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 192708 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 192791 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 421605 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 421605 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 225373 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 225373 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 83 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 418081 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 418164 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 83 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 418081 # number of overall hits
+system.cpu.l2cache.overall_hits::total 418164 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 735 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 4798 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 5533 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21790 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21790 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 739 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 26604 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 27343 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 739 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 26604 # number of overall misses
-system.cpu.l2cache.overall_misses::total 27343 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37000500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728777500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 765778000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 1545376500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 37000500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 2274154000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 2311154500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 37000500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 2274154000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 2311154500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 197619 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 198439 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 421636 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 421636 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 247159 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 247159 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 444778 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 445598 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 444778 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 445598 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.901220 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024360 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.027983 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088162 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.088162 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.901220 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.059814 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.061362 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.901220 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.059814 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.061362 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50068.335589 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.100125 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.475599 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.363011 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.363011 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 84524.540102 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 84524.540102 # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst 735 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 26588 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 27323 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 735 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 26588 # number of overall misses
+system.cpu.l2cache.overall_misses::total 27323 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37457000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728477000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 765934000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545495500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1545495500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 37457000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 2273972500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 2311429500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 37457000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 2273972500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 2311429500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 818 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 197506 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 198324 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 421605 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 421605 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 247163 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 247163 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 818 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 444669 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 445487 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 818 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 444669 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 445487 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.898533 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024293 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.027899 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088160 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.088160 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.898533 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.059793 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.061333 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.898533 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.059793 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.061333 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50961.904762 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151829.303877 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 138430.146394 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70926.824231 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70926.824231 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50961.904762 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85526.271250 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 84596.475497 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50961.904762 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85526.271250 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 84596.475497 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 2537 # number of writebacks
-system.cpu.l2cache.writebacks::total 2537 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks 2540 # number of writebacks
+system.cpu.l2cache.writebacks::total 2540 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 736 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4806 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 5542 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4789 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 5522 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21790 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21790 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 736 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 26596 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 27332 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 26596 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 27332 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342173 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668139562 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695481735 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273791296 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273791296 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342173 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941930858 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 1969273031 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342173 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941930858 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1969273031 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024320 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027928 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088162 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088162 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.061338 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.061338 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37149.691576 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139021.964628 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125492.915013 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.608811 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.608811 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 26579 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 27312 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 26579 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 27312 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27884656 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 667944528 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695829184 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273842866 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273842866 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27884656 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941787394 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 1969672050 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27884656 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941787394 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 1969672050 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024247 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027843 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088160 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088160 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.061308 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.061308 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38041.822647 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139474.739612 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126010.355668 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58459.975493 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58459.975493 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 440681 # number of replacements
-system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use
-system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits
-system.cpu.dcache.overall_hits::total 197562725 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses
-system.cpu.dcache.overall_misses::total 3714801 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159649500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5159649500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250552202 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 40250552202 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 45410201702 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 45410201702 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 45410201702 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 45410201702 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 131859995 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements 440572 # number of replacements
+system.cpu.dcache.tagsinuse 4091.500520 # Cycle average of tags in use
+system.cpu.dcache.total_refs 197561073 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 444668 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 444.288937 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 320822000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4091.500520 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.998901 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.998901 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 131514845 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 131514845 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 66043576 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 66043576 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1323 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 1323 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 197558421 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 197558421 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 197558421 # number of overall hits
+system.cpu.dcache.overall_hits::total 197558421 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 341798 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 341798 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3373955 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3373955 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 20 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 20 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 3715753 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3715753 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3715753 # number of overall misses
+system.cpu.dcache.overall_misses::total 3715753 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5154955000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5154955000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 40277017700 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 40277017700 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 312000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 312000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 45431972700 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 45431972700 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 45431972700 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 45431972700 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 131856643 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 131856643 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.944558 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.944558 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.925268 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.925268 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12224.127673 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12224.127673 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 201274174 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 201274174 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 201274174 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 201274174 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048604 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.048604 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.014892 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.014892 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.018461 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.018461 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.018461 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.018461 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15081.875845 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15081.875845 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11937.627414 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 11937.627414 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15600 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15600 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12226.854880 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12226.854880 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 132982 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 4828 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.543911 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks
-system.cpu.dcache.writebacks::total 421636 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060484256 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060484256 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.143266 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.143266 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.631998 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.631998 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 421606 # number of writebacks
+system.cpu.dcache.writebacks::total 421606 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144292 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 144292 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3126791 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3126791 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 20 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3271083 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3271083 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3271083 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3271083 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197506 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 197506 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247164 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 247164 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 444670 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 444670 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 444670 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 444670 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2876994000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2876994000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4061058256 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4061058256 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6938052256 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6938052256 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938052256 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6938052256 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14566.615698 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14566.615698 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16430.622000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16430.622000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.026786 # Number of seconds simulated
-sim_ticks 26786364500 # Number of ticks simulated
-final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.026773 # Number of seconds simulated
+sim_ticks 26773408500 # Number of ticks simulated
+final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55091 # Simulator instruction rate (inst/s)
-host_op_rate 55487 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16288150 # Simulator tick rate (ticks/s)
-host_mem_usage 365372 # Number of bytes of host memory used
-host_seconds 1644.53 # Real time elapsed on the host
-sim_insts 90599358 # Number of instructions simulated
-sim_ops 91249911 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992768 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15512 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1689218 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35373221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 37062439 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1689218 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1689218 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1689218 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35373221 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 37062439 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15512 # Total number of read requests seen
+host_inst_rate 153523 # Simulator instruction rate (inst/s)
+host_op_rate 154625 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45373007 # Simulator tick rate (ticks/s)
+host_mem_usage 376436 # Number of bytes of host memory used
+host_seconds 590.07 # Real time elapsed on the host
+sim_insts 90589798 # Number of instructions simulated
+sim_ops 91240351 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory
+system.physmem.bytes_read::total 992576 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15509 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1680473 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 35392729 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 37073203 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1680473 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1680473 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1680473 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 35392729 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 37073203 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15509 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 15514 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 992768 # Total number of bytes read from memory
+system.physmem.cpureqs 15512 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 992576 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 992768 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 992576 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1014 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 997 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 999 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 964 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 877 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 941 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1012 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 976 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 936 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 991 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1011 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 928 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 930 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 933 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1021 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 978 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 976 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26786186500 # Total gap between requests
+system.physmem.totGap 26773229500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 15512 # Categorize read packet sizes
+system.physmem.readPktSize::6 15509 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 2 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 3 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 10748 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 10802 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4514 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 45051479 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests
-system.physmem.totBusLat 62048000 # Total cycles spent in databus access
-system.physmem.totBankLat 172004000 # Total cycles spent in bank access
-system.physmem.avgQLat 2904.30 # Average queueing delay per request
-system.physmem.avgBankLat 11088.45 # Average bank access latency per request
+system.physmem.totQLat 45602981 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 279992981 # Sum of mem lat for all requests
+system.physmem.totBusLat 62036000 # Total cycles spent in databus access
+system.physmem.totBankLat 172354000 # Total cycles spent in bank access
+system.physmem.avgQLat 2940.42 # Average queueing delay per request
+system.physmem.avgBankLat 11113.16 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 17992.75 # Average memory access latency
-system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 18053.58 # Average memory access latency
+system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 15087 # Number of row buffer hits during reads
+system.physmem.readRowHits 15086 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1726804.18 # Average gap between requests
+system.physmem.avgGap 1726302.76 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53572730 # number of cpu cycles simulated
+system.cpu.numCycles 53546818 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 26681190 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 22001511 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 842165 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11371976 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11281654 # Number of BTB hits
+system.cpu.BPredUnit.lookups 26672080 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 21992542 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 842598 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 11362388 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 11268059 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 70167 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11338226 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24008993 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4747196 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 11262084 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 13843627 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 330314 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 53334178 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.412341 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.215312 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1666559 3.12% 71.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2918525 5.47% 76.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1512890 2.84% 79.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1090822 2.04% 81.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 29363698 55.06% 55.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3375400 6.33% 61.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2026423 3.80% 65.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1553443 2.91% 68.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1668565 3.13% 71.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2920644 5.48% 76.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1511002 2.83% 79.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1091875 2.05% 81.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9823128 18.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4441470 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126048465 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42747 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3892391 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 53334178 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.498108 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.386304 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16944806 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9096910 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22405465 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1004110 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3882887 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4441553 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 8682 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 125956281 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 42689 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3882887 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18731656 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3549082 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 155235 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21520684 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5494634 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 123060237 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29470902 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5524793 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2121904 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1282766 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118150173 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 10438 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105160593 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 79722 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle
+system.cpu.rename.IQFullEvents 429079 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4593412 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1240 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 143474506 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 536032151 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 536027496 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4655 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 36060320 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4617 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 4615 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12531131 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29463379 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5514746 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2152870 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1249780 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 118072720 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 8484 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 105142122 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 71988 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26643181 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 65222929 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 266 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 53334178 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.971384 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.909777 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4978396 9.33% 88.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2962958 5.55% 93.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2475458 4.64% 98.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 518730 0.97% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 15298443 28.68% 28.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 11631181 21.81% 50.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8279084 15.52% 66.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6786399 12.72% 78.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4950529 9.28% 88.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2953624 5.54% 93.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2464815 4.62% 98.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 526374 0.99% 99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 443729 0.83% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 53334178 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 340422 51.49% 58.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 275350 41.65% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 44991 6.81% 6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 27 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 339313 51.37% 58.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 276174 41.81% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74420683 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74410825 70.77% 70.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10970 0.01% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 146 0.00% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 182 0.00% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25610261 24.35% 95.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5118329 4.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25604346 24.35% 95.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5115650 4.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105160593 # Type of FU issued
-system.cpu.iq.rate 1.962950 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1049 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 331 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105821300 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 443954 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105142122 # Type of FU issued
+system.cpu.iq.rate 1.963555 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 660505 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006282 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 264350195 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 144728935 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 102671361 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 720 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1005 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 105802266 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 361 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 442877 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6895024 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7123 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6272 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 778037 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6889413 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6770 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 6285 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 769902 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31249 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 27948 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3892391 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 66339 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6977 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6272 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446356 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 445453 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 891809 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104181304 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25288567 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 979289 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3882887 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 927098 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 127053 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 118093920 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 309711 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29463379 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5514746 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 4596 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 66094 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 6965 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 6285 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 446526 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 446132 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 892658 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104164248 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25284832 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 977874 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12695 # number of nop insts executed
-system.cpu.iew.exec_refs 30349931 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21325057 # Number of branches executed
-system.cpu.iew.exec_stores 5061364 # Number of stores executed
-system.cpu.iew.exec_rate 1.944670 # Inst execution rate
-system.cpu.iew.wb_sent 102965645 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102686542 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62242061 # num instructions producing a value
-system.cpu.iew.wb_consumers 104289210 # num instructions consuming a value
+system.cpu.iew.exec_nop 12716 # number of nop insts executed
+system.cpu.iew.exec_refs 30343472 # number of memory reference insts executed
+system.cpu.iew.exec_branches 21324084 # Number of branches executed
+system.cpu.iew.exec_stores 5058640 # Number of stores executed
+system.cpu.iew.exec_rate 1.945293 # Inst execution rate
+system.cpu.iew.wb_sent 102950061 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102671670 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 62244850 # num instructions producing a value
+system.cpu.iew.wb_consumers 104302213 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.916769 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596822 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.917419 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.596774 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26913567 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 833602 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 49467817 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.844887 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.541636 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 26843909 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 834006 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 49451291 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.845310 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.541193 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19986876 40.40% 40.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13133000 26.55% 66.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4163273 8.42% 75.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3434953 6.94% 82.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1533681 3.10% 85.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 739386 1.49% 86.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 948988 1.92% 88.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 248747 0.50% 89.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5278913 10.67% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 19963736 40.37% 40.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13137085 26.57% 66.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4166734 8.43% 75.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3433201 6.94% 82.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1540600 3.12% 85.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 738938 1.49% 86.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 946959 1.91% 88.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 248344 0.50% 89.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5275694 10.67% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 49467817 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90611967 # Number of instructions committed
-system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 49451291 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 90602407 # Number of instructions committed
+system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27322634 # Number of memory references committed
-system.cpu.commit.loads 22575878 # Number of loads committed
+system.cpu.commit.refs 27318810 # Number of memory references committed
+system.cpu.commit.loads 22573966 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18734216 # Number of branches committed
+system.cpu.commit.branches 18732304 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72533322 # Number of committed integer instructions.
+system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5278913 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5275694 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162359257 # The number of ROB reads
-system.cpu.rob.rob_writes 240263976 # The number of ROB writes
-system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90599358 # Number of Instructions Simulated
-system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated
-system.cpu.cpi 0.591315 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.591315 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.691147 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.691147 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495578845 # number of integer regfile reads
-system.cpu.int_regfile_writes 120555497 # number of integer regfile writes
-system.cpu.fp_regfile_reads 176 # number of floating regfile reads
-system.cpu.fp_regfile_writes 427 # number of floating regfile writes
-system.cpu.misc_regfile_reads 29099412 # number of misc regfile reads
-system.cpu.misc_regfile_writes 11608 # number of misc regfile writes
-system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 632.599736 # Cycle average of tags in use
-system.cpu.icache.total_refs 13840965 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 735 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 18831.244898 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 162266732 # The number of ROB reads
+system.cpu.rob.rob_writes 240096387 # The number of ROB writes
+system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 212640 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 90589798 # Number of Instructions Simulated
+system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
+system.cpu.cpi 0.591091 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.591091 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.691787 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.691787 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 495496065 # number of integer regfile reads
+system.cpu.int_regfile_writes 120529637 # number of integer regfile writes
+system.cpu.fp_regfile_reads 153 # number of floating regfile reads
+system.cpu.fp_regfile_writes 387 # number of floating regfile writes
+system.cpu.misc_regfile_reads 29090556 # number of misc regfile reads
+system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
+system.cpu.icache.replacements 5 # number of replacements
+system.cpu.icache.tagsinuse 628.046446 # Cycle average of tags in use
+system.cpu.icache.total_refs 13842647 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 730 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 18962.530137 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 632.599736 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.308887 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.308887 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 13840965 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13840965 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13840965 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits
-system.cpu.icache.overall_hits::total 13840965 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
-system.cpu.icache.overall_misses::total 984 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 628.046446 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.306663 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.306663 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 13842647 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 13842647 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 13842647 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 13842647 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 13842647 # number of overall hits
+system.cpu.icache.overall_hits::total 13842647 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 979 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 979 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 979 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 979 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 979 # number of overall misses
+system.cpu.icache.overall_misses::total 979 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 47680999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 47680999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 47680999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 47680999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 47680999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 47680999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 13843626 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 13843626 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 13843626 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 13843626 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 13843626 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 13843626 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48703.778345 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48703.778345 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48703.778345 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48703.778345 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48703.778345 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48703.778345 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1057 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 132.125000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36763999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 36763999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36763999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 36763999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36763999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 36763999 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 736 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 736 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 736 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 736 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 736 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36881499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 36881499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36881499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 36881499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36881499 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 36881499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49748.307172 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49748.307172 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50110.732337 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50110.732337 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50110.732337 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50110.732337 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50110.732337 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50110.732337 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 10757.788342 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1831577 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 15495 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 118.204389 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 10753.787998 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1831539 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 15492 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 118.224826 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 9910.182329 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 617.983134 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 229.622878 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.302435 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.018859 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.007008 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.328302 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 903798 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 903825 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 942892 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 942892 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 28978 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 28978 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 932776 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 932803 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 932776 # number of overall hits
-system.cpu.l2cache.overall_hits::total 932803 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::writebacks 9912.286779 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 615.112127 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 226.389092 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.302499 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.018772 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.006909 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.328180 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 903771 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 903797 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 942884 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 942884 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 28990 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 28990 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 932761 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 932787 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 932761 # number of overall hits
+system.cpu.l2cache.overall_hits::total 932787 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 277 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 985 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 14815 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 15523 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 14815 # number of overall misses
-system.cpu.l2cache.overall_misses::total 15523 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35741000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14542000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 50283000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 602811500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 602811500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 35741000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 617353500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 653094500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 35741000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 617353500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 653094500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 904075 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 904810 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 942892 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 942892 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 43516 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 43516 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 735 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 947591 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 948326 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 735 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 947591 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 948326 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963265 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses::total 981 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 14539 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 14539 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 14816 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 15520 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 14816 # number of overall misses
+system.cpu.l2cache.overall_misses::total 15520 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35867500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14359000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 50226500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 603417500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 603417500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 35867500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 617776500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 653644000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 35867500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 617776500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 653644000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 730 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 904048 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 904778 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 942884 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 942884 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 43529 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 43529 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 730 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 947577 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 948307 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 730 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 947577 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 948307 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964384 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000306 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.001084 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.334084 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.334084 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963265 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.015634 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.016369 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963265 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.016369 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50481.638418 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52498.194946 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.730964 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41464.541202 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41464.541202 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 42072.698576 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50481.638418 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 42072.698576 # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.334007 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.334007 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964384 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.016366 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964384 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.016366 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50948.153409 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51837.545126 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51199.286442 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41503.370246 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41503.370246 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50948.153409 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41696.578024 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 42116.237113 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50948.153409 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41696.578024 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 42116.237113 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 974 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 15512 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 15512 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819584 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10783379 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602963 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 420800342 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 420800342 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819584 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431583721 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 458403305 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819584 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431583721 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 458403305 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14539 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 14539 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 15509 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 15509 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26990085 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10560900 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37550985 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 421398919 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 421398919 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26990085 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431959819 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 458949904 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26990085 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431959819 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 458949904 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001072 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.334084 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.334084 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.016357 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.016357 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37934.347949 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40387.187266 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.738193 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.334007 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.334007 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.016354 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.016354 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38392.724040 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39553.932584 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38712.355670 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28984.037348 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28984.037348 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 943495 # number of replacements
-system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
-system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
-system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
-system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements 943481 # number of replacements
+system.cpu.dcache.tagsinuse 3674.468837 # Cycle average of tags in use
+system.cpu.dcache.total_refs 28144290 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 947577 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 29.701322 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 7935444000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3674.468837 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.897087 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.897087 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 23599200 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 23599200 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4537276 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4537276 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 28136476 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 28136476 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 28136476 # number of overall hits
+system.cpu.dcache.overall_hits::total 28136476 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1173036 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1173036 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 197705 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 197705 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1370741 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1370741 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1370741 # number of overall misses
+system.cpu.dcache.overall_misses::total 1370741 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 13886322000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 13886322000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5375913921 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5375913921 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 19262235921 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 19262235921 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 19262235921 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 19262235921 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 24772236 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 24772236 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 29507217 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 29507217 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 29507217 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 29507217 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047353 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.047353 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041754 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.041754 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.046454 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.046454 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.046454 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.046454 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.933363 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.933363 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27191.593136 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27191.593136 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29214.285714 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29214.285714 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14052.425601 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14052.425601 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 132657 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 23814 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.570547 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
-system.cpu.dcache.writebacks::total 942892 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks
+system.cpu.dcache.writebacks::total 942884 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268972 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 268972 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154186 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 154186 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 423158 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 423158 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 423158 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 423158 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904064 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 904064 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43519 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43519 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 947583 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 947583 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 947583 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 947583 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9987518000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9987518000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 958248463 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 958248463 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945766463 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10945766463 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945766463 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10945766463 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036495 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036495 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009191 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009191 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032114 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032114 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11047.357267 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11047.357267 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22019.082768 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22019.082768 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 65982862500 # Number of ticks simulated
final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 39069 # Simulator instruction rate (inst/s)
-host_op_rate 68794 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16316772 # Simulator tick rate (ticks/s)
-host_mem_usage 376348 # Number of bytes of host memory used
-host_seconds 4043.87 # Real time elapsed on the host
+host_inst_rate 97221 # Simulator instruction rate (inst/s)
+host_op_rate 171190 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 40603649 # Simulator tick rate (ticks/s)
+host_mem_usage 385836 # Number of bytes of host memory used
+host_seconds 1625.05 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
system.cpu.iq.iqInstsIssued 302165189 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 115128 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 36987116 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 54145851 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 54145843 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 131886743 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.291096 # Number of insts issued each cycle
system.cpu.iq.fu_busy_rate 0.006480 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 738289800 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 352827074 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 299525455 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses 299525457 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 863 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses
system.cpu.iew.exec_stores 33015298 # Number of stores executed
system.cpu.iew.exec_rate 2.277456 # Inst execution rate
system.cpu.iew.wb_sent 299954363 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 299525609 # cumulative count of insts written-back
+system.cpu.iew.wb_count 299525611 # cumulative count of insts written-back
system.cpu.iew.wb_producers 219474385 # num instructions producing a value
system.cpu.iew.wb_consumers 297941322 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
---------- Begin Simulation Statistics ----------
-sim_seconds 0.206007 # Number of seconds simulated
-sim_ticks 206006891000 # Number of ticks simulated
-final_tick 206006891000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.199845 # Number of seconds simulated
+sim_ticks 199845137000 # Number of ticks simulated
+final_tick 199845137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48397 # Simulator instruction rate (inst/s)
-host_op_rate 54519 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19589283 # Simulator tick rate (ticks/s)
-host_mem_usage 261836 # Number of bytes of host memory used
-host_seconds 10516.31 # Real time elapsed on the host
-sim_insts 508955198 # Number of instructions simulated
-sim_ops 573341758 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 216256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9272640 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9488896 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 216256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 216256 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6250240 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6250240 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3379 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144885 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 148264 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97660 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97660 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1049751 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 45011310 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 46061061 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1049751 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1049751 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 30339956 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 30339956 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 30339956 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1049751 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 45011310 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 76401017 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 148265 # Total number of read requests seen
-system.physmem.writeReqs 97660 # Total number of write requests seen
-system.physmem.cpureqs 245934 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 9488896 # Total number of bytes read from memory
-system.physmem.bytesWritten 6250240 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 9488896 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6250240 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 9228 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 9341 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 8794 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 9227 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 8981 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 9254 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 9466 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 9155 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10302 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 9694 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9707 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 9134 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 8959 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 9019 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 8746 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5978 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 6111 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6105 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 5940 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 6130 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 6031 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 6368 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 6669 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 6289 # Track writes on a per bank basis
+host_inst_rate 125206 # Simulator instruction rate (inst/s)
+host_op_rate 141162 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 49524846 # Simulator tick rate (ticks/s)
+host_mem_usage 271424 # Number of bytes of host memory used
+host_seconds 4035.25 # Real time elapsed on the host
+sim_insts 505237723 # Number of instructions simulated
+sim_ops 569624283 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 216832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9264064 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9480896 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 216832 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 216832 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6248064 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6248064 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3388 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 144751 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 148139 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97626 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97626 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1085000 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 46356214 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 47441214 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1085000 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1085000 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 31264529 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 31264529 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 31264529 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1085000 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 46356214 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 78705743 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 148141 # Total number of read requests seen
+system.physmem.writeReqs 97626 # Total number of write requests seen
+system.physmem.cpureqs 245778 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 9480896 # Total number of bytes read from memory
+system.physmem.bytesWritten 6248064 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 9480896 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6248064 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 9221 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 9345 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8810 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 9230 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 8975 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9245 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 9467 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 9113 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10253 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 9691 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9704 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9106 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 8950 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 9023 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8762 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6117 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 5944 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6131 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 5962 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6376 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5947 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6637 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 6051 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 6056 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 5913 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 5774 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6036 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6064 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 5787 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 206006873500 # Total gap between requests
+system.physmem.totGap 199845120000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 148265 # Categorize read packet sizes
+system.physmem.readPktSize::6 148141 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 97660 # categorize write packet sizes
+system.physmem.writePktSize::6 97626 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 9 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 11 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 138270 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9286 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 138213 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9240 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 554 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4241 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4247 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4234 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1631933240 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 4708845240 # Sum of mem lat for all requests
-system.physmem.totBusLat 592780000 # Total cycles spent in databus access
-system.physmem.totBankLat 2484132000 # Total cycles spent in bank access
-system.physmem.avgQLat 11012.07 # Average queueing delay per request
-system.physmem.avgBankLat 16762.59 # Average bank access latency per request
+system.physmem.totQLat 1637260686 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4709936686 # Sum of mem lat for all requests
+system.physmem.totBusLat 592324000 # Total cycles spent in databus access
+system.physmem.totBankLat 2480352000 # Total cycles spent in bank access
+system.physmem.avgQLat 11056.52 # Average queueing delay per request
+system.physmem.avgBankLat 16749.97 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31774.66 # Average memory access latency
-system.physmem.avgRdBW 46.06 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 30.34 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 46.06 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 30.34 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31806.49 # Average memory access latency
+system.physmem.avgRdBW 47.44 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 31.26 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 47.44 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 31.26 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.48 # Data bus utilization in percentage
+system.physmem.busUtil 0.49 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 8.58 # Average write queue length over time
-system.physmem.readRowHits 128622 # Number of row buffer hits during reads
-system.physmem.writeRowHits 35037 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.79 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 35.88 # Row buffer hit rate for writes
-system.physmem.avgGap 837681.71 # Average gap between requests
+system.physmem.avgWrQLen 8.64 # Average write queue length over time
+system.physmem.readRowHits 128534 # Number of row buffer hits during reads
+system.physmem.writeRowHits 35160 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.80 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 36.01 # Row buffer hit rate for writes
+system.physmem.avgGap 813148.71 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 412013783 # number of cpu cycles simulated
+system.cpu.numCycles 399690275 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 182073557 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 142374329 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 7271583 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 93640941 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 88714986 # Number of BTB hits
+system.cpu.BPredUnit.lookups 182820446 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 143128871 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 7268870 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 92944153 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 87230072 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 12682930 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 115717 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 117168420 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 763090504 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 182073557 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 101397916 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 170904146 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 35690489 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 89173012 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 12684982 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 116077 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 119371931 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 761680364 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 182820446 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 99915054 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 170174199 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 35702256 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 75350704 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 387 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 113064693 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2443926 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 404864320 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.113664 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.961425 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 616 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 114527354 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2441016 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 392530086 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.176527 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.990721 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 233972788 57.79% 57.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14182494 3.50% 61.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22907477 5.66% 66.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22746192 5.62% 72.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20892499 5.16% 77.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13088798 3.23% 80.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13051042 3.22% 84.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 11993527 2.96% 87.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52029503 12.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 222368477 56.65% 56.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14183765 3.61% 60.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22901577 5.83% 66.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22747664 5.80% 71.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 20903604 5.33% 77.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 11591587 2.95% 80.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13062137 3.33% 83.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 11992821 3.06% 86.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52778454 13.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 404864320 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.441911 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.852099 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 127567795 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 83214346 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 161081773 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 5456100 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 27544306 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26131693 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 76746 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 833046476 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 293832 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 27544306 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 135636368 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 9592122 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 57998215 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158294561 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15798748 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 804356889 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3056071 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8809517 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 236 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 960228219 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3520047664 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3520046036 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1628 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672200251 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 288027968 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3037400 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 3037395 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 48984020 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 170948465 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 74181775 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 27930048 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15662241 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 757938362 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4467556 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 669004170 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1390745 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 187223839 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 479595431 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 746429 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 404864320 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.652416 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.728625 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 392530086 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.457405 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.905676 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 129024913 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 70885415 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 158884550 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 6176695 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 27558513 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26126183 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 76772 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 825683046 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 296199 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 27558513 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 135608190 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 9588825 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 46459719 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 158300780 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15014059 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 800754331 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1065 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3044118 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8771537 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 204 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 954467105 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3501224581 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3501223353 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1228 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 288214814 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2293021 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2293019 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 41499614 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 170286842 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 73502565 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 28542432 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 15757224 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 755181384 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3775400 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 665429696 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1394216 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 187494219 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 479993782 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 797768 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 392530086 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.695232 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.736006 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 145294997 35.89% 35.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 75803785 18.72% 54.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 69074812 17.06% 71.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53696610 13.26% 84.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 30882442 7.63% 92.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16155264 3.99% 96.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 9314791 2.30% 98.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3366855 0.83% 99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1274764 0.31% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 137153831 34.94% 34.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 69768231 17.77% 52.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 71497423 18.21% 70.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 53360624 13.59% 84.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31181551 7.94% 92.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16101363 4.10% 96.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8735003 2.23% 98.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2914770 0.74% 99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1817290 0.46% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 404864320 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 392530086 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 478550 4.99% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6548662 68.24% 73.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2569141 26.77% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 481185 5.01% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6545421 68.20% 73.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2570325 26.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 449957502 67.26% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 383513 0.06% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 114 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 154129801 23.04% 90.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 64533237 9.65% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 447832117 67.30% 67.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 383268 0.06% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 86 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 153411814 23.05% 90.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 63802408 9.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 669004170 # Type of FU issued
-system.cpu.iq.rate 1.623742 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9596353 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014344 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1753859495 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 950436200 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 649651296 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 358 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 665429696 # Type of FU issued
+system.cpu.iq.rate 1.664863 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9596931 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014422 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1734380418 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 947258082 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 646140584 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 274 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 678600390 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8560025 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 675026522 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 105 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8582869 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 44175415 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 40342 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 810510 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16577803 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 44257287 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 42197 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 811123 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 16642088 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19533 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4090 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 27544306 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 4979953 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 372702 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 763965600 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1116680 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 170948465 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 74181775 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2978814 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 218949 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11431 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 810510 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4004049 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8346983 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 659511571 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 150841037 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9492599 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 27558513 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 4987467 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 372691 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 760516980 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1117257 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 170286842 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 73502565 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2286858 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 219486 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11052 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 811123 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4340984 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4003792 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8344776 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 656001968 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 150122200 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9427728 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1559682 # number of nop insts executed
-system.cpu.iew.exec_refs 214084743 # number of memory reference insts executed
-system.cpu.iew.exec_branches 139192858 # Number of branches executed
-system.cpu.iew.exec_stores 63243706 # Number of stores executed
-system.cpu.iew.exec_rate 1.600703 # Inst execution rate
-system.cpu.iew.wb_sent 654626894 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 649651312 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 375421754 # num instructions producing a value
-system.cpu.iew.wb_consumers 646280118 # num instructions consuming a value
+system.cpu.iew.exec_nop 1560196 # number of nop insts executed
+system.cpu.iew.exec_refs 212633148 # number of memory reference insts executed
+system.cpu.iew.exec_branches 138504923 # Number of branches executed
+system.cpu.iew.exec_stores 62510948 # Number of stores executed
+system.cpu.iew.exec_rate 1.641276 # Inst execution rate
+system.cpu.iew.wb_sent 651119979 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 646140600 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 374813030 # num instructions producing a value
+system.cpu.iew.wb_consumers 646558310 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.576771 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.580896 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.616603 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.579705 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 189306245 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3721127 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7197604 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 377320014 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.523072 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.207570 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 189575186 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 7194795 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 364971573 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.564418 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.233675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 165631141 43.90% 43.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 102377769 27.13% 71.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 33965417 9.00% 80.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18834681 4.99% 85.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 16120892 4.27% 89.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7588494 2.01% 91.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6947007 1.84% 93.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3071988 0.81% 93.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22782625 6.04% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 157304822 43.10% 43.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 98491978 26.99% 70.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 33807803 9.26% 79.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 18748044 5.14% 84.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 16202992 4.44% 88.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7453577 2.04% 90.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6993904 1.92% 92.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3174450 0.87% 93.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22794003 6.25% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 377320014 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 510299082 # Number of instructions committed
-system.cpu.commit.committedOps 574685642 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 364971573 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 506581607 # Number of instructions committed
+system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 184377022 # Number of memory references committed
-system.cpu.commit.loads 126773050 # Number of loads committed
+system.cpu.commit.refs 182890032 # Number of memory references committed
+system.cpu.commit.loads 126029555 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
-system.cpu.commit.branches 122291796 # Number of branches committed
+system.cpu.commit.branches 121548301 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 473701673 # Number of committed integer instructions.
+system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22782625 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22794003 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1118522138 # The number of ROB reads
-system.cpu.rob.rob_writes 1555649058 # The number of ROB writes
-system.cpu.timesIdled 306506 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7149463 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 508955198 # Number of Instructions Simulated
-system.cpu.committedOps 573341758 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 508955198 # Number of Instructions Simulated
-system.cpu.cpi 0.809529 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.809529 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.235287 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.235287 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3078340491 # number of integer regfile reads
-system.cpu.int_regfile_writes 757780607 # number of integer regfile writes
+system.cpu.rob.rob_reads 1102713785 # The number of ROB reads
+system.cpu.rob.rob_writes 1548767048 # The number of ROB writes
+system.cpu.timesIdled 306858 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7160189 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 505237723 # Number of Instructions Simulated
+system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
+system.cpu.cpi 0.791093 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.791093 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.264073 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.264073 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3059184222 # number of integer regfile reads
+system.cpu.int_regfile_writes 752090779 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 213817535 # number of misc regfile reads
-system.cpu.misc_regfile_writes 4464074 # number of misc regfile writes
-system.cpu.icache.replacements 15034 # number of replacements
-system.cpu.icache.tagsinuse 1084.596639 # Cycle average of tags in use
-system.cpu.icache.total_refs 113043631 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 16888 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6693.725189 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 210880028 # number of misc regfile reads
+system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
+system.cpu.icache.replacements 15058 # number of replacements
+system.cpu.icache.tagsinuse 1101.681539 # Cycle average of tags in use
+system.cpu.icache.total_refs 114506253 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 16915 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 6769.509489 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1084.596639 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.529588 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.529588 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 113043631 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 113043631 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 113043631 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 113043631 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 113043631 # number of overall hits
-system.cpu.icache.overall_hits::total 113043631 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 21062 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 21062 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 21062 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 21062 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 21062 # number of overall misses
-system.cpu.icache.overall_misses::total 21062 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 460496000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 460496000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 460496000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 460496000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 460496000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 460496000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 113064693 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 113064693 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 113064693 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 113064693 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 113064693 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 113064693 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21863.830595 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21863.830595 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21863.830595 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21863.830595 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1088 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1101.681539 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.537930 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.537930 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 114506253 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 114506253 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 114506253 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 114506253 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 114506253 # number of overall hits
+system.cpu.icache.overall_hits::total 114506253 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 21101 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 21101 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 21101 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 21101 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 21101 # number of overall misses
+system.cpu.icache.overall_misses::total 21101 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 452371500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 452371500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 452371500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 452371500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 452371500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 452371500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 114527354 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 114527354 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 114527354 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 114527354 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 114527354 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 114527354 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21438.391545 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21438.391545 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21438.391545 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21438.391545 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 90.666667 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 35.700000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4099 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 4099 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 4099 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 4099 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 4099 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 4099 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 16963 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 16963 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 16963 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 16963 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 16963 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340828000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 340828000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340828000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 340828000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340828000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 340828000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20092.436479 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20092.436479 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4104 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 4104 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 4104 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 4104 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 4104 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 4104 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16997 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 16997 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 16997 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 16997 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 16997 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 16997 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339326500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 339326500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339326500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 339326500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339326500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 339326500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19963.905395 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19963.905395 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 115524 # number of replacements
-system.cpu.l2cache.tagsinuse 26913.844111 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1781016 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 146770 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 12.134741 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 106794042500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 22881.724629 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 362.646179 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 3669.473303 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.698295 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.011067 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.111983 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.821345 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 13496 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 804094 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 817590 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1110621 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1110621 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 66 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 66 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 247478 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 247478 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 13496 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1051572 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1065068 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 13496 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1051572 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1065068 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3384 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 43623 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 47007 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 101285 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 101285 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3384 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 144908 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 148292 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3384 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 144908 # number of overall misses
-system.cpu.l2cache.overall_misses::total 148292 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188319500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2550766500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 2739086000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5396872000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5396872000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 188319500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7947638500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8135958000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 188319500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7947638500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 8135958000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 16880 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 847717 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 864597 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1110621 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1110621 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 348763 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 348763 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 16880 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1196480 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1213360 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 16880 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1196480 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1213360 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200474 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051459 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.054369 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.120000 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.120000 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290412 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.290412 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200474 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.121112 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.122216 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200474 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.121112 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.122216 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55649.970449 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58472.972973 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 58269.747059 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53284.020339 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53284.020339 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55649.970449 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54846.098904 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 54864.443126 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55649.970449 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54846.098904 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 54864.443126 # average overall miss latency
+system.cpu.l2cache.replacements 115392 # number of replacements
+system.cpu.l2cache.tagsinuse 27104.061391 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1781385 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 146645 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 12.147601 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 100645092000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 23030.603679 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 365.807656 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 3707.650056 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.702838 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.011164 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.113149 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.827150 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 13507 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 804164 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 817671 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1110730 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1110730 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 70 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 70 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 247532 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 247532 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 13507 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1051696 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1065203 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 13507 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1051696 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1065203 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3394 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 43490 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 46884 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 101287 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 101287 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3394 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 144777 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 148171 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3394 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 144777 # number of overall misses
+system.cpu.l2cache.overall_misses::total 148171 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 186700000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2546099500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 2732799500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5401014000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5401014000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 186700000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7947113500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 8133813500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 186700000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7947113500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 8133813500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 16901 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 847654 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 864555 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1110730 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1110730 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 81 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 348819 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 348819 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 16901 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1196473 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1213374 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 16901 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1196473 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1213374 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200817 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051306 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.054229 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.135802 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.135802 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290371 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.290371 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200817 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.121003 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.122115 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200817 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.121003 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.122115 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55008.839128 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58544.481490 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 58288.531269 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53323.861897 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53323.861897 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55008.839128 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54892.099574 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54894.773606 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55008.839128 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54892.099574 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54894.773606 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 97660 # number of writebacks
-system.cpu.l2cache.writebacks::total 97660 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 97626 # number of writebacks
+system.cpu.l2cache.writebacks::total 97626 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 25 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 25 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3379 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43601 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 46980 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101285 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 101285 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3379 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 144886 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 148265 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3379 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 144886 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 148265 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 144900235 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1993232927 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2138133162 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4109014892 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4109014892 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144900235 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6102247819 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6247148054 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144900235 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6102247819 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6247148054 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051433 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054337 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.120000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.120000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290412 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290412 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121094 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.122194 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121094 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.122194 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42882.579165 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45715.303021 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45511.561558 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40568.839335 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40568.839335 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42882.579165 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42117.580850 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42135.015371 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42882.579165 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42117.580850 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42135.015371 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data 25 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3389 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43465 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 46854 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101287 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 101287 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3389 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 144752 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 148141 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3389 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 144752 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 148141 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143453810 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1990470119 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2133923929 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115510 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115510 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113084396 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113084396 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453810 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6103554515 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6247008325 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453810 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6103554515 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6247008325 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200521 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051277 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054194 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.135802 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.135802 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290371 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290371 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200521 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120982 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.122090 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200521 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120982 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.122090 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42329.244615 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45794.780145 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45544.114249 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10500.909091 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10500.909091 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.216217 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.216217 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42329.244615 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42165.597125 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42169.340864 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42329.244615 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42165.597125 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42169.340864 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1192383 # number of replacements
-system.cpu.dcache.tagsinuse 4054.755183 # Cycle average of tags in use
-system.cpu.dcache.total_refs 191684453 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1196479 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 160.207119 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4054.755183 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.989930 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.989930 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 136225611 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 136225611 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 50993519 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 50993519 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233068 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 2233068 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 2232036 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 2232036 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 187219130 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 187219130 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 187219130 # number of overall hits
-system.cpu.dcache.overall_hits::total 187219130 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1694816 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1694816 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3245787 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3245787 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 4940603 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4940603 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4940603 # number of overall misses
-system.cpu.dcache.overall_misses::total 4940603 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 25904626000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 25904626000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 58849421949 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 58849421949 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 574000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 574000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 84754047949 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 84754047949 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 84754047949 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 84754047949 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 137920427 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 137920427 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements 1192376 # number of replacements
+system.cpu.dcache.tagsinuse 4058.257289 # Cycle average of tags in use
+system.cpu.dcache.total_refs 190193687 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1196472 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 158.962088 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 4128824000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4058.257289 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.990785 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.990785 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 136223717 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 136223717 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 50992367 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 50992367 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488803 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 1488803 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 187216084 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 187216084 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 187216084 # number of overall hits
+system.cpu.dcache.overall_hits::total 187216084 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1697690 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1697690 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3246939 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3246939 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 4944629 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4944629 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4944629 # number of overall misses
+system.cpu.dcache.overall_misses::total 4944629 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 26054770000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 26054770000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 58807860452 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 58807860452 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 537000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 537000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 84862630452 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 84862630452 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 84862630452 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 84862630452 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 137921407 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 137921407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233106 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 2233106 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232036 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 2232036 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 192159733 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 192159733 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 192159733 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 192159733 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012288 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012288 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059842 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.059842 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000017 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000017 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025711 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025711 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025711 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025711 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15284.624408 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15284.624408 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18131.017824 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 18131.017824 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15105.263158 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15105.263158 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17154.595896 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17154.595896 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 17486 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 15854 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1635 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 605 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.694801 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 26.204959 # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488838 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1488838 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 192160713 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 192160713 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 192160713 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 192160713 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012309 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012309 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059863 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.059863 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025732 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025732 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025732 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025732 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15347.189416 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15347.189416 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18111.784808 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 18111.784808 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15342.857143 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15342.857143 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17162.588023 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17162.588023 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 16266 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 14829 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1654 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 595 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.834341 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 24.922689 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1110621 # number of writebacks
-system.cpu.dcache.writebacks::total 1110621 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 846554 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 846554 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2897494 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2897494 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3744048 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3744048 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3744048 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3744048 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848262 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 848262 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348293 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348293 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1196555 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1196555 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1196555 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1196555 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11478175000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 11478175000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269727997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269727997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19747902997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 19747902997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19747902997 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 19747902997 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 1110730 # number of writebacks
+system.cpu.dcache.writebacks::total 1110730 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 849485 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 849485 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898590 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2898590 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3748075 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3748075 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3748075 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3748075 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848205 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 848205 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348349 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 348349 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1196554 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1196554 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1196554 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1196554 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11474356500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 11474356500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8274514996 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8274514996 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19748871496 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 19748871496 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19748871496 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 19748871496 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13531.403033 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13531.403033 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23743.595183 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23743.595183 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13527.810494 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13527.810494 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23753.520165 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23753.520165 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.068267 # Number of seconds simulated
-sim_ticks 68267465500 # Number of ticks simulated
-final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.068072 # Number of seconds simulated
+sim_ticks 68071881000 # Number of ticks simulated
+final_tick 68071881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 47859 # Simulator instruction rate (inst/s)
-host_op_rate 61184 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11965597 # Simulator tick rate (ticks/s)
-host_mem_usage 240720 # Number of bytes of host memory used
-host_seconds 5705.31 # Real time elapsed on the host
-sim_insts 273048375 # Number of instructions simulated
-sim_ops 349076099 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 273088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 467008 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4267 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7297 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2840592 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4000266 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6840857 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2840592 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2840592 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2840592 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4000266 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6840857 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7297 # Total number of read requests seen
+host_inst_rate 138205 # Simulator instruction rate (inst/s)
+host_op_rate 176689 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34456552 # Simulator tick rate (ticks/s)
+host_mem_usage 251760 # Number of bytes of host memory used
+host_seconds 1975.59 # Real time elapsed on the host
+sim_insts 273036725 # Number of instructions simulated
+sim_ops 349064449 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory
+system.physmem.bytes_read::total 466240 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2846873 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4002357 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6849230 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2846873 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2846873 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2846873 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4002357 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6849230 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7286 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 7297 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 467008 # Total number of bytes read from memory
+system.physmem.cpureqs 7288 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 466240 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 467008 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 466240 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 514 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 581 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 457 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 577 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 474 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 505 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 483 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 495 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 504 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 481 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 558 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 359 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 557 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 360 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 68267283000 # Total gap between requests
+system.physmem.totGap 68071860500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 7297 # Categorize read packet sizes
+system.physmem.readPktSize::6 7286 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 2 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 4347 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2135 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 568 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 183 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4339 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2127 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 36802775 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 167840775 # Sum of mem lat for all requests
-system.physmem.totBusLat 29188000 # Total cycles spent in databus access
-system.physmem.totBankLat 101850000 # Total cycles spent in bank access
-system.physmem.avgQLat 5043.55 # Average queueing delay per request
-system.physmem.avgBankLat 13957.79 # Average bank access latency per request
+system.physmem.totQLat 38841760 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 170087760 # Sum of mem lat for all requests
+system.physmem.totBusLat 29144000 # Total cycles spent in databus access
+system.physmem.totBankLat 102102000 # Total cycles spent in bank access
+system.physmem.avgQLat 5331.01 # Average queueing delay per request
+system.physmem.avgBankLat 14013.45 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 23001.34 # Average memory access latency
-system.physmem.avgRdBW 6.84 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 23344.46 # Average memory access latency
+system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 6.84 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 6392 # Number of row buffer hits during reads
+system.physmem.readRowHits 6372 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 87.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 9355527.34 # Average gap between requests
+system.physmem.avgGap 9342830.15 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 136534932 # number of cpu cycles simulated
+system.cpu.numCycles 136143763 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 41739250 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 21065104 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1640413 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 26027262 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 16735646 # Number of BTB hits
+system.cpu.BPredUnit.lookups 41692065 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 21046025 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1612310 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 25558633 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 16675018 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 38860072 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 21559517 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 37487913 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 519565 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 136324281 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 6736046 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 7190 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 38720751 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 316654874 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 41692065 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 23411064 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 70618145 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6665842 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 21550456 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1364 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 37376595 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 521732 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 135933121 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.990728 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.456678 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 66156808 48.53% 48.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4881557 3.58% 65.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4156543 3.05% 68.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3204825 2.35% 71.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4146681 3.04% 74.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 65940392 48.51% 48.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 6730475 4.95% 53.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5637804 4.15% 57.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 5998950 4.41% 62.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4879102 3.59% 65.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4141679 3.05% 68.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3188425 2.35% 71.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4149669 3.05% 74.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 35266625 25.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 136324281 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16729556 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7269016 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 69099 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 401164000 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 213330 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 5039795 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 63595532 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 393365758 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 431881387 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2329985497 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1257436080 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 47296554 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 103432229 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 91356063 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4280154 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5359345 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 383896453 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 25411 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 373948163 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1224653 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 136324281 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 135933121 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.306236 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.325886 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 45271721 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 16691056 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 66469199 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 2527476 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4973669 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 7265289 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 69057 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 400237870 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 218381 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4973669 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 50782794 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1926905 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 308736 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 63418534 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 14522483 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 392567341 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 52 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1667501 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 10227766 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1022 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 431145358 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2325492453 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1253893551 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1071598902 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 46579165 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 11899 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 11898 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 36419091 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 103284417 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 91190896 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4278404 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5313371 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 383399978 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22859 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 373603209 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1225399 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 33612220 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 83720105 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 135933121 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.748434 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.022451 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24852307 18.23% 18.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 23977307 17.59% 78.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15767707 11.57% 90.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8831817 6.48% 96.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3361471 2.47% 99.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24617806 18.11% 18.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 19905628 14.64% 32.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 20463769 15.05% 47.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18134866 13.34% 61.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 23975475 17.64% 78.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15748338 11.59% 90.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8799560 6.47% 96.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3376937 2.48% 99.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 910742 0.67% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 136324281 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 135933121 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9041 0.05% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 46185 0.26% 0.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 46127 0.26% 0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 7671 0.04% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 470 0.00% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 190051 1.07% 1.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 6041 0.03% 1.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 241741 1.36% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9330966 52.43% 55.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 7960919 44.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 7573 0.04% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 401 0.00% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 189986 1.07% 1.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 6027 0.03% 1.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 241589 1.36% 2.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9303270 52.42% 55.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 7940124 44.74% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 126153074 33.74% 33.74% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2174128 0.58% 34.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 126062452 33.74% 33.74% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2174186 0.58% 34.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6786226 1.81% 36.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8470375 2.27% 38.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3426412 0.92% 39.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1600673 0.43% 39.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 20911148 5.59% 45.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7171927 1.92% 47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134560 1.91% 49.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 101505429 27.14% 76.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 88438925 23.65% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6778330 1.81% 36.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8468082 2.27% 38.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3426363 0.92% 39.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1600385 0.43% 39.75% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20905129 5.60% 45.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7170133 1.92% 47.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133112 1.91% 49.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 101416985 27.15% 76.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 88292763 23.63% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 373948163 # Type of FU issued
-system.cpu.iq.rate 2.738846 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 653530497 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 130436942 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 118161488 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 262975786 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 128770067 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 11107823 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 373603209 # Type of FU issued
+system.cpu.iq.rate 2.744182 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 17748829 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.047507 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 652552700 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 286781782 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 249670215 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 249561067 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 130267469 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 118091463 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 262665125 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 128686913 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 11143467 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 8781151 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 113920 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14326 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 8978150 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 8635669 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 113833 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14304 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 8815313 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 176383 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1158 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 179767 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1150 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5039795 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 951526 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 345 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 384 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14326 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1283309 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 356464 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1639773 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 370071311 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 100289689 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3876852 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4973669 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 290169 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 43007 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 383424336 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 947805 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 103284417 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 91190896 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 11825 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 324 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 376 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14304 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1257323 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 355165 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1612488 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 369752091 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 100205261 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3851118 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1594 # number of nop insts executed
-system.cpu.iew.exec_refs 187642898 # number of memory reference insts executed
-system.cpu.iew.exec_branches 38279004 # Number of branches executed
-system.cpu.iew.exec_stores 87353209 # Number of stores executed
-system.cpu.iew.exec_rate 2.710451 # Inst execution rate
-system.cpu.iew.wb_sent 368702519 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 368038571 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 182991065 # num instructions producing a value
-system.cpu.iew.wb_consumers 363891400 # num instructions consuming a value
+system.cpu.iew.exec_nop 1499 # number of nop insts executed
+system.cpu.iew.exec_refs 187415465 # number of memory reference insts executed
+system.cpu.iew.exec_branches 38269539 # Number of branches executed
+system.cpu.iew.exec_stores 87210204 # Number of stores executed
+system.cpu.iew.exec_rate 2.715894 # Inst execution rate
+system.cpu.iew.wb_sent 368418252 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 367761678 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 182872307 # num instructions producing a value
+system.cpu.iew.wb_consumers 363527613 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.695563 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.502873 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.701275 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.503049 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 34846819 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 24450 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1571698 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 131284486 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.658933 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.660928 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 34359338 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1543637 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 130959452 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.665444 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.660816 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 34526115 26.30% 26.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 28464962 21.68% 47.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13313072 10.14% 58.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11375196 8.66% 66.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 13798040 10.51% 77.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7398451 5.64% 82.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3831320 2.92% 85.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3930958 2.99% 88.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 14646372 11.16% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 34245793 26.15% 26.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 28403736 21.69% 47.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13297993 10.15% 57.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11400251 8.71% 66.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 13789663 10.53% 77.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7417902 5.66% 82.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 3851196 2.94% 85.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3914096 2.99% 88.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 14638822 11.18% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 131284486 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 273048987 # Number of instructions committed
-system.cpu.commit.committedOps 349076711 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 130959452 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 273037337 # Number of instructions committed
+system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 177028991 # Number of memory references committed
-system.cpu.commit.loads 94651078 # Number of loads committed
+system.cpu.commit.refs 177024331 # Number of memory references committed
+system.cpu.commit.loads 94648748 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
-system.cpu.commit.branches 36549040 # Number of branches committed
+system.cpu.commit.branches 36546710 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 279593931 # Number of committed integer instructions.
+system.cpu.commit.int_insts 279584611 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 14646372 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 14638822 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 500559121 # The number of ROB reads
-system.cpu.rob.rob_writes 772890927 # The number of ROB writes
-system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 210651 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 273048375 # Number of Instructions Simulated
-system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated
-system.cpu.cpi 0.500039 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.500039 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.999843 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.999843 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1769305779 # number of integer regfile reads
-system.cpu.int_regfile_writes 232713829 # number of integer regfile writes
-system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads
-system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes
-system.cpu.misc_regfile_reads 567370356 # number of misc regfile reads
-system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes
-system.cpu.icache.replacements 13908 # number of replacements
-system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use
-system.cpu.icache.total_refs 37470862 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 15795 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2372.324280 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 499742506 # The number of ROB reads
+system.cpu.rob.rob_writes 771826211 # The number of ROB writes
+system.cpu.timesIdled 6299 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 210642 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 273036725 # Number of Instructions Simulated
+system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated
+system.cpu.cpi 0.498628 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.498628 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.005503 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.005503 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1767787991 # number of integer regfile reads
+system.cpu.int_regfile_writes 232574551 # number of integer regfile writes
+system.cpu.fp_regfile_reads 188239368 # number of floating regfile reads
+system.cpu.fp_regfile_writes 132566541 # number of floating regfile writes
+system.cpu.misc_regfile_reads 566998882 # number of misc regfile reads
+system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
+system.cpu.icache.replacements 13918 # number of replacements
+system.cpu.icache.tagsinuse 1846.260886 # Cycle average of tags in use
+system.cpu.icache.total_refs 37359528 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 15804 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 2363.928626 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1849.811927 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.903228 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.903228 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 37470862 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 37470862 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 37470862 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits
-system.cpu.icache.overall_hits::total 37470862 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 17050 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 17050 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 17050 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 17050 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 17050 # number of overall misses
-system.cpu.icache.overall_misses::total 17050 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 356620497 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 356620497 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 356620497 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 356620497 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 356620497 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 356620497 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 37487912 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 37487912 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 37487912 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 37487912 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 37487912 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 37487912 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20916.158182 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20916.158182 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20916.158182 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20916.158182 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20916.158182 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1846.260886 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.901495 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.901495 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 37359528 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 37359528 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 37359528 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 37359528 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 37359528 # number of overall hits
+system.cpu.icache.overall_hits::total 37359528 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 17066 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 17066 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 17066 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 17066 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 17066 # number of overall misses
+system.cpu.icache.overall_misses::total 17066 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 359194498 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 359194498 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 359194498 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 359194498 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 359194498 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 359194498 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 37376594 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 37376594 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 37376594 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 37376594 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 37376594 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 37376594 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21047.374780 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21047.374780 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21047.374780 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21047.374780 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 550 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 28.947368 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1255 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1255 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1255 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1255 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1255 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1255 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15795 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 15795 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 15795 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 15795 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 15795 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 15795 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 291702997 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 291702997 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 291702997 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 291702997 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 291702997 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 291702997 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18468.059323 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18468.059323 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18468.059323 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18468.059323 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1259 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1259 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1259 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1259 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1259 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1259 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15807 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 15807 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 15807 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 15807 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 15807 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 15807 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293030998 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 293030998 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293030998 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 293030998 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293030998 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 293030998 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000423 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18538.052635 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18538.052635 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 3959.582108 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 13162 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 5412 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.432003 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3947.622015 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 13172 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.440163 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 367.644751 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2774.541575 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 817.395782 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.011220 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.084672 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.024945 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.120837 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 12753 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 13052 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1040 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1040 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 12753 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 317 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 13070 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 12753 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 317 # number of overall hits
-system.cpu.l2cache.overall_hits::total 13070 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3042 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1512 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 4554 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 2795 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 2795 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3042 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 4307 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 7349 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3042 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 4307 # number of overall misses
-system.cpu.l2cache.overall_misses::total 7349 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 148332000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 74802000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 223134000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128955500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 128955500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 148332000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 203757500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 352089500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 148332000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 203757500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 352089500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 15795 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1811 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 17606 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1040 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1040 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 2813 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 2813 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 15795 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 4624 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 20419 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 15795 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 4624 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 20419 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192593 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834898 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.258662 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993601 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.993601 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192593 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.931445 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.359910 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192593 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.931445 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.359910 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48761.341223 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49472.222222 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 48997.364954 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46137.924866 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46137.924866 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 47909.851681 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48761.341223 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47308.451358 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 47909.851681 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 367.078870 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2774.586146 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 805.956999 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.011202 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.084674 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.024596 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.120472 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 12765 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 296 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 13061 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1039 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1039 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 12765 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 313 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 13078 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 12765 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 313 # number of overall hits
+system.cpu.l2cache.overall_hits::total 13078 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3040 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1500 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 4540 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 2797 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 2797 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3040 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 4297 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 7337 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3040 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 4297 # number of overall misses
+system.cpu.l2cache.overall_misses::total 7337 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149534000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 75407000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 224941000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 129040500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 129040500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 149534000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 204447500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 353981500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 149534000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 204447500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 353981500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 15805 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1796 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 17601 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1039 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1039 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2814 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 2814 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 15805 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4610 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 20415 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 15805 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4610 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 20415 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192344 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835189 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.257940 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993959 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.993959 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192344 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.932104 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.359393 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192344 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.932104 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.359393 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49188.815789 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50271.333333 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 49546.475771 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46135.323561 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46135.323561 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49188.815789 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47579.124971 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 48246.081505 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49188.815789 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47579.124971 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 48246.081505 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3030 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1472 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 4502 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2795 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 2795 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3030 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 4267 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7297 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3030 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 4267 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7297 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109506099 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54676221 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164182320 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94308882 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94308882 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109506099 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148985103 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 258491202 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109506099 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148985103 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 258491202 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812811 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255708 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993601 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993601 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922794 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.357363 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191833 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922794 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.357363 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36140.626733 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37144.171875 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36468.751666 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33741.997138 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33741.997138 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36140.626733 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36140.626733 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34915.655730 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35424.311635 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1460 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4489 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2797 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 2797 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 4257 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7286 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4257 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7286 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110751088 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55451199 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 166202287 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94361392 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94361392 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110751088 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149812591 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 260563679 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110751088 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149812591 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 260563679 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812918 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255042 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993959 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993959 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.356894 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.356894 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36563.581380 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37980.273288 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37024.345511 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33736.643547 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33736.643547 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1414 # number of replacements
-system.cpu.dcache.tagsinuse 3122.405384 # Cycle average of tags in use
-system.cpu.dcache.total_refs 170873491 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4624 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 36953.609645 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 1413 # number of replacements
+system.cpu.dcache.tagsinuse 3109.588822 # Cycle average of tags in use
+system.cpu.dcache.total_refs 170749767 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37038.995011 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3122.405384 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.762306 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.762306 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 88815229 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 88815229 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82031562 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82031562 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 13475 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 13475 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 13225 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 13225 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 170846791 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 170846791 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 170846791 # number of overall hits
-system.cpu.dcache.overall_hits::total 170846791 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 4046 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 4046 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 21103 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 21103 # number of WriteReq misses
+system.cpu.dcache.occ_blocks::cpu.data 3109.588822 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.759177 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.759177 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 88696383 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 88696383 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 82031533 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 82031533 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 170727916 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 170727916 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 170727916 # number of overall hits
+system.cpu.dcache.overall_hits::total 170727916 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 4041 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 4041 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 21132 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 21132 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 25149 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 25149 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 25149 # number of overall misses
-system.cpu.dcache.overall_misses::total 25149 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 164690500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 164690500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 831954164 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 831954164 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 25173 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 25173 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 25173 # number of overall misses
+system.cpu.dcache.overall_misses::total 25173 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 164980000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 164980000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 832721164 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 832721164 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 996644664 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 996644664 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 996644664 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 996644664 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 997701164 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 997701164 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 997701164 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 997701164 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 88700424 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 88700424 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 13477 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 13225 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 13225 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 170871940 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 170871940 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 170871940 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 170871940 # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 170753089 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 170753089 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 170753089 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 170753089 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000183 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.522986 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.522986 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40826.528087 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40826.528087 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39405.695817 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39405.695817 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39629.594179 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.594179 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39629.594179 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39633.780797 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39633.780797 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 13427 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 430 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.225581 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
-system.cpu.dcache.writebacks::total 1040 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks
+system.cpu.dcache.writebacks::total 1039 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2244 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2244 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18317 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 18317 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211724000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 211724000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211724000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 211724000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 20561 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 20561 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 20561 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 20561 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1797 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1797 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2815 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2815 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80314500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 80314500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 132089500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 132089500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212404000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 212404000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212404000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 212404000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.280353 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.280353 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46929.765292 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46929.765292 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45788.062284 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45788.062284 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44693.656093 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44693.656093 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46923.445826 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46923.445826 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.624868 # Number of seconds simulated
-sim_ticks 624867585500 # Number of ticks simulated
-final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.625047 # Number of seconds simulated
+sim_ticks 625047295000 # Number of ticks simulated
+final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53257 # Simulator instruction rate (inst/s)
-host_op_rate 72528 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24038469 # Simulator tick rate (ticks/s)
-host_mem_usage 255596 # Number of bytes of host memory used
-host_seconds 25994.48 # Real time elapsed on the host
-sim_insts 1384379060 # Number of instructions simulated
-sim_ops 1885333812 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30242752 # Number of bytes read from this memory
+host_inst_rate 94484 # Simulator instruction rate (inst/s)
+host_op_rate 128674 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42659692 # Simulator tick rate (ticks/s)
+host_mem_usage 264788 # Number of bytes of host memory used
+host_seconds 14651.94 # Real time elapsed on the host
+sim_insts 1384370590 # Number of instructions simulated
+sim_ops 1885325342 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory
system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 155584 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 155584 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 155456 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 155456 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2431 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 472543 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2429 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory
system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 248987 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48398657 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48647644 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 248987 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 248987 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6769869 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6769869 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6769869 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 248987 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48398657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55417514 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 248711 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 48384947 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 48633657 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 248711 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 248711 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6767923 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6767923 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6767923 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 248711 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 48384947 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 55401580 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 474974 # Total number of read requests seen
system.physmem.writeReqs 66098 # Total number of write requests seen
-system.physmem.cpureqs 545402 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 545412 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 30398336 # Total number of bytes read from memory
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4330 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29668 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29687 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29628 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29545 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29653 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29623 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29618 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29734 # Track reads on a per bank basis
+system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4340 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 29671 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29693 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 29543 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29652 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 29628 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 29613 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 29731 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29769 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 29790 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29857 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29669 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29606 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29627 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29610 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 29771 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 29793 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29658 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29603 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 29624 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 29606 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 624867514500 # Total gap between requests
+system.physmem.totGap 625047219500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4330 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4340 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 407769 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66657 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 297 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 407751 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66647 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 302 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests
-system.physmem.totBusLat 1899312000 # Total cycles spent in databus access
-system.physmem.totBankLat 12874638000 # Total cycles spent in bank access
-system.physmem.avgQLat 6984.13 # Average queueing delay per request
-system.physmem.avgBankLat 27114.32 # Average bank access latency per request
+system.physmem.totQLat 3340611483 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 18115671483 # Sum of mem lat for all requests
+system.physmem.totBusLat 1899232000 # Total cycles spent in databus access
+system.physmem.totBankLat 12875828000 # Total cycles spent in bank access
+system.physmem.avgQLat 7035.71 # Average queueing delay per request
+system.physmem.avgBankLat 27117.97 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 38098.44 # Average memory access latency
-system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 38153.68 # Average memory access latency
+system.physmem.avgRdBW 48.63 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 48.63 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.35 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 17.43 # Average write queue length over time
-system.physmem.readRowHits 249202 # Number of row buffer hits during reads
-system.physmem.writeRowHits 48033 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads
+system.physmem.avgWrQLen 17.44 # Average write queue length over time
+system.physmem.readRowHits 249146 # Number of row buffer hits during reads
+system.physmem.writeRowHits 48036 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes
-system.physmem.avgGap 1154869.43 # Average gap between requests
+system.physmem.avgGap 1155201.56 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1249735172 # number of cpu cycles simulated
+system.cpu.numCycles 1250094591 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 439117025 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 350578524 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 30630316 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 248764319 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 227490785 # Number of BTB hits
+system.cpu.BPredUnit.lookups 438808047 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 349805436 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 30625316 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 249957064 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 227370417 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 52357585 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 2806128 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 279728002 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 600743262 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 158308312 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 133148695 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 11515 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 333206369 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10414827 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1215386936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.589820 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.189306 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 72457573 5.96% 72.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 42599927 3.51% 75.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31039765 2.55% 78.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 31697654 2.61% 81.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 614688205 50.58% 50.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42445352 3.49% 54.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 95116159 7.83% 61.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55675580 4.58% 66.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 72776602 5.99% 72.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 42276531 3.48% 75.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31131234 2.56% 78.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 31565180 2.60% 81.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 229712093 18.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 44615078 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3041090435 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 27022 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 127217578 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 972715984 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 490205592 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36288460 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 40771047 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2804297042 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 31006 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2436370950 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13311855 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 1215386936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.351020 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.829826 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 402796361 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 106301870 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 561862491 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 16807396 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 127618818 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 44638184 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12819 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3046676123 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 27895 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 127618818 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 438124604 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 35349497 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 425259 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 541326873 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 72541885 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2975830632 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4806802 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 56918075 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2945274289 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14167459331 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13596684512 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 570774819 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 952134199 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 23805 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 21281 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 197120926 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 972834043 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 492760757 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 36385181 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 42690468 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2809386355 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 28039 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2437787250 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 13304140 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 911537771 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2374413817 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 6655 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1215386936 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.005770 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.875210 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 132635579 10.92% 87.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 93723777 7.71% 95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 37883178 3.12% 98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12361449 1.02% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 379434397 31.22% 31.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 183109361 15.07% 46.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 202931100 16.70% 62.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 170113731 14.00% 76.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 132526126 10.90% 87.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 93839529 7.72% 95.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 37911750 3.12% 98.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12465689 1.03% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 3055253 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1215386936 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 714674 0.82% 0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 24388 0.03% 0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 55143304 62.90% 63.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 31782308 36.25% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 55116913 62.89% 63.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 31779800 36.26% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1107294192 45.45% 45.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11224034 0.46% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5502357 0.23% 46.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23404551 0.96% 47.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 838357967 34.41% 81.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 442336083 18.16% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1108876695 45.49% 45.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11224297 0.46% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5502220 0.23% 46.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23416324 0.96% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 838276108 34.39% 81.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 442239839 18.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2436370950 # Type of FU issued
-system.cpu.iq.rate 1.949510 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 82717236 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56437909 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2460715459 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63320089 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 84361835 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2437787250 # Type of FU issued
+system.cpu.iq.rate 1.950082 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 87635775 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.035949 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6069393440 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3638225906 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2254362609 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 122507911 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 82793715 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 56449336 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2462106345 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 63316680 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 84343916 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 341327109 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8250 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1428808 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 213208601 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 341446862 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7743 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1429272 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 215765460 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 221 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 127217578 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1558593 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2526 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1428808 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 32521161 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1512713 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 34033874 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2362219907 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 792646926 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 74151043 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 127618818 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 13752826 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1562574 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2809426795 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1398231 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 972834043 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 492760757 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 18053 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1558945 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 1429272 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 32529008 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1513965 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 34042973 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2363631235 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 792642751 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 74156015 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12429 # number of nop insts executed
-system.cpu.iew.exec_refs 1216288233 # number of memory reference insts executed
-system.cpu.iew.exec_branches 322226431 # Number of branches executed
-system.cpu.iew.exec_stores 423641307 # Number of stores executed
-system.cpu.iew.exec_rate 1.890176 # Inst execution rate
-system.cpu.iew.wb_sent 2335115057 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2309436326 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1347701281 # num instructions producing a value
-system.cpu.iew.wb_consumers 2523709653 # num instructions consuming a value
+system.cpu.iew.exec_nop 12401 # number of nop insts executed
+system.cpu.iew.exec_refs 1216279993 # number of memory reference insts executed
+system.cpu.iew.exec_branches 322475744 # Number of branches executed
+system.cpu.iew.exec_stores 423637242 # Number of stores executed
+system.cpu.iew.exec_rate 1.890762 # Inst execution rate
+system.cpu.iew.wb_sent 2336496726 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2310811945 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1347866502 # num instructions producing a value
+system.cpu.iew.wb_consumers 2524860722 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.847941 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.534016 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.848510 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.533838 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 918995782 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 23078 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 30617997 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1087855788 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.733083 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.398277 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 924090552 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 30613261 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1087768118 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.733215 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.398367 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 447553397 41.14% 41.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 288592120 26.53% 67.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 95115403 8.74% 76.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 70228058 6.46% 82.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 46464545 4.27% 87.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22184894 2.04% 89.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15849617 1.46% 90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10984656 1.01% 91.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 90883098 8.35% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 447474994 41.14% 41.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 288616071 26.53% 67.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 95091930 8.74% 76.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 70192926 6.45% 82.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 46475898 4.27% 87.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22197093 2.04% 89.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 15849951 1.46% 90.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10985154 1.01% 91.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 90884101 8.36% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1087855788 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1384390076 # Number of instructions committed
-system.cpu.commit.committedOps 1885344828 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 1087768118 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
+system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 908385866 # Number of memory references committed
-system.cpu.commit.loads 631388875 # Number of loads committed
+system.cpu.commit.refs 908382478 # Number of memory references committed
+system.cpu.commit.loads 631387181 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
-system.cpu.commit.branches 299636089 # Number of branches committed
+system.cpu.commit.branches 299634395 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1653705643 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 90883098 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 90884101 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3801294955 # The number of ROB reads
-system.cpu.rob.rob_writes 5735909866 # The number of ROB writes
-system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1384379060 # Number of Instructions Simulated
-system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated
-system.cpu.cpi 0.902741 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.902741 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.107738 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.107738 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11770471325 # number of integer regfile reads
-system.cpu.int_regfile_writes 2224868034 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68796296 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49549961 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1363964167 # number of misc regfile reads
-system.cpu.misc_regfile_writes 13776290 # number of misc regfile writes
-system.cpu.icache.replacements 22546 # number of replacements
-system.cpu.icache.tagsinuse 1642.542137 # Cycle average of tags in use
-system.cpu.icache.total_refs 333790581 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 24232 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 13774.784624 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 3806292582 # The number of ROB reads
+system.cpu.rob.rob_writes 5746483501 # The number of ROB writes
+system.cpu.timesIdled 353075 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 34707655 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
+system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
+system.cpu.cpi 0.903006 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.903006 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.107413 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.107413 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 11775193288 # number of integer regfile reads
+system.cpu.int_regfile_writes 2227107160 # number of integer regfile writes
+system.cpu.fp_regfile_reads 68795849 # number of floating regfile reads
+system.cpu.fp_regfile_writes 49561296 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1363965830 # number of misc regfile reads
+system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
+system.cpu.icache.replacements 22468 # number of replacements
+system.cpu.icache.tagsinuse 1641.255803 # Cycle average of tags in use
+system.cpu.icache.total_refs 333171598 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 24150 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 13795.925383 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1642.542137 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.802023 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.802023 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 333794637 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 333794637 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 333794637 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits
-system.cpu.icache.overall_hits::total 333794637 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses
-system.cpu.icache.overall_misses::total 30837 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 1641.255803 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.801394 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.801394 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 333175666 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 333175666 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 333175666 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 333175666 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 333175666 # number of overall hits
+system.cpu.icache.overall_hits::total 333175666 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 30702 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 30702 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 30702 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 30702 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 30702 # number of overall misses
+system.cpu.icache.overall_misses::total 30702 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 468488500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 468488500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 468488500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 468488500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 468488500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 468488500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 333206368 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 333206368 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 333206368 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 333206368 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 333206368 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 333206368 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15233.615397 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15233.615397 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15233.615397 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15233.615397 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15233.615397 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15259.217641 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15259.217641 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15259.217641 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15259.217641 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1109 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 34.793103 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 39.607143 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2273 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2273 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2273 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2273 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2273 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2273 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28564 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 28564 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 379116998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 379116998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 379116998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 379116998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 379116998 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 379116998 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2210 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2210 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2210 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2210 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2210 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2210 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28492 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 28492 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 28492 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 28492 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 28492 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 28492 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 377164000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 377164000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 377164000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 377164000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 377164000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 377164000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.545792 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.545792 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.545792 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.545792 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13237.540362 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13237.540362 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13237.540362 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13237.540362 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13237.540362 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13237.540362 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 442193 # number of replacements
-system.cpu.l2cache.tagsinuse 32688.524201 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1109720 # Total number of references to valid blocks.
+system.cpu.l2cache.replacements 442192 # number of replacements
+system.cpu.l2cache.tagsinuse 32688.738823 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1109575 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.336548 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.336242 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 1294.928331 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 48.758922 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 31344.836948 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.039518 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.956569 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.997575 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 21799 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1058077 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1079876 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 96322 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 96322 # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks 1295.493946 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 49.994068 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 31343.250808 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.039535 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001526 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.956520 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.997581 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 21719 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1058021 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1079740 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 96308 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 96308 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 21799 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1064518 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1086317 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 21799 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1064518 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1086317 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 2433 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 408924 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 4330 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 4330 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 66074 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 66074 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2433 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 472565 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2433 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 472565 # number of overall misses
-system.cpu.l2cache.overall_misses::total 474998 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 128013500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25837931500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 25965945000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3242869000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 3242869000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 128013500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 29080800500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 29208814000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 128013500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 29080800500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 29208814000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 24232 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1464568 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1488800 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 96322 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 96322 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4333 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 4333 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 72515 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 72515 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 24232 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1537083 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1561315 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 24232 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1537083 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1561315 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100404 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277550 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.274667 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999308 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999308 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911177 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.911177 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100404 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.307443 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.304229 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100404 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.307443 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.304229 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.495273 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.354416 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 63498.217273 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.350425 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.350425 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 61492.498916 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.495273 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61538.202152 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 61492.498916 # average overall miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.data 6442 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 6442 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 21719 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1064463 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1086182 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 21719 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1064463 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1086182 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2431 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 406497 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 408928 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 4340 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 4340 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2431 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 472572 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 475003 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2431 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 472572 # number of overall misses
+system.cpu.l2cache.overall_misses::total 475003 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 126924500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25862108500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 25989033000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3246043000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3246043000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 126924500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 29108151500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 29235076000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 126924500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 29108151500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 29235076000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 24150 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1464518 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1488668 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 96308 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 96308 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4343 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 4343 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 24150 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1537035 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1561185 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 24150 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1537035 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1561185 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100663 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277564 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.274694 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999309 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999309 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911166 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.911166 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100663 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.307457 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.304258 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100663 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.307457 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.304258 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52210.818593 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63621.892658 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 63554.055971 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49126.643965 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49126.643965 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52210.818593 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61595.167509 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 61547.139702 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52210.818593 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61595.167509 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 61547.139702 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2431 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406469 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 408900 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4330 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 4330 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66074 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 66074 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2431 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 472543 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2429 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 408899 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4340 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 4340 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2429 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 474974 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2431 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 472543 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2429 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97294812 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693797350 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791092162 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43304330 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43304330 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390498504 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390498504 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97294812 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084295854 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 23181590666 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97294812 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084295854 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 23181590666 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277535 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999308 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999308 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911177 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911177 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.304214 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.304214 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.133075 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.398048 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96251295 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20717048717 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20813300012 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43404340 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43404340 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2393684509 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2393684509 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96251295 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23110733226 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23206984521 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96251295 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23110733226 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23206984521 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277545 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274674 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999309 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999309 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.304239 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.304239 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39625.893372 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50968.210980 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50900.833732 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36226.780310 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36226.780310 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1532987 # number of replacements
-system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
-system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 693885026 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 276101075 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 276101075 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 11981 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 11679 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 11679 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 969986101 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 969986101 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 969986101 # number of overall hits
-system.cpu.dcache.overall_hits::total 969986101 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1953380 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1953380 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 834603 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 834603 # number of WriteReq misses
+system.cpu.dcache.replacements 1532939 # number of replacements
+system.cpu.dcache.tagsinuse 4094.623683 # Cycle average of tags in use
+system.cpu.dcache.total_refs 970042937 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1537035 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 631.113109 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 332181000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.623683 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999664 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 693909081 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 693909081 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276100966 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276100966 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 970010047 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 970010047 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 970010047 # number of overall hits
+system.cpu.dcache.overall_hits::total 970010047 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1953320 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1953320 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 834712 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 834712 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2787983 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2787983 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2787983 # number of overall misses
-system.cpu.dcache.overall_misses::total 2787983 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 67369162000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 67369162000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 39954940470 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 39954940470 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 199000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 107324102470 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 107324102470 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 107324102470 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 107324102470 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 695838406 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 695838406 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 2788032 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2788032 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2788032 # number of overall misses
+system.cpu.dcache.overall_misses::total 2788032 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 67394089000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 67394089000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 39986185470 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 39986185470 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 171500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 107380274470 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 107380274470 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 107380274470 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 107380274470 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 695862401 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 695862401 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11984 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 11984 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 11679 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 11679 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 972774084 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 972774084 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 972774084 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 972774084 # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 972798079 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 972798079 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 972798079 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 972798079 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000250 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000250 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.508124 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.989278 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.989278 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38495.249960 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.249960 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38495.249960 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 1740 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34502.328855 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34502.328855 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47904.169905 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47904.169905 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38514.720947 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38514.720947 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2182 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 795 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 88 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.964286 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 9.034091 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
-system.cpu.dcache.writebacks::total 96322 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488810 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 488810 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757757 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 757757 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 96308 # number of writebacks
+system.cpu.dcache.writebacks::total 96308 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488800 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 488800 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757854 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 757854 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1246567 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1246567 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1246567 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1246567 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464570 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1464570 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76846 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76846 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541416 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541416 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541416 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541416 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37884240500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 37884240500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3478487500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3478487500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41362728000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 41362728000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41362728000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 41362728000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 1246654 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1246654 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1246654 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1246654 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464520 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1464520 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76858 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76858 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541378 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541378 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541378 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541378 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37907812500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 37907812500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3481886500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3481886500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41389699000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 41389699000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41389699000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 41389699000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25884.120736 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25884.120736 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45302.850712 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45302.850712 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.026292 # Number of seconds simulated
-sim_ticks 26292466000 # Number of ticks simulated
-final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.026275 # Number of seconds simulated
+sim_ticks 26275145500 # Number of ticks simulated
+final_tick 26275145500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 43892 # Simulator instruction rate (inst/s)
-host_op_rate 62284 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16271073 # Simulator tick rate (ticks/s)
-host_mem_usage 263196 # Number of bytes of host memory used
-host_seconds 1615.90 # Real time elapsed on the host
-sim_insts 70925094 # Number of instructions simulated
-sim_ops 100644341 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11350476 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 302110574 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 313461050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11350476 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11350476 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 204330472 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 204330472 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 204330472 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11350476 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 302110574 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 517791522 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128777 # Total number of read requests seen
-system.physmem.writeReqs 83943 # Total number of write requests seen
-system.physmem.cpureqs 213018 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 8241664 # Total number of bytes read from memory
-system.physmem.bytesWritten 5372352 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 5372352 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 298 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 8167 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 8037 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 7896 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 7927 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 8024 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 7958 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 7983 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 8195 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 8177 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 8153 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 8060 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 8008 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 7983 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5171 # Track writes on a per bank basis
+host_inst_rate 119366 # Simulator instruction rate (inst/s)
+host_op_rate 169395 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44231565 # Simulator tick rate (ticks/s)
+host_mem_usage 271872 # Number of bytes of host memory used
+host_seconds 594.04 # Real time elapsed on the host
+sim_insts 70907629 # Number of instructions simulated
+sim_ops 100626876 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8240576 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 128759 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 11345779 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 302280495 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 313626275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 11345779 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 11345779 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 204474910 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 204474910 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 204474910 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 11345779 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 302280495 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 518101184 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 128759 # Total number of read requests seen
+system.physmem.writeReqs 83947 # Total number of write requests seen
+system.physmem.cpureqs 213029 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 8240576 # Total number of bytes read from memory
+system.physmem.bytesWritten 5372608 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 8240576 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 5372608 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 323 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 8173 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 8031 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 8094 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 7897 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 7925 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 8031 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 7954 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 7989 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 8189 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 8178 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 8151 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 8058 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 7986 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 7982 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5173 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 5231 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 5234 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 5166 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 5164 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5232 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 5372 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 5371 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 5150 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26292447500 # Total gap between requests
+system.physmem.totGap 26275013500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 128777 # Categorize read packet sizes
+system.physmem.readPktSize::6 128759 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 83943 # categorize write packet sizes
+system.physmem.writePktSize::6 83947 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 298 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 323 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 71059 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 55263 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2369 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 70960 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 55313 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2400 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3590 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3605 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4868163034 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests
-system.physmem.totBusLat 515096000 # Total cycles spent in databus access
-system.physmem.totBankLat 1373176000 # Total cycles spent in bank access
-system.physmem.avgQLat 37803.93 # Average queueing delay per request
-system.physmem.avgBankLat 10663.46 # Average bank access latency per request
+system.physmem.totQLat 4891352059 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 6777204059 # Sum of mem lat for all requests
+system.physmem.totBusLat 515028000 # Total cycles spent in databus access
+system.physmem.totBankLat 1370824000 # Total cycles spent in bank access
+system.physmem.avgQLat 37989.02 # Average queueing delay per request
+system.physmem.avgBankLat 10646.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52467.38 # Average memory access latency
-system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 204.33 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 52635.62 # Average memory access latency
+system.physmem.avgRdBW 313.63 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 204.47 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 313.63 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 204.47 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.24 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.26 # Average read queue length over time
-system.physmem.avgWrQLen 9.45 # Average write queue length over time
-system.physmem.readRowHits 118938 # Number of row buffer hits during reads
-system.physmem.writeRowHits 27082 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 9.34 # Average write queue length over time
+system.physmem.readRowHits 118922 # Number of row buffer hits during reads
+system.physmem.writeRowHits 27176 # Number of row buffer hits during writes
system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 32.26 # Row buffer hit rate for writes
-system.physmem.avgGap 123601.20 # Average gap between requests
+system.physmem.writeRowHitRate 32.37 # Row buffer hit rate for writes
+system.physmem.avgGap 123527.37 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 52584933 # number of cpu cycles simulated
+system.cpu.numCycles 52550292 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 16605622 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12744819 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 601134 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10608037 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7769778 # Number of BTB hits
+system.cpu.BPredUnit.lookups 16626972 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12763144 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 604576 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10780847 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7773827 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 1825491 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 113784 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 12554350 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 85230964 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16626972 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9599318 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21200413 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2370934 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 10497631 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11689041 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 183016 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 45992800 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.594519 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.335814 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1463280 3.18% 70.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1379331 3.00% 73.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 959670 2.08% 75.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1190775 2.59% 78.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24812491 53.95% 53.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2139973 4.65% 58.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1966955 4.28% 62.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2042614 4.44% 67.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1467231 3.19% 70.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1381601 3.00% 73.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 958651 2.08% 75.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1187660 2.58% 78.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10035624 21.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3326611 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 104659 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 116720432 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 360894 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19086496 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29582757 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 22430841 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3912004 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4391398 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 111440700 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 41006 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 107204361 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 269260 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 45992800 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.316401 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.621893 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 14631573 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8854890 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19476912 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1392472 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1636953 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3331046 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 104815 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 116877182 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 363170 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1636953 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 16335988 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2535467 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 864548 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19115469 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5504375 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 114992065 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 17001 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4650627 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 317 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 115303250 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 529787373 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 529782097 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 5276 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 16170578 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 20502 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 20496 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13002691 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29626313 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 22450124 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3876856 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4338192 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 111565223 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 36031 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 107269202 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 275818 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10829565 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 25919062 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2245 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 45992800 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.332304 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.990217 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5412181 11.75% 84.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3900032 8.47% 92.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1833850 3.98% 96.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 869462 1.89% 98.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10779099 23.44% 23.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 8049451 17.50% 40.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7422892 16.14% 57.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7126081 15.49% 72.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5395767 11.73% 84.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3928809 8.54% 92.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1841047 4.00% 96.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 874903 1.90% 98.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 574751 1.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 45992800 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1351687 54.87% 59.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1001007 40.64% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 114108 4.61% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1356583 54.78% 59.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 1005840 40.61% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 56616683 52.81% 52.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91709 0.09% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 161 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 28875176 26.93% 79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21620625 20.17% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 56641700 52.80% 52.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 91676 0.09% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 165 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 28901726 26.94% 79.83% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21633928 20.17% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 107204361 # Type of FU issued
-system.cpu.iq.rate 2.038690 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 696 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 107269202 # Type of FU issued
+system.cpu.iq.rate 2.041267 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2476532 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.023087 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 263283068 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 122458972 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 105581252 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 486 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 768 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 109667441 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2181528 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 109745491 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2188417 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2272156 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6578 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29396 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1871610 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2319205 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6776 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29966 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1894386 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 28 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 493 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 503 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1617500 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6480 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5483 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29396 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 390184 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 182395 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 572579 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106179962 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 28578383 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1024399 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1636953 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1044060 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 45930 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 111611011 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 291580 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29626313 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 22450124 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 20111 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 6644 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 5462 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29966 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 393316 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 181236 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 574552 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 106238160 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 28602099 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1031042 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9804 # number of nop insts executed
-system.cpu.iew.exec_refs 49916161 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14598129 # Number of branches executed
-system.cpu.iew.exec_stores 21337778 # Number of stores executed
-system.cpu.iew.exec_rate 2.019209 # Inst execution rate
-system.cpu.iew.wb_sent 105751543 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 105534073 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 53248858 # num instructions producing a value
-system.cpu.iew.wb_consumers 103476528 # num instructions consuming a value
+system.cpu.iew.exec_nop 9757 # number of nop insts executed
+system.cpu.iew.exec_refs 49948126 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14604066 # Number of branches executed
+system.cpu.iew.exec_stores 21346027 # Number of stores executed
+system.cpu.iew.exec_rate 2.021647 # Inst execution rate
+system.cpu.iew.wb_sent 105801461 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 105581404 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 53258894 # num instructions producing a value
+system.cpu.iew.wb_consumers 103486689 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.006926 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.514598 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.009150 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.514645 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 10979497 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 501718 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 44355847 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.268752 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.766108 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1877627 4.23% 79.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1953879 4.40% 83.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 688656 1.55% 85.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 567495 1.28% 86.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 15312059 34.52% 34.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11621987 26.20% 60.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3450685 7.78% 68.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2867250 6.46% 74.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1878784 4.24% 79.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1958737 4.42% 83.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 685559 1.55% 85.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 561142 1.27% 86.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6019644 13.57% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 70930646 # Number of instructions committed
-system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 44355847 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 70913181 # Number of instructions committed
+system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 47869832 # Number of memory references committed
-system.cpu.commit.loads 27310601 # Number of loads committed
+system.cpu.commit.refs 47862846 # Number of memory references committed
+system.cpu.commit.loads 27307108 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
-system.cpu.commit.branches 13744998 # Number of branches committed
+system.cpu.commit.branches 13741505 # Number of branches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 91486751 # Number of committed integer instructions.
+system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6019644 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 149890856 # The number of ROB reads
-system.cpu.rob.rob_writes 224611140 # The number of ROB writes
-system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 70925094 # Number of Instructions Simulated
-system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated
-system.cpu.cpi 0.741415 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.741415 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.348772 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.348772 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 511431338 # number of integer regfile reads
-system.cpu.int_regfile_writes 103318196 # number of integer regfile writes
-system.cpu.fp_regfile_reads 686 # number of floating regfile reads
-system.cpu.fp_regfile_writes 582 # number of floating regfile writes
-system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads
-system.cpu.misc_regfile_writes 38826 # number of misc regfile writes
-system.cpu.icache.replacements 30543 # number of replacements
-system.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use
-system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 149922829 # The number of ROB reads
+system.cpu.rob.rob_writes 224870236 # The number of ROB writes
+system.cpu.timesIdled 74082 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 6557492 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 70907629 # Number of Instructions Simulated
+system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
+system.cpu.cpi 0.741109 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.741109 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.349329 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.349329 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 511669135 # number of integer regfile reads
+system.cpu.int_regfile_writes 103349973 # number of integer regfile writes
+system.cpu.fp_regfile_reads 690 # number of floating regfile reads
+system.cpu.fp_regfile_writes 602 # number of floating regfile writes
+system.cpu.misc_regfile_reads 49186281 # number of misc regfile reads
+system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
+system.cpu.icache.replacements 29504 # number of replacements
+system.cpu.icache.tagsinuse 1815.541660 # Cycle average of tags in use
+system.cpu.icache.total_refs 11653533 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 31535 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 369.542825 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11635567 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11635567 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits
-system.cpu.icache.overall_hits::total 11635567 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses
-system.cpu.icache.overall_misses::total 36658 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 709083999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 709083999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11672225 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11672225 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11672225 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11672225 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11672225 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11672225 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19343.226554 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19343.226554 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1815.541660 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.886495 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.886495 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 11653539 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 11653539 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 11653539 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 11653539 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 11653539 # number of overall hits
+system.cpu.icache.overall_hits::total 11653539 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 35502 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 35502 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 35502 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 35502 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 35502 # number of overall misses
+system.cpu.icache.overall_misses::total 35502 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 704211999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 704211999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 704211999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 704211999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 704211999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 704211999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11689041 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11689041 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11689041 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11689041 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11689041 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11689041 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003037 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.003037 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.003037 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.003037 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.003037 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.003037 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19835.840206 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19835.840206 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19835.840206 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19835.840206 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 96.590909 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580605499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 580605499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580605499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 580605499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580605499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 580605499 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3638 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 3638 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 3638 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 3638 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 3638 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 3638 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31864 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 31864 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 31864 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 31864 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 31864 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 31864 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 575585499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 575585499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 575585499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 575585499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 575585499 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 575585499 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002726 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.002726 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.002726 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18063.818071 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18063.818071 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18063.818071 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18063.818071 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18063.818071 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18063.818071 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 95650 # number of replacements
-system.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 95629 # number of replacements
+system.cpu.l2cache.tagsinuse 30144.051156 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 89024 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 126742 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.702403 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.820340 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.042099 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.057268 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.919707 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 27693 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 33453 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 61146 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 129052 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 129052 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 19 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 19 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 4778 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 4778 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 27693 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 38231 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 65924 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 27693 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 38231 # number of overall hits
-system.cpu.l2cache.overall_hits::total 65924 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 4680 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 21915 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 26595 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 298 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 298 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 102256 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 102256 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 4680 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 124171 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 128851 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 124171 # number of overall misses
-system.cpu.l2cache.overall_misses::total 128851 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269871000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664900000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1934771000 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8091962000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 8091962000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 269871000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9756862000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 10026733000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 269871000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9756862000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 10026733000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 32373 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 55368 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 87741 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 129052 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 129052 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 317 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 317 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 32373 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 162402 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 194775 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 32373 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 162402 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 194775 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.144565 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395806 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.303108 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.940063 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.940063 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955360 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.955360 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144565 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.764590 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.661538 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144565 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.764590 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.661538 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.743590 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.796258 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.426584 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 77.181208 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 77.181208 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79134.349085 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79134.349085 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77816.493469 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77816.493469 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 26895.492569 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1376.193192 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1872.365396 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.820785 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.041998 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.057140 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.919923 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 26680 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 33529 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 60209 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 129085 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 129085 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 4762 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 4762 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 26680 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 38291 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 64971 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 26680 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 38291 # number of overall hits
+system.cpu.l2cache.overall_hits::total 64971 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 4675 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 21899 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 26574 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 322 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 322 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 102258 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 102258 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 4675 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 124157 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 128832 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 4675 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 124157 # number of overall misses
+system.cpu.l2cache.overall_misses::total 128832 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 276010000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1652820000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1928830000 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8120181000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 8120181000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 276010000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9773001000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 10049011000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 276010000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9773001000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 10049011000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 31355 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 55428 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 86783 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 129085 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 129085 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 339 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 339 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 107020 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 107020 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 31355 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 162448 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 193803 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 31355 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 162448 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 193803 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.149099 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395089 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.306212 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.949853 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.949853 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955504 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.955504 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149099 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.764288 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.664758 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149099 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.764288 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.664758 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59039.572193 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75474.679209 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72583.352149 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 69.875776 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 69.875776 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79408.760195 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79408.760195 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59039.572193 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78714.861023 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78000.892635 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59039.572193 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78714.861023 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78000.892635 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 83943 # number of writebacks
-system.cpu.l2cache.writebacks::total 83943 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 26521 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 298 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 298 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 124113 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 128777 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 124113 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210183444 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1389842080 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600025524 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2980298 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2980298 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6821241683 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6821241683 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210183444 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8211083763 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 8421267207 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210183444 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 8421267207 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.940063 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.940063 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955360 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955360 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.661158 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45065.060892 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.512575 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66707.495726 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66707.495726 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks
+system.cpu.l2cache.writebacks::total 83947 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4658 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21844 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 26502 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 322 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 322 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102258 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 102258 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 4658 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 124102 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 128760 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 4658 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 124102 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 128760 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 216322911 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1377962821 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1594285732 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3234820 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3234820 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6849492072 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6849492072 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216322911 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8227454893 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 8443777804 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216322911 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8227454893 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 8443777804 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394097 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305382 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.949853 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.949853 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955504 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955504 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763949 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.664386 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763949 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.664386 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46441.157364 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63081.982283 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60157.185571 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10046.024845 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10046.024845 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66982.456844 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66982.456844 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 158306 # number of replacements
-system.cpu.dcache.tagsinuse 4072.986678 # Cycle average of tags in use
-system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4072.986678 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits
-system.cpu.dcache.overall_hits::total 44303188 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses
-system.cpu.dcache.overall_misses::total 1709363 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670086500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4670086500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 124709259481 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 124709259481 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 124709259481 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 124709259481 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements 158352 # number of replacements
+system.cpu.dcache.tagsinuse 4073.285602 # Cycle average of tags in use
+system.cpu.dcache.total_refs 44355767 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 162448 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 273.045941 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 278219000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4073.285602 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.994454 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.994454 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 26058145 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 26058145 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18265070 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18265070 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 15998 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 15998 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 44323215 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 44323215 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 44323215 # number of overall hits
+system.cpu.dcache.overall_hits::total 44323215 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 124984 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 124984 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1584831 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1584831 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1709815 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1709815 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1709815 # number of overall misses
+system.cpu.dcache.overall_misses::total 1709815 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4634379500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4634379500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 120528782979 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 120528782979 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 848000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 848000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 125163162479 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 125163162479 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 125163162479 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 125163162479 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 26183129 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 26183129 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.307299 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.307299 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72956.568898 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72956.568898 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16039 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 16039 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46033030 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46033030 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46033030 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46033030 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004773 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004773 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002556 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002556 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037143 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.037143 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037143 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.037143 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37079.782212 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 37079.782212 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76051.505163 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76051.505163 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20682.926829 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20682.926829 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73202.751455 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73202.751455 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 3167 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 649 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.784173 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 43.266667 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks
-system.cpu.dcache.writebacks::total 129052 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060279000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060279000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313871492 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10313871492 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313871492 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 129085 # number of writebacks
+system.cpu.dcache.writebacks::total 129085 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69523 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 69523 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477505 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1477505 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1547028 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1547028 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1547028 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1547028 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55461 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55461 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107326 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107326 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 162787 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 162787 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 162787 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 162787 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2049044000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2049044000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8282203488 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8282203488 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10331247488 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10331247488 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10331247488 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10331247488 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36945.673536 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36945.673536 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77168.658927 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77168.658927 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.506577 # Number of seconds simulated
-sim_ticks 506577346000 # Number of ticks simulated
-final_tick 506577346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.506354 # Number of seconds simulated
+sim_ticks 506353996500 # Number of ticks simulated
+final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 78526 # Simulator instruction rate (inst/s)
-host_op_rate 87602 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25754624 # Simulator tick rate (ticks/s)
-host_mem_usage 525748 # Number of bytes of host memory used
-host_seconds 19669.37 # Real time elapsed on the host
-sim_insts 1544563048 # Number of instructions simulated
-sim_ops 1723073860 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 47872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 143709504 # Number of bytes read from this memory
-system.physmem.bytes_read::total 143757376 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 47872 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 47872 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70427136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70427136 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 748 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2245461 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2246209 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1100424 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1100424 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 94501 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 283687190 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 283781691 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 94501 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 94501 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 139025435 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 139025435 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 139025435 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 94501 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 283687190 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 422807126 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2246209 # Total number of read requests seen
-system.physmem.writeReqs 1100424 # Total number of write requests seen
-system.physmem.cpureqs 3346633 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 143757376 # Total number of bytes read from memory
-system.physmem.bytesWritten 70427136 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 143757376 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 70427136 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 648 # Number of read reqs serviced by write Q
+host_inst_rate 136322 # Simulator instruction rate (inst/s)
+host_op_rate 152077 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44690362 # Simulator tick rate (ticks/s)
+host_mem_usage 507940 # Number of bytes of host memory used
+host_seconds 11330.27 # Real time elapsed on the host
+sim_insts 1544563023 # Number of instructions simulated
+sim_ops 1723073835 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 143771904 # Number of bytes read from this memory
+system.physmem.bytes_read::total 143819904 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 70451968 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70451968 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2246436 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2247186 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1100812 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1100812 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 94795 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 283935557 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 284030352 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 94795 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 94795 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 139135799 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 139135799 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 139135799 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 94795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 283935557 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 423166152 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2247186 # Total number of read requests seen
+system.physmem.writeReqs 1100812 # Total number of write requests seen
+system.physmem.cpureqs 3347998 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 143819904 # Total number of bytes read from memory
+system.physmem.bytesWritten 70451968 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 143819904 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 70451968 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 672 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 139859 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 143718 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 141709 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 141024 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 137951 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 140151 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 141411 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 141047 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 141131 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 139616 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 140441 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 140596 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 136994 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 141023 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 138860 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 140030 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 69285 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 70316 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 69579 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 68829 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 67740 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 68386 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 68704 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 68489 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 68246 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 68330 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 68656 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 68488 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 67093 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 70319 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 69051 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 68913 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 139825 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 143804 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 141798 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 141106 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 137923 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 140335 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 141438 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 140855 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 141349 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 139500 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 140412 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 140930 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 137255 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 141125 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 138862 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 139997 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 69198 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 70413 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 69591 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 68873 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 67768 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 68429 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 68697 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 68477 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 68286 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 68308 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 68629 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 68528 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 67273 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 70384 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 69023 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 68935 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 506577272500 # Total gap between requests
+system.physmem.totGap 506353933500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 2246209 # Categorize read packet sizes
+system.physmem.readPktSize::6 2247186 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 1100424 # categorize write packet sizes
+system.physmem.writePktSize::6 1100812 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1577632 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 445457 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 156427 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 66028 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1577555 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 446581 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 156376 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 65982 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 45454 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 47483 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 47799 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 47836 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 47845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 47845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 47845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 47845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 47845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 47845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 47845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 47844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2391 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 362 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 45520 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 47517 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 47811 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 47856 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 47862 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 47862 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 47862 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 47862 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 47861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2342 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 345 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 27034566792 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 102738360792 # Sum of mem lat for all requests
-system.physmem.totBusLat 8982244000 # Total cycles spent in databus access
-system.physmem.totBankLat 66721550000 # Total cycles spent in bank access
-system.physmem.avgQLat 12039.11 # Average queueing delay per request
-system.physmem.avgBankLat 29712.64 # Average bank access latency per request
+system.physmem.totQLat 27009597750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 102747541750 # Sum of mem lat for all requests
+system.physmem.totBusLat 8986056000 # Total cycles spent in databus access
+system.physmem.totBankLat 66751888000 # Total cycles spent in bank access
+system.physmem.avgQLat 12022.89 # Average queueing delay per request
+system.physmem.avgBankLat 29713.54 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 45751.76 # Average memory access latency
-system.physmem.avgRdBW 283.78 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 139.03 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 283.78 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 139.03 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 45736.44 # Average memory access latency
+system.physmem.avgRdBW 284.03 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 139.14 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 284.03 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 139.14 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.64 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.20 # Average read queue length over time
-system.physmem.avgWrQLen 10.83 # Average write queue length over time
-system.physmem.readRowHits 914455 # Number of row buffer hits during reads
-system.physmem.writeRowHits 188951 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads
+system.physmem.avgWrQLen 11.52 # Average write queue length over time
+system.physmem.readRowHits 914505 # Number of row buffer hits during reads
+system.physmem.writeRowHits 189005 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes
-system.physmem.avgGap 151369.23 # Average gap between requests
+system.physmem.avgGap 151240.81 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1013154693 # number of cpu cycles simulated
+system.cpu.numCycles 1012707994 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 302078234 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 248282516 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 15228940 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 174133457 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 160366522 # Number of BTB hits
+system.cpu.BPredUnit.lookups 301930111 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 248173247 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 15201095 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 171785530 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 160276899 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 17581353 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 196 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 296396923 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2177678223 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 302078234 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 177947875 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 433295900 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 86556891 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 152970163 # Number of cycles fetch has spent blocked
-system.cpu.fetch.PendingTrapStallCycles 65 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 286931136 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5530103 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 951710373 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.532755 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.215871 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 17551988 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 177828887 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 433076308 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 86433742 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 153009166 # Number of cycles fetch has spent blocked
+system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 286734480 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5522368 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 951217236 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.532975 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.216056 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 518414544 54.47% 54.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25023553 2.63% 57.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 39078902 4.11% 61.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 48295865 5.07% 66.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 42590853 4.48% 70.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46358394 4.87% 75.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38409844 4.04% 79.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18541861 1.95% 81.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 174996557 18.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 518141000 54.47% 54.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25031243 2.63% 57.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 39020791 4.10% 61.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 48260411 5.07% 66.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 42551008 4.47% 70.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46329866 4.87% 75.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38408585 4.04% 79.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 18543654 1.95% 81.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 174930678 18.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 951710373 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.298156 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.149403 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 327700398 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 131274030 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 403657963 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20031323 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 69046659 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46033752 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2358943633 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2468 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 69046659 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 350846153 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 61254563 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 16168 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 399028257 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71518573 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2298097948 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 126905 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5030989 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 58378290 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 21 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2273047323 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10612493947 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10612490107 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3840 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1706319970 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 566727353 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 579 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 576 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 158294547 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 623264205 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 220545745 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 86083879 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 71111807 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2197176983 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 617 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2016362984 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3976433 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 469561245 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1109303126 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 442 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 951710373 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.118673 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.906088 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 951217236 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.298141 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.149522 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 327471231 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 131306156 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 403441377 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20045518 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 68952954 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46012127 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2358019040 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2460 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 68952954 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 350612417 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 61250936 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 16584 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 398830274 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 71554071 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2297211554 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 127534 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5036199 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 58405264 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2272168650 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10608574023 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10608571065 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2958 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 565848720 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 855 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 852 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 158388501 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 623121269 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 220470896 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 86042540 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 70771050 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2196546407 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 888 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2016009796 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3969588 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 468927262 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1107841980 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 718 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 951217236 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.119400 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.906359 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 271681104 28.55% 28.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 151029292 15.87% 44.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 160860951 16.90% 61.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 119423719 12.55% 73.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 124040655 13.03% 86.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 73844505 7.76% 94.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 38423887 4.04% 98.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 9837914 1.03% 99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2568346 0.27% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 271448438 28.54% 28.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 150881497 15.86% 44.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 160823100 16.91% 61.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 119315575 12.54% 73.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 124031902 13.04% 86.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 73881034 7.77% 94.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 38429694 4.04% 98.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 9823536 1.03% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2582460 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 951710373 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 951217236 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 884251 3.71% 3.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5803 0.02% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 18260912 76.52% 80.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4713024 19.75% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 875964 3.67% 3.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5764 0.02% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 18242361 76.45% 80.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4736544 19.85% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1235730188 61.29% 61.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 925294 0.05% 61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1235492979 61.28% 61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 925544 0.05% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 40 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 27 0.00% 61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 13 0.00% 61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 586669934 29.10% 90.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193037461 9.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 586540633 29.09% 90.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193050569 9.58% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2016362984 # Type of FU issued
-system.cpu.iq.rate 1.990183 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 23863990 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011835 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5012276382 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2666928163 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1956898360 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 382 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 744 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2040226783 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 191 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 64738379 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2016009796 # Type of FU issued
+system.cpu.iq.rate 1.990712 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 23860633 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011836 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5011066759 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2665664471 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1956606463 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 290 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2039870285 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 64705720 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 137337431 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 268034 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 192473 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 45698695 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 137194500 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 273797 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 192943 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 45623851 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 3808296 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 3807412 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 69046659 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27170871 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1494320 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2197177695 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 6112052 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 623264205 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 220545745 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 552 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 473344 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 89494 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 192473 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8164015 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 9611639 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 17775654 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1986719031 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 573114745 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 29643953 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 68952954 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27155997 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1495704 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2196547422 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 6100181 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 623121269 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 220470896 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 826 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 473871 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 90052 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 192943 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8142096 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 9608050 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 17750146 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1986410888 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 573023734 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29598908 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 95 # number of nop insts executed
-system.cpu.iew.exec_refs 763276448 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238352176 # Number of branches executed
-system.cpu.iew.exec_stores 190161703 # Number of stores executed
-system.cpu.iew.exec_rate 1.960924 # Inst execution rate
-system.cpu.iew.wb_sent 1965347769 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1956898514 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1295796153 # num instructions producing a value
-system.cpu.iew.wb_consumers 2060480328 # num instructions consuming a value
+system.cpu.iew.exec_nop 127 # number of nop insts executed
+system.cpu.iew.exec_refs 763190345 # number of memory reference insts executed
+system.cpu.iew.exec_branches 238305534 # Number of branches executed
+system.cpu.iew.exec_stores 190166611 # Number of stores executed
+system.cpu.iew.exec_rate 1.961484 # Inst execution rate
+system.cpu.iew.wb_sent 1965043499 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1956606576 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1295701772 # num instructions producing a value
+system.cpu.iew.wb_consumers 2060221208 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.931490 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.628881 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.932054 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.628914 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 474201695 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 175 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15228277 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 882663714 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.952130 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.732822 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 473572340 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 15200427 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 882264282 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.953013 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.733344 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 395325741 44.79% 44.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 192113195 21.77% 66.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 72479892 8.21% 74.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35250909 3.99% 78.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18971392 2.15% 80.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30754959 3.48% 84.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 20068273 2.27% 86.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11416653 1.29% 87.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106282700 12.04% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 395036396 44.78% 44.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 191994213 21.76% 66.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 72477507 8.21% 74.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35260039 4.00% 78.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 18947912 2.15% 80.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 30765236 3.49% 84.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 20067867 2.27% 86.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11401417 1.29% 87.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106313695 12.05% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 882663714 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1544563066 # Number of instructions committed
-system.cpu.commit.committedOps 1723073878 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 882264282 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
+system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 660773824 # Number of memory references committed
-system.cpu.commit.loads 485926774 # Number of loads committed
+system.cpu.commit.refs 660773814 # Number of memory references committed
+system.cpu.commit.loads 485926769 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
-system.cpu.commit.branches 213462431 # Number of branches committed
+system.cpu.commit.branches 213462426 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1536941861 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106282700 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106313695 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2973655988 # The number of ROB reads
-system.cpu.rob.rob_writes 4463745378 # The number of ROB writes
-system.cpu.timesIdled 1007703 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 61444320 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1544563048 # Number of Instructions Simulated
-system.cpu.committedOps 1723073860 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1544563048 # Number of Instructions Simulated
-system.cpu.cpi 0.655949 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.655949 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.524509 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.524509 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 9950552971 # number of integer regfile reads
-system.cpu.int_regfile_writes 1936868290 # number of integer regfile writes
-system.cpu.fp_regfile_reads 164 # number of floating regfile reads
-system.cpu.fp_regfile_writes 170 # number of floating regfile writes
-system.cpu.misc_regfile_reads 737621516 # number of misc regfile reads
-system.cpu.misc_regfile_writes 134 # number of misc regfile writes
+system.cpu.rob.rob_reads 2972596181 # The number of ROB reads
+system.cpu.rob.rob_writes 4462393115 # The number of ROB writes
+system.cpu.timesIdled 1008109 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 61490758 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
+system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
+system.cpu.cpi 0.655660 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.655660 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.525181 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.525181 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 9949148949 # number of integer regfile reads
+system.cpu.int_regfile_writes 1936492974 # number of integer regfile writes
+system.cpu.fp_regfile_reads 113 # number of floating regfile reads
+system.cpu.fp_regfile_writes 115 # number of floating regfile writes
+system.cpu.misc_regfile_reads 737540247 # number of misc regfile reads
+system.cpu.misc_regfile_writes 124 # number of misc regfile writes
system.cpu.icache.replacements 23 # number of replacements
-system.cpu.icache.tagsinuse 625.920238 # Cycle average of tags in use
-system.cpu.icache.total_refs 286929961 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 368331.143774 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 625.185145 # Cycle average of tags in use
+system.cpu.icache.total_refs 286733320 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 778 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 368551.825193 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 625.920238 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.305625 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.305625 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 286929961 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 286929961 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 286929961 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 286929961 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 286929961 # number of overall hits
-system.cpu.icache.overall_hits::total 286929961 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1175 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1175 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1175 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1175 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1175 # number of overall misses
-system.cpu.icache.overall_misses::total 1175 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 61332500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 61332500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 61332500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 61332500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 61332500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 61332500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 286931136 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 286931136 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 286931136 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 286931136 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 286931136 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 286931136 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 625.185145 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.305266 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.305266 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 286733320 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 286733320 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 286733320 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 286733320 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 286733320 # number of overall hits
+system.cpu.icache.overall_hits::total 286733320 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1160 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1160 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1160 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1160 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1160 # number of overall misses
+system.cpu.icache.overall_misses::total 1160 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 59910000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 59910000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 59910000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 59910000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 59910000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 59910000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 286734480 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 286734480 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 286734480 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 286734480 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 286734480 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 286734480 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52197.872340 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 52197.872340 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 52197.872340 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 52197.872340 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 52197.872340 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 52197.872340 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51646.551724 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 51646.551724 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 51646.551724 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 51646.551724 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42649000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 42649000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42649000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 42649000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42649000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 42649000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 382 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 382 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 382 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 382 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43554500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 43554500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43554500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 43554500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43554500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 43554500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54748.395379 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54748.395379 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54748.395379 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54748.395379 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54748.395379 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54748.395379 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55982.647815 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55982.647815 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 2213514 # number of replacements
-system.cpu.l2cache.tagsinuse 31523.929913 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 9246342 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 2243293 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 4.121772 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 2214498 # number of replacements
+system.cpu.l2cache.tagsinuse 31523.726273 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9246379 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2244276 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.119983 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 20414306502 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14436.839849 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 20.727036 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 17066.363028 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.440577 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.000633 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.520824 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.962034 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 6288773 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 6288803 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 3781738 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 3781738 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 1067182 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 1067182 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 7355955 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 7355985 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 7355955 # number of overall hits
-system.cpu.l2cache.overall_hits::total 7355985 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 749 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1419078 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1419827 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 826390 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 826390 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 749 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 2245468 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 2246217 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 749 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 2245468 # number of overall misses
-system.cpu.l2cache.overall_misses::total 2246217 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41559000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98096930500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 98138489500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58737447000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 58737447000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 41559000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 156834377500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 156875936500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 41559000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 156834377500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 156875936500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 779 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 7707851 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7708630 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 3781738 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 3781738 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893572 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1893572 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 779 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 9601423 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 9602202 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 779 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 9601423 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 9602202 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961489 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184108 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.184187 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436419 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.436419 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961489 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.233868 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.233927 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961489 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.233868 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.233927 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55485.981308 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69127.229441 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69120.033286 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71077.151224 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71077.151224 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55485.981308 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69844.850828 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69840.062870 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55485.981308 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69844.850828 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69840.062870 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 14432.975360 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 20.502484 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 17070.248430 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.440459 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000626 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.520943 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.962028 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 6289310 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 6289336 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 3781550 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 3781550 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1066723 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1066723 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 7356033 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 7356059 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 7356033 # number of overall hits
+system.cpu.l2cache.overall_hits::total 7356059 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 752 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1419753 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1420505 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 826690 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 826690 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 752 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 2246443 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 2247195 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 752 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 2246443 # number of overall misses
+system.cpu.l2cache.overall_misses::total 2247195 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42504500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98123407500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 98165912000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58742590000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 58742590000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 42504500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 156865997500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 156908502000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 42504500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 156865997500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 156908502000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 7709063 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7709841 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3781550 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3781550 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893413 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1893413 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 9602476 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9603254 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 9602476 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9603254 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.966581 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184167 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.184246 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436614 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.436614 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966581 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.233944 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.234003 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966581 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.233944 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.234003 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56521.941489 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69113.012968 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.347391 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71057.579020 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71057.579020 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56521.941489 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69828.612389 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69824.159452 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56521.941489 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69828.612389 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69824.159452 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1100424 # number of writebacks
-system.cpu.l2cache.writebacks::total 1100424 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks 1100812 # number of writebacks
+system.cpu.l2cache.writebacks::total 1100812 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 748 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419071 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1419819 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826390 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 826390 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 748 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2245461 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2246209 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 748 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2245461 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2246209 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32066173 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80158804465 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80190870638 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48314626333 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48314626333 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32066173 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128473430798 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 128505496971 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32066173 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128473430798 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 128505496971 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184107 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184186 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436419 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436419 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233868 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.233926 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960205 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233868 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.233926 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42869.215241 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56486.817407 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56479.643277 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58464.679308 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58464.679308 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42869.215241 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57214.723746 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57209.946613 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42869.215241 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57214.723746 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57209.946613 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 750 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419746 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1420496 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826690 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 826690 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 750 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2246436 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2247186 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 750 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2246436 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2247186 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32919184 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80176207714 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80209126898 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48315790009 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48315790009 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32919184 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128491997723 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 128524916907 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32919184 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128491997723 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 128524916907 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184166 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184245 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436614 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436614 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.234003 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.234003 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43892.245333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56472.219477 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56465.577445 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58444.870519 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58444.870519 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9597327 # number of replacements
-system.cpu.dcache.tagsinuse 4087.938249 # Cycle average of tags in use
-system.cpu.dcache.total_refs 656067317 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9601423 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 68.330217 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 9598379 # number of replacements
+system.cpu.dcache.tagsinuse 4087.934747 # Cycle average of tags in use
+system.cpu.dcache.total_refs 656008169 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9602475 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 68.316571 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3424422000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.938249 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.998032 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.998032 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 489013498 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 489013498 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 167053663 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 167053663 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 90 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 90 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 66 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 66 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 656067161 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 656067161 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 656067161 # number of overall hits
-system.cpu.dcache.overall_hits::total 656067161 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 11472935 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 11472935 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5532384 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5532384 # number of WriteReq misses
+system.cpu.dcache.occ_blocks::cpu.data 4087.934747 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 488954223 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 488954223 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 167053823 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 167053823 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 656008046 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 656008046 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 656008046 # number of overall hits
+system.cpu.dcache.overall_hits::total 656008046 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 11476242 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 11476242 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5532224 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5532224 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 17005319 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 17005319 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 17005319 # number of overall misses
-system.cpu.dcache.overall_misses::total 17005319 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 299507112500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 299507112500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 217112545758 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 217112545758 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 516619658258 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 516619658258 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 516619658258 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 516619658258 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 500486433 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 500486433 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 17008466 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 17008466 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 17008466 # number of overall misses
+system.cpu.dcache.overall_misses::total 17008466 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 299283762000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 299283762000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 216949721927 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 216949721927 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 516233483927 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 516233483927 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 516233483927 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 516233483927 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 500430465 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 500430465 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 93 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 93 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 66 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 66 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 673072480 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 673072480 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 673072480 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 673072480 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022924 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.022924 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032056 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032056 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032258 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.032258 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025265 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025265 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025265 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025265 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26105.535550 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26105.535550 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39243.940001 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39243.940001 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30379.886332 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30379.886332 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30379.886332 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30379.886332 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 19797443 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 993226 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1172557 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.883992 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 15.388594 # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 673016512 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 673016512 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 673016512 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 673016512 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032055 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.032055 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025272 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025272 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025272 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025272 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26078.550975 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26078.550975 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39215.643099 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39215.643099 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30351.560448 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30351.560448 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 19781174 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 987477 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1172505 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 64541 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.870865 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 15.299995 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3781738 # number of writebacks
-system.cpu.dcache.writebacks::total 3781738 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3765084 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3765084 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638812 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3638812 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 3781550 # number of writebacks
+system.cpu.dcache.writebacks::total 3781550 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767179 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3767179 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638811 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3638811 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7403896 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7403896 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7403896 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7403896 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707851 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7707851 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893572 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1893572 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9601423 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9601423 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9601423 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9601423 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170518232500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 170518232500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71841286448 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 71841286448 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242359518948 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 242359518948 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242359518948 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 242359518948 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22122.668497 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22122.668497 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37939.558912 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37939.558912 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.041617 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.041617 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.041617 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.041617 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 7405990 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7405990 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7405990 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7405990 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709063 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7709063 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893413 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1893413 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9602476 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9602476 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9602476 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9602476 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170550521000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 170550521000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71842126604 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 71842126604 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242392647604 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 242392647604 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242392647604 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 242392647604 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22123.378808 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22123.378808 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37943.188625 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37943.188625 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.074245 # Number of seconds simulated
-sim_ticks 74245032000 # Number of ticks simulated
-final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.074149 # Number of seconds simulated
+sim_ticks 74148853000 # Number of ticks simulated
+final_tick 74148853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 44193 # Simulator instruction rate (inst/s)
-host_op_rate 48386 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19039219 # Simulator tick rate (ticks/s)
-host_mem_usage 236076 # Number of bytes of host memory used
-host_seconds 3899.58 # Real time elapsed on the host
-sim_insts 172333441 # Number of instructions simulated
-sim_ops 188686923 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory
-system.physmem.bytes_read::total 242688 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 131008 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 131008 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2047 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3792 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1764536 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1504208 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3268744 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1764536 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1764536 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1764536 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1504208 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3268744 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3793 # Total number of read requests seen
+host_inst_rate 112590 # Simulator instruction rate (inst/s)
+host_op_rate 123276 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48451809 # Simulator tick rate (ticks/s)
+host_mem_usage 247684 # Number of bytes of host memory used
+host_seconds 1530.36 # Real time elapsed on the host
+sim_insts 172303021 # Number of instructions simulated
+sim_ops 188656503 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 131648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 111744 # Number of bytes read from this memory
+system.physmem.bytes_read::total 243392 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 131648 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 131648 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2057 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1746 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3803 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1775456 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1507023 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3282478 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1775456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1775456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1775456 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1507023 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3282478 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 3804 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 3795 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 242688 # Total number of bytes read from memory
+system.physmem.cpureqs 3804 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 243392 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 242688 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 243392 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 231 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 191 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 236 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 190 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 235 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 242 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 243 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 247 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 259 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 248 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 249 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 261 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 179 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 237 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 239 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 74245013500 # Total gap between requests
+system.physmem.totGap 74148834500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 3793 # Categorize read packet sizes
+system.physmem.readPktSize::6 3804 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 2 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 2791 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 811 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 2808 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 800 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 12368785 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests
-system.physmem.totBusLat 15172000 # Total cycles spent in databus access
-system.physmem.totBankLat 58828000 # Total cycles spent in bank access
-system.physmem.avgQLat 3260.95 # Average queueing delay per request
-system.physmem.avgBankLat 15509.62 # Average bank access latency per request
+system.physmem.totQLat 11954297 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 86040297 # Sum of mem lat for all requests
+system.physmem.totBusLat 15216000 # Total cycles spent in databus access
+system.physmem.totBankLat 58870000 # Total cycles spent in bank access
+system.physmem.avgQLat 3142.56 # Average queueing delay per request
+system.physmem.avgBankLat 15475.81 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 22770.57 # Average memory access latency
-system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 22618.37 # Average memory access latency
+system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 3295 # Number of row buffer hits during reads
+system.physmem.readRowHits 3306 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 19574219.22 # Average gap between requests
+system.physmem.avgGap 19492332.94 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 148490065 # number of cpu cycles simulated
+system.cpu.numCycles 148297707 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 94824011 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 74811084 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 6283419 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 44691419 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 43068728 # Number of BTB hits
+system.cpu.BPredUnit.lookups 94799058 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 74801869 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 6279291 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 44724397 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 43048437 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps
+system.cpu.BPredUnit.usedRAS 4355507 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 88338 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 39650853 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 380235632 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 94799058 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 47403944 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 80363745 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 27281096 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 7190522 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 5914 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 36846162 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1830987 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 148197153 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.802808 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.153253 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8658719 5.84% 69.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6556174 4.42% 73.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6250200 4.21% 77.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8011886 5.40% 83.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 68002614 45.89% 45.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5258973 3.55% 49.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 10529156 7.10% 56.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10279296 6.94% 63.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8665155 5.85% 69.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 6547882 4.42% 73.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 6243481 4.21% 77.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 8012637 5.41% 83.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 24657959 16.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 14343881 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164426 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 392938907 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 736414 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 20843724 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 43027461 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16443523 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 5668310 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3691413 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 329308816 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 54643 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 249531465 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 795533 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 148197153 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.639248 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.564002 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 45504222 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5859124 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 74799977 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1201103 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 20832727 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 14326960 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 164415 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 392837219 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 734618 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 20832727 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 50888432 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 722612 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 592441 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 70554465 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4606476 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 371355589 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 339881 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3653545 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 631848996 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1581867929 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1564559444 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 17308485 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 333804857 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 25175 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25171 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13001756 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 43004891 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16418786 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5685881 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3634471 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 329217927 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 47188 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 249444233 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 790071 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 139538270 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 362161071 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1972 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 148197153 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.683192 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.761683 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12554169 8.46% 92.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6514357 4.39% 96.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4035019 2.72% 99.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1109043 0.75% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56041941 37.82% 37.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 22617532 15.26% 53.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 24819018 16.75% 69.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 20330052 13.72% 83.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12543560 8.46% 92.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 6522981 4.40% 96.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4027974 2.72% 99.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1111240 0.75% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 182855 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 148197153 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1162967 46.43% 85.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 373557 14.91% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 964308 38.46% 38.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5601 0.22% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1163168 46.39% 85.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 374037 14.92% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 194943196 78.12% 78.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 980225 0.39% 78.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 194888705 78.13% 78.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 979440 0.39% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33090 0.01% 78.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 164479 0.07% 78.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 254525 0.10% 78.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76418 0.03% 78.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 465710 0.19% 78.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 206458 0.08% 79.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 38372441 15.38% 94.40% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 13962748 5.60% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 33084 0.01% 78.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 164341 0.07% 78.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 254530 0.10% 78.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 76430 0.03% 78.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 465703 0.19% 78.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 38355599 15.38% 94.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 13947826 5.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 249531465 # Type of FU issued
-system.cpu.iq.rate 1.680459 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2189794 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1841578 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 250160112 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1876275 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2013222 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 249444233 # Type of FU issued
+system.cpu.iq.rate 1.682051 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2507262 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010051 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 646645921 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 466634028 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 237875698 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3737031 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2187759 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1841461 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 250076224 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1875271 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2007740 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 13171893 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11381 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18785 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3792805 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 13155407 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11336 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18867 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3774152 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 96 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 95 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 20843724 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 209 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18785 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3890771 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3762289 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7653060 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 243027736 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 36864796 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6503729 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 20832727 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 16956 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 865 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 329282292 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 783571 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 43004891 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16418786 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 24780 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 273 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18867 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3889474 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3759056 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 7648530 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 242951850 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 36852953 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 6492383 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 16968 # number of nop insts executed
-system.cpu.iew.exec_refs 50523279 # number of memory reference insts executed
-system.cpu.iew.exec_branches 53444477 # Number of branches executed
-system.cpu.iew.exec_stores 13658483 # Number of stores executed
-system.cpu.iew.exec_rate 1.636660 # Inst execution rate
-system.cpu.iew.wb_sent 240848315 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 239789364 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 148488630 # num instructions producing a value
-system.cpu.iew.wb_consumers 267300896 # num instructions consuming a value
+system.cpu.iew.exec_nop 17177 # number of nop insts executed
+system.cpu.iew.exec_refs 50499895 # number of memory reference insts executed
+system.cpu.iew.exec_branches 53421871 # Number of branches executed
+system.cpu.iew.exec_stores 13646942 # Number of stores executed
+system.cpu.iew.exec_rate 1.638271 # Inst execution rate
+system.cpu.iew.wb_sent 240774594 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 239717159 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 148465347 # num instructions producing a value
+system.cpu.iew.wb_consumers 267264848 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.614851 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.555511 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.616459 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.555499 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 140679091 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 51300 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6130085 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 127544650 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.479492 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.184685 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 140611386 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 6125994 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 127364426 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.481347 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.186226 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 57798190 45.32% 45.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 31737959 24.88% 70.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13785979 10.81% 81.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 7635406 5.99% 87.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4383857 3.44% 90.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1319533 1.03% 91.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1705049 1.34% 92.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1307627 1.03% 93.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7871050 6.17% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 57685030 45.29% 45.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 31666758 24.86% 70.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13788542 10.83% 80.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 7634444 5.99% 86.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4378206 3.44% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1321179 1.04% 91.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1702157 1.34% 92.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1312824 1.03% 93.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 7875286 6.18% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 127544650 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 172347829 # Number of instructions committed
-system.cpu.commit.committedOps 188701311 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 127364426 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 172317409 # Number of instructions committed
+system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 42506286 # Number of memory references committed
-system.cpu.commit.loads 29855568 # Number of loads committed
+system.cpu.commit.refs 42494118 # Number of memory references committed
+system.cpu.commit.loads 29849484 # Number of loads committed
system.cpu.commit.membars 22408 # Number of memory barriers committed
-system.cpu.commit.branches 40306395 # Number of branches committed
+system.cpu.commit.branches 40300311 # Number of branches committed
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 150130553 # Number of committed integer instructions.
+system.cpu.commit.int_insts 150106217 # Number of committed integer instructions.
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 7871050 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 7875286 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 449048801 # The number of ROB reads
-system.cpu.rob.rob_writes 679713725 # The number of ROB writes
-system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 172333441 # Number of Instructions Simulated
-system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated
-system.cpu.cpi 0.861644 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.861644 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.160572 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.160572 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1079711901 # number of integer regfile reads
-system.cpu.int_regfile_writes 384939818 # number of integer regfile writes
-system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes
-system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads
-system.cpu.misc_regfile_writes 832204 # number of misc regfile writes
-system.cpu.icache.replacements 2508 # number of replacements
-system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use
-system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 448766216 # The number of ROB reads
+system.cpu.rob.rob_writes 679506166 # The number of ROB writes
+system.cpu.timesIdled 2556 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 100554 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 172303021 # Number of Instructions Simulated
+system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated
+system.cpu.cpi 0.860680 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.860680 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.161872 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.161872 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1079384127 # number of integer regfile reads
+system.cpu.int_regfile_writes 384869699 # number of integer regfile writes
+system.cpu.fp_regfile_reads 2912697 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2497246 # number of floating regfile writes
+system.cpu.misc_regfile_reads 54493639 # number of misc regfile reads
+system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
+system.cpu.icache.replacements 2375 # number of replacements
+system.cpu.icache.tagsinuse 1350.215949 # Cycle average of tags in use
+system.cpu.icache.total_refs 36840897 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 4105 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 8974.639951 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 36854521 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 36854521 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits
-system.cpu.icache.overall_hits::total 36854521 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5340 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5340 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5340 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5340 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5340 # number of overall misses
-system.cpu.icache.overall_misses::total 5340 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 158697499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 158697499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 158697499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 158697499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 158697499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 158697499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 36859861 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 36859861 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 36859861 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 36859861 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 36859861 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 36859861 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1350.215949 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.659285 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.659285 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 36840897 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 36840897 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 36840897 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 36840897 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 36840897 # number of overall hits
+system.cpu.icache.overall_hits::total 36840897 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 5265 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 5265 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 5265 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 5265 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 5265 # number of overall misses
+system.cpu.icache.overall_misses::total 5265 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 158318499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 158318499 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 158318499 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 158318499 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 158318499 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 158318499 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 36846162 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 36846162 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 36846162 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 36846162 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 36846162 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 36846162 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30069.990313 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 30069.990313 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 30069.990313 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 30069.990313 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30069.990313 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 30069.990313 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 679 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 37.722222 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1103 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1103 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1103 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1103 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1103 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1103 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 4237 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 4237 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 4237 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122742499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 122742499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122742499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 122742499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122742499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 122742499 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000115 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000115 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000115 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28969.199670 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28969.199670 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1159 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1159 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1159 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1159 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1159 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4106 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 4106 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 4106 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 4106 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 4106 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 4106 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121527999 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 121527999 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121527999 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 121527999 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121527999 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 121527999 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29597.661715 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29597.661715 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29597.661715 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 29597.661715 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29597.661715 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 29597.661715 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 1961.084990 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 1964.083296 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2132 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2732 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.780381 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1424.044661 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 533.017333 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.059848 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 2184 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2274 # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::writebacks 4.995038 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1428.113595 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 530.974663 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.043583 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.016204 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.059939 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 2043 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2131 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 2184 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 98 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2282 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 2184 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 98 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2282 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 2051 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 681 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 2732 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2051 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 3807 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2051 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses
-system.cpu.l2cache.overall_misses::total 3807 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35089000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 131742500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 81286000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 177939500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 81286000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 177939500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 2043 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2140 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 2043 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2140 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 677 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 2740 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2063 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1757 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 3820 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2063 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1757 # number of overall misses
+system.cpu.l2cache.overall_misses::total 3820 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96979500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34478500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 131458000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46382000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 46382000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 96979500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 80860500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 177840000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 96979500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 80860500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 177840000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 4106 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 765 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 4871 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 4235 # number of demand (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1089 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1089 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 4106 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1854 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 6089 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 4235 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 5960 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 4106 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1854 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 6089 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.484298 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.883268 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.545745 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484298 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.947141 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.625226 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484298 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51525.697504 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.998536 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 46740.084056 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 46740.084056 # average overall miss latency
+system.cpu.l2cache.overall_accesses::total 5960 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.502435 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.884967 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.562513 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.502435 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.947681 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.640940 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.502435 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.947681 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.640940 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47008.967523 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50928.360414 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 47977.372263 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42946.296296 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42946.296296 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47008.967523 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46021.912351 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 46554.973822 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47008.967523 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46021.912351 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 46554.973822 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2048 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 670 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 2718 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2048 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 3793 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70388399 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26267459 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96655858 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70388399 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58983617 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 129372016 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70388399 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58983617 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 129372016 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.622927 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34369.335449 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2058 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 666 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2724 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2058 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1746 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3804 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2058 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1746 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3804 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70489427 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25721458 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96210885 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32841183 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32841183 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70489427 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58562641 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 129052068 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70489427 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58562641 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 129052068 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870588 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559228 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941748 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.638255 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941748 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.638255 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34251.422255 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38620.807808 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35319.708150 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30408.502778 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30408.502778 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34251.422255 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33541.031501 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33925.359621 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34251.422255 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33541.031501 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33925.359621 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 57 # number of replacements
-system.cpu.dcache.tagsinuse 1406.445410 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
+system.cpu.dcache.replacements 58 # number of replacements
+system.cpu.dcache.tagsinuse 1406.419520 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46792514 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 25238.680690 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
-system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
+system.cpu.dcache.occ_blocks::cpu.data 1406.419520 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.343364 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.343364 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 34391106 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 34391106 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12356535 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12356535 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 22466 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 22466 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 46747641 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 46747641 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 46747641 # number of overall hits
+system.cpu.dcache.overall_hits::total 46747641 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1904 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1904 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
-system.cpu.dcache.overall_misses::total 9552 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 82599500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 82599500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 9656 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9656 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9656 # number of overall misses
+system.cpu.dcache.overall_misses::total 9656 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 84169500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 84169500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 293859496 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 293859496 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 375319996 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 378028996 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 378028996 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 378028996 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 378028996 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 34393010 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 34393010 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22468 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 22468 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46757297 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46757297 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46757297 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46757297 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44206.670168 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 44206.670168 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37907.571723 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37907.571723 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39149.647473 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39149.647473 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 472 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 34 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.307692 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
system.cpu.dcache.writebacks::total 18 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1138 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1138 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6664 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6664 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 7802 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7802 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7802 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7802 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 766 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1088 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1088 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1854 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1854 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1854 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1854 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36187000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 36187000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47523998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 47523998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83710998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 83710998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83710998 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 83710998 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47241.514360 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47241.514360 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43680.145221 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43680.145221 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.082648 # Number of seconds simulated
-sim_ticks 82648140000 # Number of ticks simulated
-final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.082776 # Number of seconds simulated
+sim_ticks 82776043000 # Number of ticks simulated
+final_tick 82776043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 31465 # Simulator instruction rate (inst/s)
-host_op_rate 52738 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19690094 # Simulator tick rate (ticks/s)
-host_mem_usage 268216 # Number of bytes of host memory used
-host_seconds 4197.45 # Real time elapsed on the host
+host_inst_rate 77695 # Simulator instruction rate (inst/s)
+host_op_rate 130224 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48695604 # Simulator tick rate (ticks/s)
+host_mem_usage 276624 # Number of bytes of host memory used
+host_seconds 1699.87 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory
-system.physmem.bytes_read::total 342144 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1944 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5346 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2634397 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1505370 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4139766 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2634397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2634397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2634397 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1505370 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4139766 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5348 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 124288 # Number of bytes read from this memory
+system.physmem.bytes_read::total 342272 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1942 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5348 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2633419 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1501497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4134916 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2633419 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2633419 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2633419 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1501497 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4134916 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5350 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 5502 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 342144 # Total number of bytes read from memory
+system.physmem.cpureqs 5531 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 342272 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 342144 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 342272 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 181 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 308 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 315 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 307 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 328 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 327 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 305 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 257 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 436 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 435 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 295 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 297 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 82648109000 # Total gap between requests
+system.physmem.totGap 82776014000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 5348 # Categorize read packet sizes
+system.physmem.readPktSize::6 5350 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 154 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 181 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 4185 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4186 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 931 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 16873822 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests
-system.physmem.totBusLat 21392000 # Total cycles spent in databus access
-system.physmem.totBankLat 84182000 # Total cycles spent in bank access
-system.physmem.avgQLat 3155.16 # Average queueing delay per request
-system.physmem.avgBankLat 15740.84 # Average bank access latency per request
+system.physmem.totQLat 13963836 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 119601836 # Sum of mem lat for all requests
+system.physmem.totBusLat 21400000 # Total cycles spent in databus access
+system.physmem.totBankLat 84238000 # Total cycles spent in bank access
+system.physmem.avgQLat 2610.06 # Average queueing delay per request
+system.physmem.avgBankLat 15745.42 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 22896.00 # Average memory access latency
-system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 22355.48 # Average memory access latency
+system.physmem.avgRdBW 4.13 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 4.13 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 4742 # Number of row buffer hits during reads
+system.physmem.readRowHits 4744 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 15454021.88 # Average gap between requests
+system.physmem.avgGap 15472152.15 # Average gap between requests
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 165296281 # number of cpu cycles simulated
+system.cpu.numCycles 165552087 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits
+system.cpu.BPredUnit.lookups 19937507 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 19937507 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 2011224 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 13844585 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 13082184 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 25823167 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 218797366 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 19937507 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 13082184 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 57543253 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 17618129 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 66723129 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2032 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 86 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 24434096 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 426892 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 165432321 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.185723 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.325531 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3450171 2.09% 73.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3573015 2.16% 75.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4309284 2.61% 78.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2725915 1.65% 79.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 33580712 20.33% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 109484552 66.18% 66.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3053467 1.85% 68.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2384541 1.44% 69.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2897248 1.75% 71.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3448185 2.08% 73.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 3564782 2.15% 75.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4309445 2.60% 78.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2719256 1.64% 79.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 33570845 20.29% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 165175969 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.120712 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.324235 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38701150 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 56465114 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 44698220 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9957565 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 15353920 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 353610105 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 15353920 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 46165738 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 14909579 # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total 165432321 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.120430 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.321623 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 38724148 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 56736512 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 44639960 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9991325 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 15340376 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 353466965 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 15340376 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 46189093 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 15008557 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 23078 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 46524421 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 42199233 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 345243747 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 88 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 17893684 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 22177130 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 398936501 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 960723880 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 950976963 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9746917 # Number of floating rename lookups
+system.cpu.rename.RunCycles 46492003 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 42379214 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 345094521 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 18065019 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 22190556 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 104 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 398767810 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 960056051 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 950296029 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 9760022 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 139507897 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 139339206 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1674 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1664 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 90390787 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 86672801 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 31756377 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 57758664 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 18775058 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 333623093 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3362 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 267451276 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 258403 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 111810012 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 230098900 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2117 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 165175969 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.619190 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.505359 # Number of insts issued each cycle
+system.cpu.rename.tempSerializingInsts 1663 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 90597841 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 86592813 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 31744520 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 57837693 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 18834679 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 333487648 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3580 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 267379172 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 250437 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 111676069 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 229742853 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2335 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 165432321 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.616245 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.503217 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 44964626 27.22% 27.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 46539597 28.18% 55.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 32801785 19.86% 75.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 19824720 12.00% 87.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 13230335 8.01% 95.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4791341 2.90% 98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2351721 1.42% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 529174 0.32% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 142670 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 45038788 27.22% 27.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 46767309 28.27% 55.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 32846173 19.85% 75.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 19795888 11.97% 87.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 13207626 7.98% 95.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4774334 2.89% 98.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2327149 1.41% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 533647 0.32% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 141407 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 165175969 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 165432321 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 137826 5.20% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2250902 84.86% 90.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 263908 9.95% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 133618 5.04% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2250761 84.95% 90.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 265061 10.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1212134 0.45% 0.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 174151286 65.12% 65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1593879 0.60% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 67229168 25.14% 91.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 23264809 8.70% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 174135882 65.13% 65.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1593779 0.60% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 67177367 25.12% 91.30% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 23260010 8.70% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 267451276 # Type of FU issued
-system.cpu.iq.rate 1.618011 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2652636 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.009918 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 697648502 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 441157156 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 260237459 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 5341058 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 4570848 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2570585 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 266205797 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2685981 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 19039823 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 267379172 # Type of FU issued
+system.cpu.iq.rate 1.615076 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2649440 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.009909 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 697750591 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 440878444 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 260170034 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 5339951 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 4579505 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 2570780 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 266131077 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2685401 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 19003165 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 30023215 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 29490 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 296813 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 11240660 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 29943227 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 28980 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 295958 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11228803 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 49425 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 49224 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 15353920 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 582358 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 260686 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 333626455 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 190123 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 86672801 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 31756377 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1654 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 146774 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 31153 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 296813 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1177159 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 916050 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2093209 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 264577691 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 66245889 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2873585 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 15340376 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 584172 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 263019 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 333491228 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 190803 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 86592813 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 31744520 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1661 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 148723 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 30980 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 295958 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1176359 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 917156 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2093515 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 264503897 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 66194002 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2875275 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 89117815 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14597039 # Number of branches executed
-system.cpu.iew.exec_stores 22871926 # Number of stores executed
-system.cpu.iew.exec_rate 1.600627 # Inst execution rate
-system.cpu.iew.wb_sent 263630467 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 262808044 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 212084858 # num instructions producing a value
-system.cpu.iew.wb_consumers 375096623 # num instructions consuming a value
+system.cpu.iew.exec_refs 89062868 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14601707 # Number of branches executed
+system.cpu.iew.exec_stores 22868866 # Number of stores executed
+system.cpu.iew.exec_rate 1.597708 # Inst execution rate
+system.cpu.iew.wb_sent 263570746 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 262740814 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 211979430 # num instructions producing a value
+system.cpu.iew.wb_consumers 374947027 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.589921 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.565414 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.587058 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.565358 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 112301239 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 112163051 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2011502 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149822049 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.477506 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.946000 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2011438 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 150091945 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.474849 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.942132 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 50722618 33.86% 33.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57116806 38.12% 71.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13820755 9.22% 81.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 12019830 8.02% 89.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4145175 2.77% 91.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2956577 1.97% 93.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1072909 0.72% 94.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 994916 0.66% 95.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6972463 4.65% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 50831007 33.87% 33.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57256127 38.15% 72.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13834026 9.22% 81.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12065346 8.04% 89.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4152706 2.77% 92.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2955841 1.97% 94.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1060436 0.71% 94.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1001549 0.67% 95.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6934907 4.62% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149822049 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 150091945 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221362961 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339551 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6972463 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6934907 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 476513786 # The number of ROB reads
-system.cpu.rob.rob_writes 682717187 # The number of ROB writes
-system.cpu.timesIdled 2881 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 120312 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 476683050 # The number of ROB reads
+system.cpu.rob.rob_writes 682427429 # The number of ROB writes
+system.cpu.timesIdled 2933 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 119766 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221362961 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
-system.cpu.cpi 1.251570 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.251570 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.798997 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.798997 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 562635091 # number of integer regfile reads
-system.cpu.int_regfile_writes 298739906 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3520410 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2230055 # number of floating regfile writes
-system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads
+system.cpu.cpi 1.253506 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.253506 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.797762 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.797762 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 562448945 # number of integer regfile reads
+system.cpu.int_regfile_writes 298656184 # number of integer regfile writes
+system.cpu.fp_regfile_reads 3520617 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2230281 # number of floating regfile writes
+system.cpu.misc_regfile_reads 136958061 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
-system.cpu.icache.replacements 4732 # number of replacements
-system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use
-system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks.
+system.cpu.icache.replacements 4787 # number of replacements
+system.cpu.icache.tagsinuse 1623.671048 # Cycle average of tags in use
+system.cpu.icache.total_refs 24425061 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 6754 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 3616.384513 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 24437101 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 24437101 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits
-system.cpu.icache.overall_hits::total 24437101 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses
-system.cpu.icache.overall_misses::total 8952 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1623.671048 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.792808 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.792808 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 24425061 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 24425061 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 24425061 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 24425061 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 24425061 # number of overall hits
+system.cpu.icache.overall_hits::total 24425061 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 9035 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 9035 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 9035 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 9035 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 9035 # number of overall misses
+system.cpu.icache.overall_misses::total 9035 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 258546498 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 258546498 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 258546498 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 258546498 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 258546498 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 258546498 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 24434096 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 24434096 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 24434096 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 24434096 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 24434096 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 24434096 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000370 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000370 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000370 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000370 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000370 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000370 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28616.103818 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28616.103818 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28616.103818 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28616.103818 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28616.103818 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28616.103818 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 770 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2099 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2099 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2099 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2099 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2099 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2099 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6936 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 6936 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 6936 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 6936 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 6936 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 6936 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197636498 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 197636498 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197636498 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 197636498 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197636498 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 197636498 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000284 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000284 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000284 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28494.304787 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28494.304787 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28494.304787 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 28494.304787 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28494.304787 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 28494.304787 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 2509.913640 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3332 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2513.899297 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3380 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3793 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.891115 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.076596 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 3299 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 3329 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks 1.852274 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2239.000678 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 273.046345 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.000057 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.068329 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.008333 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.076718 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 3349 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 28 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 3377 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 3299 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 37 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 3336 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 3299 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 37 # number of overall hits
-system.cpu.l2cache.overall_hits::total 3336 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3402 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 386 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 3788 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 154 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 154 # number of UpgradeReq misses
+system.cpu.l2cache.demand_hits::cpu.inst 3349 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 35 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 3384 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 3349 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 35 # number of overall hits
+system.cpu.l2cache.overall_hits::total 3384 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3406 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 384 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 3790 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 181 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 181 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1560 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1560 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3402 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1946 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 5348 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1946 # number of overall misses
-system.cpu.l2cache.overall_misses::total 5348 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158304000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 179981000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68234000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 68234000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 158304000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 89911000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 248215000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 158304000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 89911000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 248215000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 6701 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 416 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7117 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 154 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 154 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst 3406 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1944 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 5350 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3406 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1944 # number of overall misses
+system.cpu.l2cache.overall_misses::total 5350 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 157031500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20920500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 177952000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67559500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 67559500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 157031500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 88480000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 245511500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 157031500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 88480000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 245511500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 6755 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 412 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7167 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 181 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 181 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1567 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1567 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 6701 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1983 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 8684 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 6701 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1983 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 8684 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.507685 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927885 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.532247 # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 6755 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1979 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 8734 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 6755 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1979 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 8734 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.504219 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.932039 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.528813 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995533 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.995533 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.507685 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.981341 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.615845 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.507685 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.981341 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.615845 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.627866 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56158.031088 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.463569 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43739.743590 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43739.743590 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.504219 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.982314 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.612549 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.504219 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.982314 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.612549 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46104.374633 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54480.468750 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 46953.034301 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43307.371795 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43307.371795 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46104.374633 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 45514.403292 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 45890 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46104.374633 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 45514.403292 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 45890 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3402 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 386 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 3788 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 154 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 154 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3406 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 384 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3790 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 181 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 181 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1560 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1560 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3402 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1946 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 5348 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1946 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 5348 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532247 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3406 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1944 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5350 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3406 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1944 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 5350 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 114067502 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16106596 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 130174098 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1810181 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1810181 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 47662994 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 47662994 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114067502 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63769590 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 177837092 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114067502 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63769590 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 177837092 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.504219 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.528813 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995533 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995533 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.615845 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.615845 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.748089 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.504219 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.982314 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.612549 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.504219 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.982314 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.612549 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33490.165003 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41944.260417 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34346.727704 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30553.201282 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30553.201282 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33490.165003 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32803.287037 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33240.577944 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33490.165003 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32803.287037 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33240.577944 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 55 # number of replacements
-system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use
-system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 54 # number of replacements
+system.cpu.dcache.tagsinuse 1408.542073 # Cycle average of tags in use
+system.cpu.dcache.total_refs 67546144 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1977 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34165.980779 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits
-system.cpu.dcache.overall_hits::total 67560798 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses
-system.cpu.dcache.overall_misses::total 2513 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data 1408.542073 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.343882 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.343882 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 47031922 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 47031922 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20513982 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20513982 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 67545904 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 67545904 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 67545904 # number of overall hits
+system.cpu.dcache.overall_hits::total 67545904 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 820 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 820 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1749 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1749 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2569 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2569 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2569 # number of overall misses
+system.cpu.dcache.overall_misses::total 2569 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 36866000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 36866000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 76858000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 76858000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 113724000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 113724000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 113724000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 113724000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 47032742 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 47032742 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 67548473 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 67548473 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 67548473 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 67548473 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44958.536585 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 44958.536585 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43943.967982 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43943.967982 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 44267.808486 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 44267.808486 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 44267.808486 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 44267.808486 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 14 # number of writebacks
-system.cpu.dcache.writebacks::total 14 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
+system.cpu.dcache.writebacks::total 13 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 407 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 407 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 409 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 409 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 409 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 409 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1747 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1747 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2160 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2160 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2160 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2160 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21692000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21692000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73250500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 73250500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 94942500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 94942500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 94942500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 94942500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000085 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000085 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52523.002421 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52523.002421 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41929.307384 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41929.307384 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43954.861111 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43954.861111 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43954.861111 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 43954.861111 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13372000 # Number of ticks simulated
-final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13354000 # Number of ticks simulated
+final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 16216 # Simulator instruction rate (inst/s)
-host_op_rate 20228 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47166036 # Simulator tick rate (ticks/s)
-host_mem_usage 230800 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
-sim_insts 4596 # Number of instructions simulated
-sim_ops 5734 # Number of ops (including micro ops) simulated
+host_inst_rate 46154 # Simulator instruction rate (inst/s)
+host_op_rate 57584 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 134203003 # Simulator tick rate (ticks/s)
+host_mem_usage 242404 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+sim_insts 4591 # Number of instructions simulated
+sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13314500 # Total gap between requests
+system.physmem.totGap 13296500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.avgBankLat 16558.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26804.30 # Average memory access latency
-system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s
+system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 11.79 # Data bus utilization in percentage
+system.physmem.busUtil 11.80 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.79 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 319 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 33793.15 # Average gap between requests
+system.physmem.avgGap 33747.46 # Average gap between requests
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
system.cpu.checker.itb.misses 0 # DTB misses
system.cpu.checker.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.checker.numCycles 5747 # number of cpu cycles simulated
+system.cpu.checker.numCycles 5742 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 26745 # number of cpu cycles simulated
+system.cpu.numCycles 26709 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2505 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2501 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1795 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 1976 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 702 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS 292 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
+system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2444 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch
+system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2247 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads.
+system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
-system.cpu.iq.rate 0.336063 # Inst issue rate
+system.cpu.iq.rate 0.336516 # Inst issue rate
system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions
+system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1446 # Number of branches executed
-system.cpu.iew.exec_stores 1164 # Number of stores executed
-system.cpu.iew.exec_rate 0.320209 # Inst execution rate
-system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8109 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3899 # num instructions producing a value
-system.cpu.iew.wb_consumers 7837 # num instructions consuming a value
+system.cpu.iew.exec_refs 3303 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1443 # Number of branches executed
+system.cpu.iew.exec_stores 1167 # Number of stores executed
+system.cpu.iew.exec_rate 0.320604 # Inst execution rate
+system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8105 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3904 # num instructions producing a value
+system.cpu.iew.wb_consumers 7842 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 4596 # Number of instructions committed
-system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 4591 # Number of instructions committed
+system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 2140 # Number of memory references committed
-system.cpu.commit.loads 1201 # Number of loads committed
+system.cpu.commit.refs 2138 # Number of memory references committed
+system.cpu.commit.loads 1200 # Number of loads committed
system.cpu.commit.membars 12 # Number of memory barriers committed
-system.cpu.commit.branches 1008 # Number of branches committed
+system.cpu.commit.branches 1007 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
+system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 22988 # The number of ROB reads
-system.cpu.rob.rob_writes 23599 # The number of ROB writes
+system.cpu.rob.rob_reads 22955 # The number of ROB reads
+system.cpu.rob.rob_writes 23605 # The number of ROB writes
system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 4596 # Number of Instructions Simulated
-system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
-system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39369 # number of integer regfile reads
-system.cpu.int_regfile_writes 8027 # number of integer regfile writes
+system.cpu.committedInsts 4591 # Number of Instructions Simulated
+system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
+system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39368 # number of integer regfile reads
+system.cpu.int_regfile_writes 8018 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
-system.cpu.misc_regfile_writes 26 # number of misc regfile writes
-system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use
-system.cpu.icache.total_refs 1601 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 2982 # number of misc regfile reads
+system.cpu.misc_regfile_writes 24 # number of misc regfile writes
+system.cpu.icache.replacements 3 # number of replacements
+system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use
+system.cpu.icache.total_refs 1597 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
-system.cpu.icache.overall_hits::total 1601 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
-system.cpu.icache.overall_misses::total 360 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits
+system.cpu.icache.overall_hits::total 1597 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
+system.cpu.icache.overall_misses::total 359 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
+system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
+system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
-system.cpu.l2cache.overall_hits::total 40 # number of overall hits
+system.cpu.l2cache.overall_hits::total 39 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.934708 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.901763 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits
-system.cpu.dcache.overall_hits::total 2371 # number of overall hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
+system.cpu.dcache.overall_hits::total 2373 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13372000 # Number of ticks simulated
-final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13354000 # Number of ticks simulated
+final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 20879 # Simulator instruction rate (inst/s)
-host_op_rate 26045 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 60729168 # Simulator tick rate (ticks/s)
-host_mem_usage 230484 # Number of bytes of host memory used
-host_seconds 0.22 # Real time elapsed on the host
-sim_insts 4596 # Number of instructions simulated
-sim_ops 5734 # Number of ops (including micro ops) simulated
+host_inst_rate 53438 # Simulator instruction rate (inst/s)
+host_op_rate 66670 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 155374810 # Simulator tick rate (ticks/s)
+host_mem_usage 242400 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+sim_insts 4591 # Number of instructions simulated
+sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13314500 # Total gap between requests
+system.physmem.totGap 13296500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.avgBankLat 16558.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26804.30 # Average memory access latency
-system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s
+system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 11.79 # Data bus utilization in percentage
+system.physmem.busUtil 11.80 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.79 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 319 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 33793.15 # Average gap between requests
+system.physmem.avgGap 33747.46 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 26745 # number of cpu cycles simulated
+system.cpu.numCycles 26709 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2505 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2501 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1795 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 1976 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 702 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS 292 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
+system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2444 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch
+system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle
+system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2247 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads.
+system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
-system.cpu.iq.rate 0.336063 # Inst issue rate
+system.cpu.iq.rate 0.336516 # Inst issue rate
system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions
+system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1446 # Number of branches executed
-system.cpu.iew.exec_stores 1164 # Number of stores executed
-system.cpu.iew.exec_rate 0.320209 # Inst execution rate
-system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8109 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3899 # num instructions producing a value
-system.cpu.iew.wb_consumers 7837 # num instructions consuming a value
+system.cpu.iew.exec_refs 3303 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1443 # Number of branches executed
+system.cpu.iew.exec_stores 1167 # Number of stores executed
+system.cpu.iew.exec_rate 0.320604 # Inst execution rate
+system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8105 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3904 # num instructions producing a value
+system.cpu.iew.wb_consumers 7842 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 4596 # Number of instructions committed
-system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 4591 # Number of instructions committed
+system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 2140 # Number of memory references committed
-system.cpu.commit.loads 1201 # Number of loads committed
+system.cpu.commit.refs 2138 # Number of memory references committed
+system.cpu.commit.loads 1200 # Number of loads committed
system.cpu.commit.membars 12 # Number of memory barriers committed
-system.cpu.commit.branches 1008 # Number of branches committed
+system.cpu.commit.branches 1007 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
+system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 22988 # The number of ROB reads
-system.cpu.rob.rob_writes 23599 # The number of ROB writes
+system.cpu.rob.rob_reads 22955 # The number of ROB reads
+system.cpu.rob.rob_writes 23605 # The number of ROB writes
system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 4596 # Number of Instructions Simulated
-system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
-system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39369 # number of integer regfile reads
-system.cpu.int_regfile_writes 8027 # number of integer regfile writes
+system.cpu.committedInsts 4591 # Number of Instructions Simulated
+system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
+system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39368 # number of integer regfile reads
+system.cpu.int_regfile_writes 8018 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
-system.cpu.misc_regfile_writes 26 # number of misc regfile writes
-system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use
-system.cpu.icache.total_refs 1601 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 2982 # number of misc regfile reads
+system.cpu.misc_regfile_writes 24 # number of misc regfile writes
+system.cpu.icache.replacements 3 # number of replacements
+system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use
+system.cpu.icache.total_refs 1597 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
-system.cpu.icache.overall_hits::total 1601 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
-system.cpu.icache.overall_misses::total 360 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits
+system.cpu.icache.overall_hits::total 1597 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
+system.cpu.icache.overall_misses::total 359 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
+system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
+system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
-system.cpu.l2cache.overall_hits::total 40 # number of overall hits
+system.cpu.l2cache.overall_hits::total 39 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.934708 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.901763 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits
-system.cpu.dcache.overall_hits::total 2371 # number of overall hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
+system.cpu.dcache.overall_hits::total 2373 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
projects / gem5.git / commitdiff