Added blackbox $__COUNT_ cell model

diff --git a/techlibs/greenpak4/Makefile.inc b/techlibs/greenpak4/Makefile.inc
index 9c3efcb8d610a35f2ab2aa9c14530d6641d6346d..b43fb7511f87fc30659f7a0236ca673510e042cb 100644 (file)
--- a/techlibs/greenpak4/Makefile.inc
+++ b/techlibs/greenpak4/Makefile.inc
@@ -2,6 +2,7 @@
 OBJS += techlibs/greenpak4/synth_greenpak4.o
 OBJS += techlibs/greenpak4/greenpak4_dffinv.o
 
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_blackbox.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))

diff --git a/techlibs/greenpak4/cells_blackbox.v b/techlibs/greenpak4/cells_blackbox.v
new file mode 100644 (file)
index 0000000..8dd38a0
--- /dev/null
+++ b/techlibs/greenpak4/cells_blackbox.v
@@ -0,0 +1,17 @@
+module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
+
+       input wire CE;
+       input wire CLK;
+       output reg OUT;
+       output reg[WIDTH-1:0] POUT;
+       input wire RST;
+       input wire UP;
+
+       parameter COUNT_TO = 1;
+       parameter RESET_MODE = "RISING";
+       parameter HAS_POUT = 0;
+       parameter HAS_CE = 0;
+       parameter WIDTH = 8;
+       parameter DIRECTION = "DOWN";
+
+endmodule