examples: demonstrate multi-clock support

diff --git a/examples/basic/memory.py b/examples/basic/memory.py
index ec61c83a981431b1a18fa97aa491721f4bee7857..30d0430cce3e4fe9c714c42109ce9774b65ddac6 100644 (file)
--- a/examples/basic/memory.py
+++ b/examples/basic/memory.py
@@ -15,7 +15,7 @@ p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
 a2 = Signal(BV(d_b))
 d2 = Signal(BV(w))
 re2 = Signal()
-p2 = MemoryPort(a2, d2, re=re2)
+p2 = MemoryPort(a2, d2, re=re2, clock_domain="rd")
 
 mem = Memory(w, d, p1, p2, init=[5, 18, 32])
 f = Fragment(memories=[mem])

diff --git a/examples/basic/psync.py b/examples/basic/psync.py
new file mode 100644 (file)
index 0000000..4ca25f5
--- /dev/null
+++ b/examples/basic/psync.py
@@ -0,0 +1,23 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog
+
+# convert pulse into level change
+i = Signal()
+level = Signal()
+isync = [If(i, level.eq(~level))]
+
+# synchronize level to oclk domain
+slevel = [Signal() for i in range(3)]
+osync = [
+       slevel[0].eq(level),
+       slevel[1].eq(slevel[0]),
+       slevel[2].eq(slevel[1])
+]
+
+# regenerate pulse
+o = Signal()
+comb = [o.eq(slevel[1] ^ slevel[2])]
+
+f = Fragment(comb, {"i": isync, "o": osync})
+v = verilog.convert(f, ios={i, o})
+print(v)