Revert "dffinit -noreinit to silently continue when init value is 1'bx"

This reverts commit aa081f83c791b1d666214776aaf744a80ce6a690.

diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 37479da6536ab76cf288c62542cabd8ed14544f2..48390488eff98faddc995c4b4f7a43e143bfef41 100644 (file)
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -135,18 +135,10 @@ struct DffinitPass : public Pass {
                                                        continue;
                                                while (GetSize(value.bits) <= i)
                                                        value.bits.push_back(State::S0);
-                                               if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i])) {
-                                                       if (init_bits.at(sig[i]) != State::Sx) {
-                                                               log_error("Trying to assign a different init value for %s.%s.%s which technically "
-                                                                               "have a conflicted init value.\n",
-                                                                               log_id(module), log_id(cell), log_id(it.second));
-                                                       }
-                                                       else {
-                                                               // Trying to overwrite an existing INIT value with 1'bx,
-                                                               //   silently ignore?
-                                                               continue;
-                                                       }
-                                               }
+                                               if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i]))
+                                                       log_error("Trying to assign a different init value for %s.%s.%s which technically "
+                                                                       "have a conflicted init value.\n",
+                                                                       log_id(module), log_id(cell), log_id(it.second));
                                                value.bits[i] = init_bits.at(sig[i]);
                                                cleanup_bits.insert(sig[i]);
                                        }