Added $slice and $concat cell types

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d8160c97b1e01cdcd1dd1e2f02984475a1fcbf64..d7fe4c4e210085675703b64e1a0b4b6df25b9a43 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -571,6 +571,28 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
                return true;
        }
 
+       if (cell->type == "$slice")
+       {
+               fprintf(f, "%s" "assign ", indent.c_str());
+               dump_sigspec(f, cell->connections["\\Y"]);
+               fprintf(f, " = ");
+               dump_sigspec(f, cell->connections["\\A"]);
+               fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int());
+               return true;
+       }
+
+       if (cell->type == "$concat")
+       {
+               fprintf(f, "%s" "assign ", indent.c_str());
+               dump_sigspec(f, cell->connections["\\Y"]);
+               fprintf(f, " = { ");
+               dump_sigspec(f, cell->connections["\\B"]);
+               fprintf(f, " , ");
+               dump_sigspec(f, cell->connections["\\A"]);
+               fprintf(f, " };\n");
+               return true;
+       }
+
        if (cell->type == "$dff" || cell->type == "$adff")
        {
                RTLIL::SigSpec sig_clk, sig_arst, val_arst;

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 9e63e9d1bfe848169e7b8a9e86068f51ef9c16ac..24504aee8175882c9eebcc7a940d86217aee6e74 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -270,6 +270,20 @@ struct CellTypes
 
        static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2)
        {
+               if (cell->type == "$slice") {
+                       RTLIL::Const ret;
+                       int width = cell->parameters.at("\\Y_WIDTH").as_int();
+                       int offset = cell->parameters.at("\\OFFSET").as_int();
+                       ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
+                       return ret;
+               }
+
+               if (cell->type == "$concat") {
+                       RTLIL::Const ret = arg1;
+                       ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
+                       return ret;
+               }
+
                bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
                bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
                int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
@@ -289,10 +303,7 @@ struct CellTypes
                }
 
                assert(sel.bits.size() == 0);
-               bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
-               bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
-               int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
-               return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len);
+               return eval(cell, arg1, arg2);
        }
 };
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 12aa35df36aaf05deae8e557b95fececf4964f77..4c944c93cb32c34414b773d9b9c8e47b08ef4309 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -462,6 +462,24 @@ namespace {
                                return;
                        }
 
+                       if (cell->type == "$slice") {
+                               param("\\OFFSET");
+                               port("\\A", param("\\A_WIDTH"));
+                               port("\\Y", param("\\Y_WIDTH"));
+                               if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
+                                       error(__LINE__);
+                               check_expected();
+                               return;
+                       }
+
+                       if (cell->type == "$concat") {
+                               port("\\A", param("\\A_WIDTH"));
+                               port("\\B", param("\\B_WIDTH"));
+                               port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
+                               check_expected();
+                               return;
+                       }
+
                        if (cell->type == "$mux") {
                                port("\\A", param("\\WIDTH"));
                                port("\\B", param("\\WIDTH"));

diff --git a/kernel/satgen.h b/kernel/satgen.h
index 473aa6166dc6ba38ab5b33bbbe5a8f8819a06564..840700cbd9c9a3835cd1401b9e528f1c9031cb65 100644 (file)
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -761,6 +761,27 @@ struct SatGen
                        return true;
                }
 
+               if (cell->type == "$slice")
+               {
+                       RTLIL::SigSpec a = cell->connections.at("\\A");
+                       RTLIL::SigSpec y = cell->connections.at("\\Y");
+                       ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.width), y, timestep));
+                       return true;
+               }
+
+               if (cell->type == "$concat")
+               {
+                       RTLIL::SigSpec a = cell->connections.at("\\A");
+                       RTLIL::SigSpec b = cell->connections.at("\\B");
+                       RTLIL::SigSpec y = cell->connections.at("\\Y");
+
+                       RTLIL::SigSpec ab = a;
+                       ab.append(b);
+
+                       ez->assume(signals_eq(ab, y, timestep));
+                       return true;
+               }
+
                if (timestep > 0 && (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_"))
                {
                        if (timestep == 1)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index c8c2b6c6c6217c4aaa296c034d84e949ca1fa7eb..e7895521a6d559ab258a927129bb22a6f10b10ff 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -429,3 +429,7 @@ using the {\tt abc} pass.
 Add information about {\tt \$assert} cells.
 \end{fixme}
 
+\begin{fixme}
+Add information about {\tt \$slice} and {\tt \$concat} cells.
+\end{fixme}
+

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index e06a80bbd546add8dec731e4358f422bdaaf52a9..e67b1e055883870f4750a5a256eeb88662dd1a10 100644 (file)
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -312,6 +312,22 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
        }
 }
 
+static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+       int offset = cell->parameters.at("\\OFFSET").as_int();
+       RTLIL::SigSpec sig_a = cell->connections.at("\\A");
+       RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
+       module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.width)));
+}
+
+static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+       RTLIL::SigSpec sig_ab = cell->connections.at("\\A");
+       sig_ab.append(cell->connections.at("\\B"));
+       RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
+       module->connections.push_back(RTLIL::SigSig(sig_y, sig_ab));
+}
+
 static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 {
        int width = cell->parameters.at("\\WIDTH").as_int();
@@ -480,6 +496,8 @@ void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::
        mappers["$logic_and"]   = simplemap_logbin;
        mappers["$logic_or"]    = simplemap_logbin;
        mappers["$mux"]         = simplemap_mux;
+       mappers["$slice"]       = simplemap_slice;
+       mappers["$concat"]      = simplemap_concat;
        mappers["$sr"]          = simplemap_sr;
        mappers["$dff"]         = simplemap_dff;
        mappers["$dffsr"]       = simplemap_dffsr;

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 87e83bd1581f50b74e5f1793b17f423fb5981500..4436abfe73fc832376404167fe8293f41efd7b6a 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -829,6 +829,36 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$slice (A, Y);
+
+parameter OFFSET = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
+
+assign Y = A >> OFFSET;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$concat (A, B, Y);
+
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [A_WIDTH+B_WIDTH-1:0] Y;
+
+assign Y = {B, A};
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$mux (A, B, S, Y);
 
 parameter WIDTH = 0;

diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index e33e651ca52605a38db1a095d46f5f9c083fec05..fdee26b6fad0a5f2723f369de7eb11685941246c 100644 (file)
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -956,6 +956,18 @@ endmodule
 
 // --------------------------------------------------------
 
+(* techmap_simplemap *)
+module \$slice ;
+endmodule
+
+// --------------------------------------------------------
+
+(* techmap_simplemap *)
+module \$concat ;
+endmodule
+
+// --------------------------------------------------------
+
 (* techmap_simplemap *)
 module \$mux ;
 endmodule