import argparse
-from migen import *
+from litex.gen import *
from litex.boards.platforms import de0nano
from litex.soc.cores.sdram.settings import IS42S16160
import argparse
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import kc705
from litex.soc.cores.sdram.settings import MT8JTF12864
import argparse
from fractions import Fraction
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import minispartan6
from litex.soc.cores.sdram.settings import AS4C16M16
import argparse
import importlib
-from migen import *
+from litex.gen import *
from litex.boards.platforms import sim
-from migen.genlib.io import CRG
+from litex.gen.genlib.io import CRG
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
import argparse
import importlib
-from migen import *
-from migen.genlib.io import CRG
+from litex.gen import *
+from litex.gen.genlib.io import CRG
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
-from migen.genlib.io import DifferentialInput, DifferentialOutput
+from litex.gen.fhdl.module import Module
+from litex.gen.fhdl.specials import Instance
+from litex.gen.genlib.io import DifferentialInput, DifferentialOutput
class AlteraDifferentialInputImpl(Module):
import os
import subprocess
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
from litex.build.generic_platform import Pins, IOStandard, Misc
from litex.build import tools
import os
-from migen.fhdl.structure import Signal
-from migen.genlib.record import Record
-from migen.genlib.io import CRG
-from migen.fhdl import verilog, edif
+from litex.gen.fhdl.structure import Signal
+from litex.gen.genlib.record import Record
+from litex.gen.genlib.io import CRG
+from litex.gen.fhdl import verilog, edif
from litex.build import tools
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
-from migen.genlib.io import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen.fhdl.module import Module
+from litex.gen.fhdl.specials import Instance
+from litex.gen.genlib.io import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
class LatticeAsyncResetSynchronizerImpl(Module):
import subprocess
import shutil
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
import os
import subprocess
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
from litex.build import tools
from litex.build.generic_platform import *
import sys
from distutils.version import StrictVersion
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
-from migen.fhdl.specials import SynthesisDirective
-from migen.genlib.cdc import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.io import *
+from litex.gen.fhdl.structure import *
+from litex.gen.fhdl.specials import Instance
+from litex.gen.fhdl.module import Module
+from litex.gen.fhdl.specials import SynthesisDirective
+from litex.gen.genlib.cdc import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen.genlib.io import *
from litex.build import tools
import subprocess
import sys
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.xilinx import common
import subprocess
import sys
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.xilinx import common
elif isinstance(node, Case):
if node.cases:
r = "\t"*level + "case (" + _printexpr(ns, node.test)[0] + ")\n"
- css = sorted([(k, v) for (k, v) in node.cases.items() if k != "default"], key=itemgetter(0))
+ css = [(k, v) for k, v in node.cases.items() if isinstance(k, Constant)]
+ css = sorted(css, key=lambda x: x[0].value)
for choice, statements in css:
r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
r += _printnode(ns, at, level + 2, statements, target_filter)
ns.clock_domains = f.clock_domains
r.ns = ns
- src = "/* Machine-generated using Migen */\n"
+ src = "/* Machine-generated using LiteX gen*/\n"
src += _printheader(f, ios, name, ns,
reg_initialization=not asic_syntax)
src += _printcomb(f, ns,
import os
-from migen import *
+from litex.gen import *
from litex.soc.interconnect import wishbone
import os
-from migen import *
+from litex.gen import *
from litex.soc.interconnect import wishbone
-from migen import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import wishbone
-from migen import *
-from migen.genlib.misc import timeline
+from litex.gen import *
+from litex.gen.genlib.misc import timeline
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus
-from migen import *
-from migen.genlib.cdc import MultiReg
+from litex.gen import *
+from litex.gen.genlib.cdc import MultiReg
from litex.soc.interconnect.csr import *
-from migen import *
+from litex.gen import *
class Identifier(Module):
-from migen import *
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib.record import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.stream import *
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.csr import *
from litex.soc.cores.liteeth_mini.common import *
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.csr import *
from litex.soc.cores.liteeth_mini.common import *
from functools import reduce
from operator import xor
-from migen import *
-from migen.genlib.misc import chooser
+from litex.gen import *
+from litex.gen.genlib.misc import chooser
from litex.soc.interconnect.stream import *
import math
-from migen import *
-from migen.genlib.fsm import *
+from litex.gen import *
+from litex.gen.genlib.fsm import *
from litex.soc.interconnect.stream import Sink, Source
from litex.soc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.stream import *
from litex.soc.cores.liteeth_mini.common import eth_phy_description
import math
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.stream import *
from litex.soc.cores.liteeth_mini.common import eth_phy_description
-from migen import *
-from migen.genlib.fsm import *
-from migen.genlib.misc import chooser
-from migen.genlib.record import Record
+from litex.gen import *
+from litex.gen.genlib.fsm import *
+from litex.gen.genlib.misc import chooser
+from litex.gen.genlib.record import Record
from litex.soc.interconnect.stream import *
from litex.soc.cores.liteeth_mini.common import eth_phy_description, eth_preamble
-from migen import *
-from migen.fhdl.simplify import FullMemoryWE
+from litex.gen import *
+from litex.gen.fhdl.simplify import FullMemoryWE
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
-from migen import *
-from migen.genlib.io import DDROutput
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen import *
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.liteeth_mini.common import *
-from migen import *
-from migen.genlib.io import DDROutput
-from migen.genlib.cdc import PulseSynchronizer
+from litex.gen import *
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.cdc import PulseSynchronizer
from litex.soc.interconnect.stream import *
from litex.soc.cores.liteeth_mini.common import *
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.stream import *
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.stream import *
# RGMII PHY for Spartan-6
-from migen import *
-from migen.genlib.io import DDROutput
-from migen.genlib.misc import WaitTimer
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.misc import WaitTimer
+from litex.gen.genlib.fsm import FSM, NextState
from litex.soc.interconnect.stream import *
from litex.soc.interconnect.csr import *
-from migen import *
+from litex.gen import *
from litex.soc.interconnect import dfi
from litex.soc.interconnect.csr import *
-from migen import *
-from migen.genlib.roundrobin import *
-from migen.genlib.fsm import FSM, NextState
-from migen.genlib.fifo import SyncFIFO
+from litex.gen import *
+from litex.gen.genlib.roundrobin import *
+from litex.gen.genlib.fsm import FSM, NextState
+from litex.gen.genlib.fifo import SyncFIFO
from litex.soc.cores.sdram.lasmicon.multiplexer import *
-from migen import *
+from litex.gen import *
from litex.soc.interconnect import dfi, lasmi_bus
from litex.soc.cores.sdram.lasmicon.refresher import *
from functools import reduce
from operator import or_, and_
-from migen import *
-from migen.genlib.roundrobin import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.roundrobin import *
+from litex.gen.genlib.fsm import FSM, NextState
from litex.soc.cores.sdram.lasmicon.perf import Bandwidth
from litex.soc.interconnect.csr import AutoCSR
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.csr import *
-from migen import *
-from migen.genlib.misc import timeline
-from migen.genlib.fsm import FSM
+from litex.gen import *
+from litex.gen.genlib.misc import timeline
+from litex.gen.genlib.fsm import FSM
from litex.soc.cores.sdram.lasmicon.multiplexer import *
from functools import reduce
from operator import or_
-from migen import *
-from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import WaitTimer
+from litex.gen import *
+from litex.gen.genlib.fsm import FSM, NextState
+from litex.gen.genlib.misc import WaitTimer
from litex.soc.interconnect import dfi as dfibus
from litex.soc.interconnect import wishbone
# TODO:
# - add $display support to LiteX gen and manage timing violations?
-from migen import *
-from migen.fhdl.specials import *
+from litex.gen import *
+from litex.gen.fhdl.specials import *
from litex.soc.interconnect.dfi import *
from functools import reduce
# This PHY only supports CAS Latency 2.
#
-from migen import *
-from migen.genlib.record import *
-from migen.fhdl.specials import Tristate
+from litex.gen import *
+from litex.gen.genlib.record import *
+from litex.gen.fhdl.specials import Tristate
from litex.soc.interconnect.dfi import *
from litex.soc.cores.sdram import settings as sdram_settings
# tCK=5ns CL=7 CWL=6
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.dfi import *
from litex.soc.interconnect.csr import *
from functools import reduce
from operator import or_
-from migen import *
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib.record import *
from litex.soc.interconnect.dfi import *
from litex.soc.cores.sdram import settings as sdram_settings
from math import ceil
from collections import namedtuple
-from migen import *
+from litex.gen import *
PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
from functools import reduce
from operator import xor
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import dma_lasmi
print("{0:032x}".format(selfp.dut.o))
if __name__ == "__main__":
- from migen.fhdl import verilog
- from migen.sim.generic import run_simulation
+ from litex.gen.fhdl import verilog
+ from litex.gen.sim.generic import run_simulation
lfsr = LFSR(3, 4, [3, 2])
print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o}))
-from migen import *
-from migen.bank.description import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.bank.description import *
+from litex.gen.genlib.fsm import FSM, NextState
class SPIMaster(Module, AutoCSR):
-from migen import *
-from migen.genlib.record import *
-from migen.sim.generic import run_simulation
+from litex.gen import *
+from litex.gen.genlib.record import *
+from litex.gen.sim.generic import run_simulation
from litex.soc.com.spi import SPIMaster
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
from litex.soc.cores.uart.core import RS232PHY
-from migen import *
-from migen.genlib.record import Record
-from migen.genlib.cdc import MultiReg
+from litex.gen import *
+from litex.gen.genlib.record import Record
+from litex.gen.genlib.cdc import MultiReg
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
-from migen import *
+from litex.gen import *
from litex.soc.interconnect.csr import CSRStatus
-from migen import log2_int
+from litex.gen import log2_int
def get_sdram_phy_header(sdram_phy_settings):
from operator import itemgetter
-from migen import *
+from litex.gen import *
from litex.soc.cores import identifier, timer, uart
from litex.soc.cores.cpu import lm32, mor1kx
-from migen import *
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib.record import *
from litex.soc.interconnect import wishbone, wishbone2lasmi, lasmi_bus
from litex.soc.interconnect.csr import AutoCSR
# Remove this workaround when fixed by Xilinx.
from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
- from migen.fhdl.simplify import FullMemoryWE
+ from litex.gen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
# Remove this workaround when fixed by Xilinx.
from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
- from migen.fhdl.simplify import FullMemoryWE
+ from litex.gen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
-from migen import *
-from migen.util.misc import xdir
-from migen.fhdl.tracer import get_obj_var_name
+from litex.gen import *
+from litex.gen.util.misc import xdir
+from litex.gen.fhdl.tracer import get_obj_var_name
class _CSRBase(DUID):
-from migen import *
-from migen.genlib.record import *
-from migen.genlib.misc import chooser
-from migen.util.misc import xdir
+from litex.gen import *
+from litex.gen.genlib.record import *
+from litex.gen.genlib.misc import chooser
+from litex.gen.util.misc import xdir
from litex.soc.interconnect import csr
from litex.soc.interconnect.csr import CSRStorage
from functools import reduce
from operator import or_
-from migen import *
-from migen.util.misc import xdir
+from litex.gen import *
+from litex.gen.util.misc import xdir
from litex.soc.interconnect.csr import *
-from migen import *
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib.record import *
def phase_cmd_description(addressbits, bankbits):
-from migen import *
-from migen.genlib.fifo import SyncFIFO
+from litex.gen import *
+from litex.gen.genlib.fifo import SyncFIFO
class Reader(Module):
from functools import reduce
from operator import or_
-from migen import *
-from migen.genlib import roundrobin
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib import roundrobin
+from litex.gen.genlib.record import *
class Interface(Record):
-from migen import *
-from migen.genlib.roundrobin import *
-from migen.genlib.record import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.roundrobin import *
+from litex.gen.genlib.record import *
+from litex.gen.genlib.fsm import FSM, NextState
from litex.soc.interconnect.stream import *
-from migen import *
-from migen.genlib.record import *
-from migen.genlib import fifo
+from litex.gen import *
+from litex.gen.genlib.record import *
+from litex.gen.genlib import fifo
def _make_m2s(layout):
# XXX
from copy import copy
-from migen.util.misc import xdir
+from litex.gen.util.misc import xdir
def pack_layout(l, n):
return [("chunk"+str(i), l) for i in range(n)]
from functools import reduce
from operator import or_
-from migen import *
-from migen.genlib import roundrobin
-from migen.genlib.record import *
-from migen.genlib.misc import split, displacer, chooser
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib import roundrobin
+from litex.gen.genlib.record import *
+from litex.gen.genlib.misc import split, displacer, chooser
+from litex.gen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import csr
-from migen import *
-from migen.genlib.misc import timeline
+from litex.gen import *
+from litex.gen.genlib.misc import timeline
from litex.soc.interconnect import csr_bus, wishbone
-from migen import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.fsm import FSM, NextState
class WB2LASMI(Module):
-from migen import *
+from litex.gen import *
-from migen.genlib.misc import chooser, WaitTimer
-from migen.genlib.record import Record
-from migen.genlib.fsm import FSM, NextState
+from litex.gen.genlib.misc import chooser, WaitTimer
+from litex.gen.genlib.record import Record
+from litex.gen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.stream import Sink, Source
projects / litex.git / commitdiff