radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0

It's not needed since it was fixed in the kernel.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index dcf206df216a1702d54272dd287a94c70018d9f3..6221f1cb83a5c9ae199c36101cd20005fdec54bd 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -116,8 +116,9 @@ void si_context_gfx_flush(void *context, unsigned flags,
 
        ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
                        SI_CONTEXT_PS_PARTIAL_FLUSH;
-       /* The kernel doesn't flush TC for VI correctly (need TC_WB_ACTION_ENA). */
-       if (ctx->b.chip_class == VI)
+
+       /* DRM 3.1.0 doesn't flush TC for VI correctly. */
+       if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
                ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
                                SI_CONTEXT_INV_VMEM_L1;