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diff --git a/openpower/ISA_WG/Board_letter_26mar2021.mdwn b/openpower/ISA_WG/Board_letter_26mar2021.mdwn
index f91dabce0f33a5e1d153291df6337cc0d23847d7..390df5b459c81c409e92c2b5192f7789d6120823 100644 (file)
--- a/openpower/ISA_WG/Board_letter_26mar2021.mdwn
+++ b/openpower/ISA_WG/Board_letter_26mar2021.mdwn
@@ -28,7 +28,7 @@ Dear OPF Board,
 
 As you know the LibreSOC team have been working for over 3 years on a massive conceptual upgrade to the OpenPOWER ISA, based on Cray-Style Vectors, which will modernise it for today's 3D and VPU workloads, with an incidental side-effect of upgrading it for future supercomputing needs over the next few decades in a clean and elegant fashion.
 
-RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA which is already so large that efforts to update it would do far more harm than good.  It goes without saying that over the past few decades, SIMD has been demonstrated to be harmful.
+RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA which is already so large that efforts to update it to suit modern 3D Shader and Video workloads would do far more harm than good.  It goes without saying that over the past few decades, SIMD has been demonstrated to be harmful.
 
 https://www.sigarch.org/simd-instructions-considered-harmful/