radv/gfx9: remove some leftover gfx6 descriptor setup.

We set this later in the non-gfx9 path, just remove these
bits from here.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index c0064c0a17050ee0132c8a29125af9434d232b05..8d3ff1a515ea416ac7d8308ee22c02dbb0d1e932 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -204,7 +204,6 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 {
        uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
        uint64_t va = gpu_address;
-       unsigned pitch = base_level_info->nblk_x * block_width;
        enum chip_class chip_class = device->physical_device->rad_info.chip_class;
        uint64_t meta_va = 0;
        if (chip_class >= GFX9) {
@@ -221,9 +220,6 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                        state[0] |= image->surface.tile_swizzle;
        state[1] &= C_008F14_BASE_ADDRESS_HI;
        state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
-       state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
-                                                            is_stencil));
-       state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
 
        if (chip_class >= VI) {
                state[6] &= C_008F28_COMPRESSION_EN;