#include "base/logging.hh"
#include "params/FastModelCortexA76x1.hh"
#include "sim/core.hh"
+#include "systemc/tlm_bridge/gem5_to_tlm.hh"
namespace FastModel
{
cntpnsirqWrapper(cntpnsirq, params.name + ".cntpnsirq", -1),
clockChanged(Iris::ClockEventName.c_str()),
clockPeriod(Iris::PeriodAttributeName.c_str()),
- gem5Cpu(Iris::Gem5CpuAttributeName.c_str())
+ gem5Cpu(Iris::Gem5CpuAttributeName.c_str()),
+ sendFunctional(Iris::SendFunctionalAttributeName.c_str())
{
clockRateControl.bind(clock_rate_s);
SC_METHOD(clockChangeHandler);
dont_initialize();
sensitive << clockChanged;
+
+ sendFunctional.value = [this](PacketPtr pkt) { sendFunc(pkt); };
+ add_attribute(sendFunctional);
+}
+
+void
+CortexA76x1::sendFunc(PacketPtr pkt)
+{
+ auto *trans = sc_gem5::packet2payload(pkt);
+ panic_if(scx_evs_CortexA76x1::amba->transport_dbg(*trans) !=
+ trans->get_data_length(), "Didn't send entire functional packet!");
+ trans->release();
}
Port &
#include "arch/arm/fastmodel/amba_ports.hh"
#include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh"
+#include "mem/port_proxy.hh"
#include "params/FastModelCortexA76x1.hh"
#include "scx_evs_CortexA76x1.h"
#include "systemc/ext/core/sc_event.hh"
sc_core::sc_event clockChanged;
sc_core::sc_attribute<Tick> clockPeriod;
sc_core::sc_attribute<::BaseCPU *> gem5Cpu;
+ sc_core::sc_attribute<PortProxy::SendFunctionalFunc> sendFunctional;
+
+ void sendFunc(PacketPtr pkt);
void clockChangeHandler();