def misoc_import(default, external, name):
if external:
try:
- del sys.modules[name] # force external path search
+ del sys.modules[name] # force external path search
except KeyError:
pass
loader = importlib.find_loader(name, [external])
rx_done.eq(0),
rx_r.eq(rx),
If(~rx_busy,
- If(~rx & rx_r, # look for start bit
+ If(~rx & rx_r, # look for start bit
rx_busy.eq(1),
rx_bitcount.eq(0),
)
If(uart_clk_rxen,
rx_bitcount.eq(rx_bitcount + 1),
If(rx_bitcount == 0,
- If(rx, # verify start bit
+ If(rx, # verify start bit
rx_busy.eq(0)
)
).Elif(rx_bitcount == 9,
rx_busy.eq(0),
- If(rx, # verify stop bit
+ If(rx, # verify stop bit
rx_data.eq(rx_reg),
rx_done.eq(1)
)
m, s = pty.openpty()
name = os.ttyname(s)
print("UART tty: "+name)
- time.sleep(0.5) # pause for user
+ time.sleep(0.5) # pause for user
f = open("/tmp/simserial", "w")
f.write(os.ttyname(s))
f.close()
class LASMIcon(Module):
def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
if phy_settings.memtype in ["SDR"]:
- burst_length = phy_settings.nphases*1 # command multiplication*SDR
+ burst_length = phy_settings.nphases*1 # command multiplication*SDR
elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
- burst_length = phy_settings.nphases*2 # command multiplication*DDR
+ burst_length = phy_settings.nphases*2 # command multiplication*DDR
address_align = log2_int(burst_length)
self.dfi = dfi.Interface(geom_settings.addressbits,
# Command steering
nop = CommandRequest(geom_settings.addressbits, geom_settings.bankbits)
- commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd] # nop must be 1st
+ commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd] # nop must be 1st
(STEER_NOP, STEER_CMD, STEER_REQ, STEER_REFRESH) = range(4)
steerer = _Steerer(commands, dfi)
self.submodules += steerer
steerer.sel[0].eq(STEER_REFRESH),
If(~refresher.req, NextState("READ"))
)
- fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
+ fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
fsm.finalize()
class Refresher(Module):
def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True):
self.req = Signal()
- self.ack = Signal() # 1st command 1 cycle after assertion of ack
+ self.ack = Signal() # 1st command 1 cycle after assertion of ack
self.cmd = CommandRequest(a, ba)
###
class Minicon(Module):
def __init__(self, phy_settings, geom_settings, timing_settings):
if phy_settings.memtype in ["SDR"]:
- burst_length = phy_settings.nphases*1 # command multiplication*SDR
+ burst_length = phy_settings.nphases*1 # command multiplication*SDR
elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
- burst_length = phy_settings.nphases*2 # command multiplication*DDR
+ burst_length = phy_settings.nphases*2 # command multiplication*DDR
address_align = log2_int(burst_length)
nbanks = range(2**geom_settings.bankbits)
class PhaseInjector(Module, AutoCSR):
def __init__(self, phase):
- self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
+ self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
self._command_issue = CSR()
self._address = CSRStorage(flen(phase.address))
self._baddress = CSRStorage(flen(phase.bank))
self.slave = dfi.Interface(addressbits, bankbits, databits, nphases)
self.master = dfi.Interface(addressbits, bankbits, databits, nphases)
- self._control = CSRStorage(4) # sel, cke, odt, reset_n
+ self._control = CSRStorage(4) # sel, cke, odt, reset_n
for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
mr2 |= rtt_wr << 9
return mr2
- mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
- mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
- mr2 = format_mr2(sdram_phy_settings.cwl, 2) # Rtt(WR) RZQ/4
+ mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
+ mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
+ mr2 = format_mr2(sdram_phy_settings.cwl, 2) # Rtt(WR) RZQ/4
mr3 = 0
init_sequence = [
def do_simulation(self, selfp):
dfip = selfp.ctler.dfi
for p in dfip.phases:
- if p.ras_n and not p.cas_n and not p.we_n: # write
+ if p.ras_n and not p.cas_n and not p.we_n: # write
d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64)
print(d)
if d != p.address//2 + p.bank*512 + self.open_row*2048:
print("**** ERROR ****")
- elif not p.ras_n and p.cas_n and p.we_n: # activate
+ elif not p.ras_n and p.cas_n and p.we_n: # activate
self.open_row = p.address
if __name__ == "__main__":
from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
-l2_size = 8192 # in bytes
+l2_size = 8192 # in bytes
def my_generator():
class SoC(Module):
csr_map = {
- "crg": 0, # user
- "uart_phy": 1, # provided by default (optional)
- "uart": 2, # provided by default (optional)
- "identifier": 3, # provided by default (optional)
- "timer0": 4, # provided by default (optional)
- "buttons": 5, # user
- "leds": 6, # user
+ "crg": 0, # user
+ "uart_phy": 1, # provided by default (optional)
+ "uart": 2, # provided by default (optional)
+ "identifier": 3, # provided by default (optional)
+ "timer0": 4, # provided by default (optional)
+ "buttons": 5, # user
+ "leds": 6, # user
}
interrupt_map = {
- "uart": 0,
- "timer0": 1,
+ "uart": 0,
+ "timer0": 1,
}
mem_map = {
- "rom": 0x00000000, # (shadow @0x80000000)
- "sram": 0x10000000, # (shadow @0x90000000)
- "main_ram": 0x40000000, # (shadow @0xc0000000)
- "csr": 0x60000000, # (shadow @0xe0000000)
+ "rom": 0x00000000, # (shadow @0x80000000)
+ "sram": 0x10000000, # (shadow @0x90000000)
+ "main_ram": 0x40000000, # (shadow @0xc0000000)
+ "csr": 0x60000000, # (shadow @0xe0000000)
}
def __init__(self, platform, clk_freq,
cpu_type="lm32", cpu_reset_address=0x00000000,
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
- self._memory_regions = [] # list of (name, origin, length)
- self._csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
- self._constants = [] # list of (name, value)
+ self._memory_regions = [] # list of (name, origin, length)
+ self._csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
+ self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
encoded_pixel = Signal(24)
self.comb += encoded_pixel.eq(Cat(self.b, self.g, self.r))
pack_factor = word_width//24
- assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
+ assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
pack_counter = Signal(max=pack_factor)
self.sync.pix += [
cur_word_valid.eq(0),
)
self.specials += Instance("PLL_ADV",
p_CLKFBOUT_MULT=10,
- p_CLKOUT0_DIVIDE=1, # pix10x
- p_CLKOUT1_DIVIDE=5, # pix2x
- p_CLKOUT2_DIVIDE=10, # pix
+ p_CLKOUT0_DIVIDE=1, # pix10x
+ p_CLKOUT1_DIVIDE=5, # pix2x
+ p_CLKOUT2_DIVIDE=10, # pix
p_COMPENSATION="INTERNAL",
i_CLKINSEL=1,
]
unpack_counter = Signal(max=pack_factor)
- assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
+ assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
self.sync.pix += [
unpack_counter.eq(unpack_counter + 1),
self.pix_hsync.eq(fifo.dout.hsync),
self.specials += [
Instance("PLL_ADV",
p_CLKFBOUT_MULT=10,
- p_CLKOUT0_DIVIDE=1, # pix10x
- p_CLKOUT1_DIVIDE=5, # pix2x
- p_CLKOUT2_DIVIDE=10, # pix
+ p_CLKOUT0_DIVIDE=1, # pix10x
+ p_CLKOUT1_DIVIDE=5, # pix2x
+ p_CLKOUT2_DIVIDE=10, # pix
p_COMPENSATION="INTERNAL",
i_CLKINSEL=1,
default_platform = "kc705"
csr_map = {
- "spiflash": 16,
- "ddrphy": 17,
+ "spiflash": 16,
+ "ddrphy": 17,
}
csr_map.update(SDRAMSoC.csr_map)
class MiniSoC(BaseSoC):
csr_map = {
- "ethphy": 18,
- "ethmac": 19,
+ "ethphy": 18,
+ "ethmac": 19,
}
csr_map.update(BaseSoC.csr_map)
interrupt_map = {
- "ethmac": 2,
+ "ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
- "ethmac": 0x30000000, # (shadow @0xb0000000)
+ "ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
- p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
- p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
+ p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
+ p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
)
self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
class BaseSoC(SDRAMSoC):
- default_platform = "mixxeo" # also supports m1
+ default_platform = "mixxeo" # also supports m1
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
class MiniSoC(BaseSoC):
csr_map = {
- "ethphy": 16,
- "ethmac": 17,
+ "ethphy": 16,
+ "ethmac": 17,
}
csr_map.update(BaseSoC.csr_map)
interrupt_map = {
- "ethmac": 2,
+ "ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
- "ethmac": 0x30000000, # (shadow @0xb0000000)
+ "ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
class FramebufferSoC(MiniSoC):
csr_map = {
- "fb": 18,
+ "fb": 18,
}
csr_map.update(MiniSoC.csr_map)
o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
- p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd
+ p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//8,
- p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl
- p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr
+ p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl
+ p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,
- p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
+ p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
reset = platform.request("user_btn")
default_platform = "pipistrello"
csr_map = {
- "spiflash": 16,
+ "spiflash": 16,
}
csr_map.update(SDRAMSoC.csr_map)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 75*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
- cpu_reset_address=0x170000, # 1.5 MB
+ cpu_reset_address=0x170000, # 1.5 MB
sdram_controller_settings=sdram_controller_settings,
**kwargs)
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
- p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
- p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
+ p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
+ p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
)
self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
default_platform = "papilio_pro"
csr_map = {
- "spiflash": 16,
+ "spiflash": 16,
}
csr_map.update(SDRAMSoC.csr_map)
class MiniSoC(BaseSoC):
csr_map = {
- "ethphy": 20,
- "ethmac": 21
+ "ethphy": 20,
+ "ethmac": 21
}
csr_map.update(BaseSoC.csr_map)
interrupt_map = {
- "ethmac": 2,
+ "ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
- "ethmac": 0x30000000, # (shadow @0xb0000000)
+ "ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
self.serial = serial.Serial(port, speed, timeout=0.25)
self.serial.flushOutput()
self.serial.flushInput()
- self.serial.close() # in case port was not correctly closed
+ self.serial.close() # in case port was not correctly closed
self.serial.open()
def close(self):
projects / litex.git / commitdiff