radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega

Copied from RadeonSI.

This fixes all CTS
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.clear.*

And some other ones which use the same format.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 5c53e8163760587171fa7ed13e0cc6b0fe4d6259..efd17e488966b8ff252b0479b9153bcc8cecf762 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -416,6 +416,12 @@ si_make_texture_descriptor(struct radv_device *device,
                data_format = 0;
        }
 
+       /* S8 with Z32 HTILE needs a special format. */
+       if (device->physical_device->rad_info.chip_class >= GFX9 &&
+           vk_format == VK_FORMAT_S8_UINT &&
+           image->tc_compatible_htile)
+               data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
+
        type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
                            is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
        if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {