minor clarify

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index e7bfb5d0cf77456e2d3d1a9e4f8894d92a2e3097..1e0264b83585c8742a6be0de797b65bd15f74ec5 100644 (file)
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -76,8 +76,8 @@ performance, CPU architects typically increase the width of registers
 (to 128-, 256-, 512-bit etc) for more partitions.\par Additionally,
 binary compatibility is an important feature, and thus each doubling
 of SIMD registers also expands the instruction set. The number of
-instructions quickly balloons and this can be seen in popular \ac{ISA},
-for example IA-32 expanding from 80 to about 1400 instructions since
+instructions quickly balloons and this can be seen in for example
+IA-32 expanding from 80 to about 1400 instructions since
 1978\cite{SIMD_HARM}.\par
 
 \subsection{Vector Architectures}