adffs test update (equiv_opt -multiclock).

diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
index 93c8bf52c75c87ba9282d58eb785ef20458ad58e..05e68caf7e91a6d02759be09648055a44b26025f 100644 (file)
--- a/tests/ice40/adffs.v
+++ b/tests/ice40/adffs.v
@@ -22,30 +22,26 @@ module adffn
             q <= d;
 endmodule
 
-module dffsr
+module dffs
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-       always @( posedge clk, posedge pre, posedge clr )
-               if ( clr )
-                       q <= 1'b0;
-               else if ( pre )
+       always @( posedge clk )
+               if ( pre )
                        q <= 1'b1;
                else
             q <= d;
 endmodule
 
-module ndffnsnr
+module ndffnr
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-       always @( negedge clk, negedge pre, negedge clr )
+       always @( negedge clk )
                if ( !clr )
                        q <= 1'b0;
-               else if ( !pre )
-                       q <= 1'b1;
                else
             q <= d;
 endmodule
@@ -58,7 +54,7 @@ input a,
 output b,b1,b2,b3
 );
 
-dffsr u_dffsr (
+dffs u_dffs (
         .clk (clk ),
         .clr (clr),
         .pre (pre),
@@ -66,7 +62,7 @@ dffsr u_dffsr (
         .q (b )
     );
 
-ndffnsnr u_ndffnsnr (
+ndffnr u_ndffnr (
         .clk (clk ),
         .clr (clr),
         .pre (pre),

diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index 14b251c5c5de762372ed15cfbfe42b719750787c..f82da6b145cb494d1d327592b3dcbf799b028c6e 100644 (file)
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,12 +1,11 @@
 read_verilog adffs.v
 proc
-async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFF
-select -assert-count 1 t:SB_DFFN
-select -assert-count 2 t:SB_DFFSR
-select -assert-count 7 t:SB_LUT4
-select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D
+select -assert-count 1 t:SB_DFFNSR
+select -assert-count 2 t:SB_DFFR
+select -assert-count 1 t:SB_DFFSS
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D