back.rtlil: handle reset_less domains.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 1836d75756171358a6b19db8b82e73e3a264a005..67ffdd3e8491e5bfe467a7c5b2dd670a521f5c68 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -515,7 +515,8 @@ def convert_fragment(builder, fragment, name, top):
         for domain, _ in fragment.iter_sync():
             cd = fragment.domains[domain]
             compiler_state.resolve_curr(cd.clk)
-            compiler_state.resolve_curr(cd.rst)
+            if cd.rst is not None:
+                compiler_state.resolve_curr(cd.rst)
 
         # Transform all subfragments to their respective cells. Transforming signals connected
         # to their ports into wires eagerly makes sure they get sensible (prefixed with submodule