Started to add support for O3 for sparc.

--HG--
extra : convert_revision : 3f94bda14024a09b9fbd7a5d13284d4987349ddf

diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index 44882e5ec20f2e0d4208148194f63d6bd4d0f92c..afbd4c533c3e4170ab8a3ca25bfecd47d88b9f35 100755 (executable)
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -59,13 +59,12 @@ elif env['TARGET_ISA'] == 'mips':
         mips/cpu_builder.cc
         ''')
 elif env['TARGET_ISA'] == 'sparc':
-    sys.exit('O3 CPU does not support Sparc')
-    #sources += Split('''
-    #    sparc/dyn_inst.cc
-    #    sparc/cpu.cc
-    #    sparc/thread_context.cc
-    #    sparc/cpu_builder.cc
-    #    ''')
+    sources += Split('''
+        sparc/dyn_inst.cc
+        sparc/cpu.cc
+        sparc/thread_context.cc
+        sparc/cpu_builder.cc
+        ''')
 else:
     sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
 

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 5f7caf79fdb88627070df0e224e0a88260691671..2795134934661195fd005e48656854f8e3cb7c06 100644 (file)
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -41,6 +41,10 @@
     template <class Impl> class MipsDynInst;
     struct MipsSimpleImpl;
     typedef MipsDynInst<MipsSimpleImpl> O3DynInst;
+#elif THE_ISA == SPARC_ISA
+    template <class Impl> class SparcDynInst;
+    struct SparcSimpleImpl;
+    typedef SparcDynInst<SparcSimpleImpl> O3DynInst;
 #else
     #error "O3DynInst not defined for this ISA"
 #endif